1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * ARC CPU startup Code !! 2 * This file is subject to the terms and conditions of the GNU General Public
>> 3 * License. See the file "COPYING" in the main directory of this archive
>> 4 * for more details.
4 * 5 *
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Sy !! 6 * Copyright (C) 1994, 1995 Waldorf Electronics
6 * !! 7 * Written by Ralf Baechle and Andreas Busse
7 * Vineetg: Dec 2007 !! 8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
8 * -Check if we are running on Simulator or o !! 9 * Copyright (C) 1996 Paul M. Antoine
9 * to skip certain things during boot on !! 10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
>> 11 * Further modifications by David S. Miller and Harald Koerfgen
>> 12 * Copyright (C) 1999 Silicon Graphics, Inc.
>> 13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
>> 14 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
10 */ 15 */
>> 16 #include <linux/init.h>
>> 17 #include <linux/threads.h>
11 18
12 #include <linux/linkage.h> !! 19 #include <asm/addrspace.h>
13 #include <asm/asm-offsets.h> !! 20 #include <asm/asm.h>
14 #include <asm/entry.h> !! 21 #include <asm/asmmacro.h>
15 #include <asm/arcregs.h> <<
16 #include <asm/cache.h> <<
17 #include <asm/dsp-impl.h> <<
18 #include <asm/irqflags.h> 22 #include <asm/irqflags.h>
19 !! 23 #include <asm/regdef.h>
20 .macro CPU_EARLY_SETUP !! 24 #include <asm/mipsregs.h>
21 !! 25 #include <asm/stackframe.h>
22 ; Setting up Vectror Table (in case ex !! 26
23 sr @_int_vec_base_lds, [AUX_INTR_ !! 27 #include <kernel-entry-init.h>
24 !! 28
25 ; Disable I-cache/D-cache if kernel so !! 29 /*
26 lr r5, [ARC_REG_IC_BCR] !! 30 * For the moment disable interrupts, mark the kernel mode and
27 breq r5, 0, 1f ; I$ d !! 31 * set ST0_KX so that the CPU does not spit fire when using
28 lr r5, [ARC_REG_IC_CTRL] !! 32 * 64-bit addresses. A full initialization of the CPU's status
29 #ifdef CONFIG_ARC_HAS_ICACHE !! 33 * register is done later in per_cpu_trap_init().
30 bclr r5, r5, 0 ; 0 - !! 34 */
>> 35 .macro setup_c0_status set clr
>> 36 .set push
>> 37 mfc0 t0, CP0_STATUS
>> 38 or t0, ST0_CU0|\set|0x1f|\clr
>> 39 xor t0, 0x1f|\clr
>> 40 mtc0 t0, CP0_STATUS
>> 41 .set noreorder
>> 42 sll zero,3 # ehb
>> 43 .set pop
>> 44 .endm
>> 45
>> 46 .macro setup_c0_status_pri
>> 47 #ifdef CONFIG_64BIT
>> 48 setup_c0_status ST0_KX 0
31 #else 49 #else
32 bset r5, r5, 0 ; I$ e !! 50 setup_c0_status 0 0
33 #endif 51 #endif
34 sr r5, [ARC_REG_IC_CTRL] !! 52 .endm
35 53
36 1: !! 54 .macro setup_c0_status_sec
37 lr r5, [ARC_REG_DC_BCR] !! 55 #ifdef CONFIG_64BIT
38 breq r5, 0, 1f ; D$ d !! 56 setup_c0_status ST0_KX ST0_BEV
39 lr r5, [ARC_REG_DC_CTRL] <<
40 bclr r5, r5, 6 ; Inva <<
41 #ifdef CONFIG_ARC_HAS_DCACHE <<
42 bclr r5, r5, 0 ; Enab <<
43 #else 57 #else
44 bset r5, r5, 0 ; Disa !! 58 setup_c0_status 0 ST0_BEV
45 #endif 59 #endif
46 sr r5, [ARC_REG_DC_CTRL] !! 60 .endm
47 <<
48 1: <<
49 61
50 #ifdef CONFIG_ISA_ARCV2 !! 62 #ifndef CONFIG_NO_EXCEPT_FILL
51 ; Unaligned access is disabled at rese !! 63 /*
52 ; gcc 7.3.1 (ARC GNU 2018.03) onwards !! 64 * Reserved space for exception handlers.
53 ; by default !! 65 * Necessary for machines which link their kernels at KSEG0.
54 lr r5, [status32] !! 66 */
55 #ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS !! 67 .fill 0x400
56 bset r5, r5, STATUS_AD_BIT <<
57 #else <<
58 ; Although disabled at reset, bootload <<
59 bclr r5, r5, STATUS_AD_BIT <<
60 #endif 68 #endif
61 kflag r5 <<
62 69
63 #ifdef CONFIG_ARC_LPB_DISABLE !! 70 EXPORT(_stext)
64 lr r5, [ARC_REG_LPB_BUILD] <<
65 breq r5, 0, 1f ; LPB <<
66 mov r5, 1 <<
67 sr r5, [ARC_REG_LPB_CTRL] <<
68 1: <<
69 #endif /* CONFIG_ARC_LPB_DISABLE */ <<
70 71
71 /* On HSDK, CCMs need to remapped supe !! 72 #ifdef CONFIG_BOOT_RAW
72 #ifdef CONFIG_ARC_SOC_HSDK !! 73 /*
73 mov r6, 0x60000000 !! 74 * Give us a fighting chance of running if execution beings at the
74 lr r5, [ARC_REG_ICCM_BUILD] !! 75 * kernel load address. This is needed because this platform does
75 breq r5, 0, 1f !! 76 * not have a ELF loader yet.
76 sr r6, [ARC_REG_AUX_ICCM] !! 77 */
>> 78 FEXPORT(__kernel_entry)
>> 79 j kernel_entry
>> 80 #endif /* CONFIG_BOOT_RAW */
>> 81
>> 82 __REF
>> 83
>> 84 NESTED(kernel_entry, 16, sp) # kernel entry point
>> 85
>> 86 kernel_entry_setup # cpu specific setup
>> 87
>> 88 setup_c0_status_pri
>> 89
>> 90 /* We might not get launched at the address the kernel is linked to,
>> 91 so we jump there. */
>> 92 PTR_LA t0, 0f
>> 93 jr t0
>> 94 0:
>> 95
>> 96 #ifdef CONFIG_USE_OF
>> 97 #if defined(CONFIG_MIPS_RAW_APPENDED_DTB) || \
>> 98 defined(CONFIG_MIPS_ELF_APPENDED_DTB)
>> 99
>> 100 PTR_LA t2, __appended_dtb
>> 101
>> 102 #ifdef CONFIG_CPU_BIG_ENDIAN
>> 103 li t1, 0xd00dfeed
>> 104 #else /* !CONFIG_CPU_BIG_ENDIAN */
>> 105 li t1, 0xedfe0dd0
>> 106 #endif /* !CONFIG_CPU_BIG_ENDIAN */
>> 107 lw t0, (t2)
>> 108 beq t0, t1, dtb_found
>> 109 #endif /* CONFIG_MIPS_RAW_APPENDED_DTB || CONFIG_MIPS_ELF_APPENDED_DTB */
>> 110 li t1, -2
>> 111 move t2, a1
>> 112 beq a0, t1, dtb_found
>> 113
>> 114 li t2, 0
>> 115 dtb_found:
>> 116 #endif /* CONFIG_USE_OF */
>> 117 PTR_LA t0, __bss_start # clear .bss
>> 118 LONG_S zero, (t0)
>> 119 PTR_LA t1, __bss_stop - LONGSIZE
77 1: 120 1:
78 lr r5, [ARC_REG_DCCM_BUILD] !! 121 PTR_ADDIU t0, LONGSIZE
79 breq r5, 0, 2f !! 122 LONG_S zero, (t0)
80 sr r6, [ARC_REG_AUX_DCCM] !! 123 bne t0, t1, 1b
81 2: !! 124
82 #endif /* CONFIG_ARC_SOC_HSDK */ !! 125 LONG_S a0, fw_arg0 # firmware arguments
83 !! 126 LONG_S a1, fw_arg1
84 #endif /* CONFIG_ISA_ARCV2 */ !! 127 LONG_S a2, fw_arg2
85 !! 128 LONG_S a3, fw_arg3
86 ; Config DSP_CTRL properly, so kernel <<
87 ; multiply-accumulate, and divide oper <<
88 DSP_EARLY_INIT <<
89 .endm <<
90 <<
91 .section .init.text, "ax",@progbits <<
92 <<
93 ;--------------------------------------------- <<
94 ; Default Reset Handler (jumped into from Rese <<
95 ; - Don't clobber r0,r1,r2 as they might have <<
96 ; - Platforms can override this weak version i <<
97 ;--------------------------------------------- <<
98 WEAK(res_service) <<
99 j stext <<
100 END(res_service) <<
101 <<
102 ;--------------------------------------------- <<
103 ; Kernel Entry point <<
104 ;--------------------------------------------- <<
105 ENTRY(stext) <<
106 <<
107 CPU_EARLY_SETUP <<
108 <<
109 #ifdef CONFIG_SMP <<
110 GET_CPU_ID r5 <<
111 cmp r5, 0 <<
112 mov.nz r0, r5 <<
113 bz .Lmaster_proceed <<
114 <<
115 ; Non-Masters wait for Master to boot <<
116 ; when they resume, tail-call to entry <<
117 mov blink, @first_lines_of_seconda <<
118 j arc_platform_smp_wait_to_boot <<
119 129
120 .Lmaster_proceed: !! 130 #ifdef CONFIG_USE_OF
>> 131 LONG_S t2, fw_passed_dtb
121 #endif 132 #endif
122 133
123 ; Clear BSS before updating any global !! 134 MTC0 zero, CP0_CONTEXT # clear context register
124 ; XXX: use ZOL here !! 135 PTR_LA $28, init_thread_union
125 mov r5, __bss_start !! 136 /* Set the SP after an empty pt_regs. */
126 sub r6, __bss_stop, r5 !! 137 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
127 lsr.f lp_count, r6, 2 !! 138 PTR_ADDU sp, $28
128 lpnz 1f !! 139 back_to_back_c0_hazard
129 st.ab 0, [r5, 4] !! 140 set_saved_sp sp, t0, t1
130 1: !! 141 PTR_SUBU sp, 4 * SZREG # init stack pointer
131 !! 142
132 ; Uboot - kernel ABI !! 143 #ifdef CONFIG_RELOCATABLE
133 ; r0 = [0] No uboot interaction, [1 !! 144 /* Copy kernel and apply the relocations */
134 ; r1 = magic number (always zero as !! 145 jal relocate_kernel
135 ; r2 = pointer to uboot provided cm !! 146
136 ; These are handled later in handle_ub !! 147 /* Repoint the sp into the new kernel image */
137 st r0, [@uboot_tag] !! 148 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
138 st r1, [@uboot_magic] !! 149 PTR_ADDU sp, $28
139 st r2, [@uboot_arg] !! 150 set_saved_sp sp, t0, t1
140 !! 151 PTR_SUBU sp, 4 * SZREG # init stack pointer
141 ; setup "current" tsk and optionally c !! 152
142 mov r9, @init_task !! 153 /*
143 SET_CURR_TASK_ON_CPU r9, r0 ; r9 = !! 154 * relocate_kernel returns the entry point either
144 !! 155 * in the relocated kernel or the original if for
145 ; setup stack (fp, sp) !! 156 * some reason relocation failed - jump there now
146 mov fp, 0 !! 157 * with instruction hazard barrier because of the
147 !! 158 * newly sync'd icache.
148 ; tsk->thread_info is really a PAGE, w !! 159 */
149 GET_TSK_STACK_BASE r9, sp ; r9 = !! 160 jr.hb v0
150 !! 161 #else /* !CONFIG_RELOCATABLE */
151 j start_kernel ; "C" entry po !! 162 j start_kernel
152 END(stext) !! 163 #endif /* !CONFIG_RELOCATABLE */
>> 164 END(kernel_entry)
153 165
154 #ifdef CONFIG_SMP 166 #ifdef CONFIG_SMP
155 ;--------------------------------------------- !! 167 /*
156 ; First lines of code run by secondary bef !! 168 * SMP slave cpus entry point. Board specific code for bootstrap calls this
157 ;--------------------------------------------- !! 169 * function after setting up the stack and gp registers.
158 .section .text, "ax",@progbits !! 170 */
159 ENTRY(first_lines_of_secondary) !! 171 NESTED(smp_bootstrap, 16, sp)
160 !! 172 smp_slave_setup
161 ; setup per-cpu idle task as "current" !! 173 setup_c0_status_sec
162 ld r0, [@secondary_idle_tsk] !! 174 j start_secondary
163 SET_CURR_TASK_ON_CPU r0, r1 !! 175 END(smp_bootstrap)
164 !! 176 #endif /* CONFIG_SMP */
165 ; setup stack (fp, sp) <<
166 mov fp, 0 <<
167 <<
168 ; set its stack base to tsk->thread_in <<
169 GET_TSK_STACK_BASE r0, sp <<
170 <<
171 j start_kernel_secondary <<
172 END(first_lines_of_secondary) <<
173 #endif <<
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