1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Sy !! 2 * This file is subject to the terms and conditions of the GNU General Public
>> 3 * License. See the file "COPYING" in the main directory of this archive
>> 4 * for more details.
>> 5 *
>> 6 * Copyright (C) 1998, 1999, 2000 by Ralf Baechle
>> 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
>> 8 * Copyright (C) 2007 by Maciej W. Rozycki
>> 9 * Copyright (C) 2011, 2012 MIPS Technologies, Inc.
4 */ 10 */
>> 11 #include <asm/asm.h>
>> 12 #include <asm/asm-offsets.h>
>> 13 #include <asm/regdef.h>
>> 14
>> 15 #if LONGSIZE == 4
>> 16 #define LONG_S_L swl
>> 17 #define LONG_S_R swr
>> 18 #else
>> 19 #define LONG_S_L sdl
>> 20 #define LONG_S_R sdr
>> 21 #endif
>> 22
>> 23 #ifdef CONFIG_CPU_MICROMIPS
>> 24 #define STORSIZE (LONGSIZE * 2)
>> 25 #define STORMASK (STORSIZE - 1)
>> 26 #define FILL64RG t8
>> 27 #define FILLPTRG t7
>> 28 #undef LONG_S
>> 29 #define LONG_S LONG_SP
>> 30 #else
>> 31 #define STORSIZE LONGSIZE
>> 32 #define STORMASK LONGMASK
>> 33 #define FILL64RG a1
>> 34 #define FILLPTRG t0
>> 35 #endif
>> 36
>> 37 #define EX(insn,reg,addr,handler) \
>> 38 9: insn reg, addr; \
>> 39 .section __ex_table,"a"; \
>> 40 PTR 9b, handler; \
>> 41 .previous
>> 42
>> 43 .macro f_fill64 dst, offset, val, fixup
>> 44 EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup)
>> 45 EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup)
>> 46 EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup)
>> 47 EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup)
>> 48 #if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS))
>> 49 EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup)
>> 50 EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup)
>> 51 EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup)
>> 52 EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup)
>> 53 #endif
>> 54 #if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
>> 55 EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup)
>> 56 EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup)
>> 57 EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
>> 58 EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
>> 59 EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
>> 60 EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
>> 61 EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
>> 62 EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
>> 63 #endif
>> 64 .endm
5 65
6 #include <linux/linkage.h> !! 66 /*
7 !! 67 * memset(void *s, int c, size_t n)
8 #define SMALL 7 /* Must be at least 6 to dea !! 68 *
9 !! 69 * a0: start of area to clear
10 ENTRY_CFI(memset) !! 70 * a1: char to fill with
11 mov_s r4,r0 !! 71 * a2: size of area to clear
12 or r12,r0,r2 !! 72 */
13 bmsk.f r12,r12,1 !! 73 .set noreorder
14 extb_s r1,r1 !! 74 .align 5
15 asl r3,r1,8 !! 75 LEAF(memset)
16 beq.d .Laligned !! 76 beqz a1, 1f
17 or_s r1,r1,r3 !! 77 move v0, a0 /* result */
18 brls r2,SMALL,.Ltiny !! 78
19 add r3,r2,r0 !! 79 andi a1, 0xff /* spread fillword */
20 stb r1,[r3,-1] !! 80 LONG_SLL t1, a1, 8
21 bclr_s r3,r3,0 !! 81 or a1, t1
22 stw r1,[r3,-2] !! 82 LONG_SLL t1, a1, 16
23 bmsk.f r12,r0,1 !! 83 #if LONGSIZE == 8
24 add_s r2,r2,r12 !! 84 or a1, t1
25 sub.ne r2,r2,4 !! 85 LONG_SLL t1, a1, 32
26 stb.ab r1,[r4,1] !! 86 #endif
27 and r4,r4,-2 !! 87 or a1, t1
28 stw.ab r1,[r4,2] !! 88 1:
29 and r4,r4,-4 !! 89
30 .Laligned: ; This code address should be !! 90 FEXPORT(__bzero)
31 asl r3,r1,16 !! 91 sltiu t0, a2, STORSIZE /* very small region? */
32 lsr.f lp_count,r2,2 !! 92 bnez t0, .Lsmall_memset
33 or_s r1,r1,r3 !! 93 andi t0, a0, STORMASK /* aligned? */
34 lpne .Loop_end !! 94
35 st.ab r1,[r4,4] !! 95 #ifdef CONFIG_CPU_MICROMIPS
36 .Loop_end: !! 96 move t8, a1 /* used by 'swp' instruction */
37 j_s [blink] !! 97 move t9, a1
38 !! 98 #endif
39 .balign 4 !! 99 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
40 .Ltiny: !! 100 beqz t0, 1f
41 mov.f lp_count,r2 !! 101 PTR_SUBU t0, STORSIZE /* alignment in bytes */
42 lpne .Ltiny_end !! 102 #else
43 stb.ab r1,[r4,1] !! 103 .set noat
44 .Ltiny_end: !! 104 li AT, STORSIZE
45 j_s [blink] !! 105 beqz t0, 1f
46 END_CFI(memset) !! 106 PTR_SUBU t0, AT /* alignment in bytes */
47 !! 107 .set at
48 ; memzero: @r0 = mem, @r1 = size_t !! 108 #endif
49 ; memset: @r0 = mem, @r1 = char, @r2 = size_t !! 109
50 !! 110 R10KCBARRIER(0(ra))
51 ENTRY_CFI(memzero) !! 111 #ifdef __MIPSEB__
52 ; adjust bzero args to memset args !! 112 EX(LONG_S_L, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
53 mov r2, r1 !! 113 #endif
54 mov r1, 0 !! 114 #ifdef __MIPSEL__
55 b memset ;tail call so need to tinker !! 115 EX(LONG_S_R, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
56 END_CFI(memzero) !! 116 #endif
>> 117 PTR_SUBU a0, t0 /* long align ptr */
>> 118 PTR_ADDU a2, t0 /* correct size */
>> 119
>> 120 1: ori t1, a2, 0x3f /* # of full blocks */
>> 121 xori t1, 0x3f
>> 122 beqz t1, .Lmemset_partial /* no block to fill */
>> 123 andi t0, a2, 0x40-STORSIZE
>> 124
>> 125 PTR_ADDU t1, a0 /* end address */
>> 126 .set reorder
>> 127 1: PTR_ADDIU a0, 64
>> 128 R10KCBARRIER(0(ra))
>> 129 f_fill64 a0, -64, FILL64RG, .Lfwd_fixup
>> 130 bne t1, a0, 1b
>> 131 .set noreorder
>> 132
>> 133 .Lmemset_partial:
>> 134 R10KCBARRIER(0(ra))
>> 135 PTR_LA t1, 2f /* where to start */
>> 136 #ifdef CONFIG_CPU_MICROMIPS
>> 137 LONG_SRL t7, t0, 1
>> 138 #endif
>> 139 #if LONGSIZE == 4
>> 140 PTR_SUBU t1, FILLPTRG
>> 141 #else
>> 142 .set noat
>> 143 LONG_SRL AT, FILLPTRG, 1
>> 144 PTR_SUBU t1, AT
>> 145 .set at
>> 146 #endif
>> 147 jr t1
>> 148 PTR_ADDU a0, t0 /* dest ptr */
>> 149
>> 150 .set push
>> 151 .set noreorder
>> 152 .set nomacro
>> 153 f_fill64 a0, -64, FILL64RG, .Lpartial_fixup /* ... but first do longs ... */
>> 154 2: .set pop
>> 155 andi a2, STORMASK /* At most one long to go */
>> 156
>> 157 beqz a2, 1f
>> 158 PTR_ADDU a0, a2 /* What's left */
>> 159 R10KCBARRIER(0(ra))
>> 160 #ifdef __MIPSEB__
>> 161 EX(LONG_S_R, a1, -1(a0), .Llast_fixup)
>> 162 #endif
>> 163 #ifdef __MIPSEL__
>> 164 EX(LONG_S_L, a1, -1(a0), .Llast_fixup)
>> 165 #endif
>> 166 1: jr ra
>> 167 move a2, zero
>> 168
>> 169 .Lsmall_memset:
>> 170 beqz a2, 2f
>> 171 PTR_ADDU t1, a0, a2
>> 172
>> 173 1: PTR_ADDIU a0, 1 /* fill bytewise */
>> 174 R10KCBARRIER(0(ra))
>> 175 bne t1, a0, 1b
>> 176 sb a1, -1(a0)
>> 177
>> 178 2: jr ra /* done */
>> 179 move a2, zero
>> 180 END(memset)
>> 181
>> 182 .Lfirst_fixup:
>> 183 jr ra
>> 184 nop
>> 185
>> 186 .Lfwd_fixup:
>> 187 PTR_L t0, TI_TASK($28)
>> 188 andi a2, 0x3f
>> 189 LONG_L t0, THREAD_BUADDR(t0)
>> 190 LONG_ADDU a2, t1
>> 191 jr ra
>> 192 LONG_SUBU a2, t0
>> 193
>> 194 .Lpartial_fixup:
>> 195 PTR_L t0, TI_TASK($28)
>> 196 andi a2, STORMASK
>> 197 LONG_L t0, THREAD_BUADDR(t0)
>> 198 LONG_ADDU a2, t1
>> 199 jr ra
>> 200 LONG_SUBU a2, t0
>> 201
>> 202 .Llast_fixup:
>> 203 jr ra
>> 204 andi v1, a2, STORMASK
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