1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Sy !! 2 * This file is subject to the terms and conditions of the GNU General Public
>> 3 * License. See the file "COPYING" in the main directory of this archive
>> 4 * for more details.
>> 5 *
>> 6 * Copyright (C) 1998, 1999, 2000 by Ralf Baechle
>> 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
>> 8 * Copyright (C) 2007 by Maciej W. Rozycki
>> 9 * Copyright (C) 2011, 2012 MIPS Technologies, Inc.
4 */ 10 */
>> 11 #include <asm/asm.h>
>> 12 #include <asm/asm-offsets.h>
>> 13 #include <asm/export.h>
>> 14 #include <asm/regdef.h>
5 15
6 #include <linux/linkage.h> !! 16 #if LONGSIZE == 4
>> 17 #define LONG_S_L swl
>> 18 #define LONG_S_R swr
>> 19 #else
>> 20 #define LONG_S_L sdl
>> 21 #define LONG_S_R sdr
>> 22 #endif
7 23
8 #define SMALL 7 /* Must be at least 6 to dea !! 24 #ifdef CONFIG_CPU_MICROMIPS
>> 25 #define STORSIZE (LONGSIZE * 2)
>> 26 #define STORMASK (STORSIZE - 1)
>> 27 #define FILL64RG t8
>> 28 #define FILLPTRG t7
>> 29 #undef LONG_S
>> 30 #define LONG_S LONG_SP
>> 31 #else
>> 32 #define STORSIZE LONGSIZE
>> 33 #define STORMASK LONGMASK
>> 34 #define FILL64RG a1
>> 35 #define FILLPTRG t0
>> 36 #endif
9 37
10 ENTRY_CFI(memset) !! 38 #define LEGACY_MODE 1
11 mov_s r4,r0 !! 39 #define EVA_MODE 2
12 or r12,r0,r2 !! 40
13 bmsk.f r12,r12,1 !! 41 /*
14 extb_s r1,r1 !! 42 * No need to protect it with EVA #ifdefery. The generated block of code
15 asl r3,r1,8 !! 43 * will never be assembled if EVA is not enabled.
16 beq.d .Laligned !! 44 */
17 or_s r1,r1,r3 !! 45 #define __EVAFY(insn, reg, addr) __BUILD_EVA_INSN(insn##e, reg, addr)
18 brls r2,SMALL,.Ltiny !! 46 #define ___BUILD_EVA_INSN(insn, reg, addr) __EVAFY(insn, reg, addr)
19 add r3,r2,r0 !! 47
20 stb r1,[r3,-1] !! 48 #define EX(insn,reg,addr,handler) \
21 bclr_s r3,r3,0 !! 49 .if \mode == LEGACY_MODE; \
22 stw r1,[r3,-2] !! 50 9: insn reg, addr; \
23 bmsk.f r12,r0,1 !! 51 .else; \
24 add_s r2,r2,r12 !! 52 9: ___BUILD_EVA_INSN(insn, reg, addr); \
25 sub.ne r2,r2,4 !! 53 .endif; \
26 stb.ab r1,[r4,1] !! 54 .section __ex_table,"a"; \
27 and r4,r4,-2 !! 55 PTR 9b, handler; \
28 stw.ab r1,[r4,2] !! 56 .previous
29 and r4,r4,-4 !! 57
30 .Laligned: ; This code address should be !! 58 .macro f_fill64 dst, offset, val, fixup, mode
31 asl r3,r1,16 !! 59 EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup)
32 lsr.f lp_count,r2,2 !! 60 EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup)
33 or_s r1,r1,r3 !! 61 EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup)
34 lpne .Loop_end !! 62 EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup)
35 st.ab r1,[r4,4] !! 63 #if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS))
36 .Loop_end: !! 64 EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup)
37 j_s [blink] !! 65 EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup)
38 !! 66 EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup)
39 .balign 4 !! 67 EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup)
40 .Ltiny: !! 68 #endif
41 mov.f lp_count,r2 !! 69 #if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
42 lpne .Ltiny_end !! 70 EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup)
43 stb.ab r1,[r4,1] !! 71 EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup)
44 .Ltiny_end: !! 72 EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
45 j_s [blink] !! 73 EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
46 END_CFI(memset) !! 74 EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
47 !! 75 EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
48 ; memzero: @r0 = mem, @r1 = size_t !! 76 EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
49 ; memset: @r0 = mem, @r1 = char, @r2 = size_t !! 77 EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
50 !! 78 #endif
51 ENTRY_CFI(memzero) !! 79 .endm
52 ; adjust bzero args to memset args !! 80
53 mov r2, r1 !! 81 .set noreorder
54 mov r1, 0 !! 82 .align 5
55 b memset ;tail call so need to tinker !! 83
56 END_CFI(memzero) !! 84 /*
>> 85 * Macro to generate the __bzero{,_user} symbol
>> 86 * Arguments:
>> 87 * mode: LEGACY_MODE or EVA_MODE
>> 88 */
>> 89 .macro __BUILD_BZERO mode
>> 90 /* Initialize __memset if this is the first time we call this macro */
>> 91 .ifnotdef __memset
>> 92 .set __memset, 1
>> 93 .hidden __memset /* Make sure it does not leak */
>> 94 .endif
>> 95
>> 96 sltiu t0, a2, STORSIZE /* very small region? */
>> 97 bnez t0, .Lsmall_memset\@
>> 98 andi t0, a0, STORMASK /* aligned? */
>> 99
>> 100 #ifdef CONFIG_CPU_MICROMIPS
>> 101 move t8, a1 /* used by 'swp' instruction */
>> 102 move t9, a1
>> 103 #endif
>> 104 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
>> 105 beqz t0, 1f
>> 106 PTR_SUBU t0, STORSIZE /* alignment in bytes */
>> 107 #else
>> 108 .set noat
>> 109 li AT, STORSIZE
>> 110 beqz t0, 1f
>> 111 PTR_SUBU t0, AT /* alignment in bytes */
>> 112 .set at
>> 113 #endif
>> 114
>> 115 #ifndef CONFIG_CPU_MIPSR6
>> 116 R10KCBARRIER(0(ra))
>> 117 #ifdef __MIPSEB__
>> 118 EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
>> 119 #else
>> 120 EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
>> 121 #endif
>> 122 PTR_SUBU a0, t0 /* long align ptr */
>> 123 PTR_ADDU a2, t0 /* correct size */
>> 124
>> 125 #else /* CONFIG_CPU_MIPSR6 */
>> 126 #define STORE_BYTE(N) \
>> 127 EX(sb, a1, N(a0), .Lbyte_fixup\@); \
>> 128 beqz t0, 0f; \
>> 129 PTR_ADDU t0, 1;
>> 130
>> 131 PTR_ADDU a2, t0 /* correct size */
>> 132 PTR_ADDU t0, 1
>> 133 STORE_BYTE(0)
>> 134 STORE_BYTE(1)
>> 135 #if LONGSIZE == 4
>> 136 EX(sb, a1, 2(a0), .Lbyte_fixup\@)
>> 137 #else
>> 138 STORE_BYTE(2)
>> 139 STORE_BYTE(3)
>> 140 STORE_BYTE(4)
>> 141 STORE_BYTE(5)
>> 142 EX(sb, a1, 6(a0), .Lbyte_fixup\@)
>> 143 #endif
>> 144 0:
>> 145 ori a0, STORMASK
>> 146 xori a0, STORMASK
>> 147 PTR_ADDIU a0, STORSIZE
>> 148 #endif /* CONFIG_CPU_MIPSR6 */
>> 149 1: ori t1, a2, 0x3f /* # of full blocks */
>> 150 xori t1, 0x3f
>> 151 beqz t1, .Lmemset_partial\@ /* no block to fill */
>> 152 andi t0, a2, 0x40-STORSIZE
>> 153
>> 154 PTR_ADDU t1, a0 /* end address */
>> 155 .set reorder
>> 156 1: PTR_ADDIU a0, 64
>> 157 R10KCBARRIER(0(ra))
>> 158 f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
>> 159 bne t1, a0, 1b
>> 160 .set noreorder
>> 161
>> 162 .Lmemset_partial\@:
>> 163 R10KCBARRIER(0(ra))
>> 164 PTR_LA t1, 2f /* where to start */
>> 165 #ifdef CONFIG_CPU_MICROMIPS
>> 166 LONG_SRL t7, t0, 1
>> 167 #endif
>> 168 #if LONGSIZE == 4
>> 169 PTR_SUBU t1, FILLPTRG
>> 170 #else
>> 171 .set noat
>> 172 LONG_SRL AT, FILLPTRG, 1
>> 173 PTR_SUBU t1, AT
>> 174 .set at
>> 175 #endif
>> 176 jr t1
>> 177 PTR_ADDU a0, t0 /* dest ptr */
>> 178
>> 179 .set push
>> 180 .set noreorder
>> 181 .set nomacro
>> 182 /* ... but first do longs ... */
>> 183 f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
>> 184 2: .set pop
>> 185 andi a2, STORMASK /* At most one long to go */
>> 186
>> 187 beqz a2, 1f
>> 188 #ifndef CONFIG_CPU_MIPSR6
>> 189 PTR_ADDU a0, a2 /* What's left */
>> 190 R10KCBARRIER(0(ra))
>> 191 #ifdef __MIPSEB__
>> 192 EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
>> 193 #else
>> 194 EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
>> 195 #endif
>> 196 #else
>> 197 PTR_SUBU t0, $0, a2
>> 198 move a2, zero /* No remaining longs */
>> 199 PTR_ADDIU t0, 1
>> 200 STORE_BYTE(0)
>> 201 STORE_BYTE(1)
>> 202 #if LONGSIZE == 4
>> 203 EX(sb, a1, 2(a0), .Lbyte_fixup\@)
>> 204 #else
>> 205 STORE_BYTE(2)
>> 206 STORE_BYTE(3)
>> 207 STORE_BYTE(4)
>> 208 STORE_BYTE(5)
>> 209 EX(sb, a1, 6(a0), .Lbyte_fixup\@)
>> 210 #endif
>> 211 0:
>> 212 #endif
>> 213 1: jr ra
>> 214 move a2, zero
>> 215
>> 216 .Lsmall_memset\@:
>> 217 beqz a2, 2f
>> 218 PTR_ADDU t1, a0, a2
>> 219
>> 220 1: PTR_ADDIU a0, 1 /* fill bytewise */
>> 221 R10KCBARRIER(0(ra))
>> 222 bne t1, a0, 1b
>> 223 EX(sb, a1, -1(a0), .Lsmall_fixup\@)
>> 224
>> 225 2: jr ra /* done */
>> 226 move a2, zero
>> 227 .if __memset == 1
>> 228 END(memset)
>> 229 .set __memset, 0
>> 230 .hidden __memset
>> 231 .endif
>> 232
>> 233 #ifdef CONFIG_CPU_MIPSR6
>> 234 .Lbyte_fixup\@:
>> 235 PTR_SUBU a2, t0
>> 236 jr ra
>> 237 PTR_ADDIU a2, 1
>> 238 #endif /* CONFIG_CPU_MIPSR6 */
>> 239
>> 240 .Lfirst_fixup\@:
>> 241 jr ra
>> 242 nop
>> 243
>> 244 .Lfwd_fixup\@:
>> 245 PTR_L t0, TI_TASK($28)
>> 246 andi a2, 0x3f
>> 247 LONG_L t0, THREAD_BUADDR(t0)
>> 248 LONG_ADDU a2, t1
>> 249 jr ra
>> 250 LONG_SUBU a2, t0
>> 251
>> 252 .Lpartial_fixup\@:
>> 253 PTR_L t0, TI_TASK($28)
>> 254 andi a2, STORMASK
>> 255 LONG_L t0, THREAD_BUADDR(t0)
>> 256 LONG_ADDU a2, a0
>> 257 jr ra
>> 258 LONG_SUBU a2, t0
>> 259
>> 260 .Llast_fixup\@:
>> 261 jr ra
>> 262 nop
>> 263
>> 264 .Lsmall_fixup\@:
>> 265 .set reorder
>> 266 PTR_SUBU a2, t1, a0
>> 267 PTR_ADDIU a2, 1
>> 268 jr ra
>> 269 .set noreorder
>> 270
>> 271 .endm
>> 272
>> 273 /*
>> 274 * memset(void *s, int c, size_t n)
>> 275 *
>> 276 * a0: start of area to clear
>> 277 * a1: char to fill with
>> 278 * a2: size of area to clear
>> 279 */
>> 280
>> 281 LEAF(memset)
>> 282 EXPORT_SYMBOL(memset)
>> 283 beqz a1, 1f
>> 284 move v0, a0 /* result */
>> 285
>> 286 andi a1, 0xff /* spread fillword */
>> 287 LONG_SLL t1, a1, 8
>> 288 or a1, t1
>> 289 LONG_SLL t1, a1, 16
>> 290 #if LONGSIZE == 8
>> 291 or a1, t1
>> 292 LONG_SLL t1, a1, 32
>> 293 #endif
>> 294 or a1, t1
>> 295 1:
>> 296 #ifndef CONFIG_EVA
>> 297 FEXPORT(__bzero)
>> 298 EXPORT_SYMBOL(__bzero)
>> 299 #else
>> 300 FEXPORT(__bzero_kernel)
>> 301 EXPORT_SYMBOL(__bzero_kernel)
>> 302 #endif
>> 303 __BUILD_BZERO LEGACY_MODE
>> 304
>> 305 #ifdef CONFIG_EVA
>> 306 LEAF(__bzero)
>> 307 EXPORT_SYMBOL(__bzero)
>> 308 __BUILD_BZERO EVA_MODE
>> 309 END(__bzero)
>> 310 #endif
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