1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.
5 *
6 * This file is dual-licensed: you can use it
7 * of the GPL or the X11 license, at your opti
8 * licensing only applies to this file, and no
9 * whole.
10 *
11 * a) This file is free software; you can red
12 * modify it under the terms of the GNU Ge
13 * published by the Free Software Foundati
14 * License, or (at your option) any later
15 *
16 * This file is distributed in the hope th
17 * but WITHOUT ANY WARRANTY; without even
18 * MERCHANTABILITY or FITNESS FOR A PARTIC
19 * GNU General Public License for more det
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of c
24 * obtaining a copy of this software and a
25 * files (the "Software"), to deal in the
26 * restriction, including without limitati
27 * copy, modify, merge, publish, distribut
28 * sell copies of the Software, and to per
29 * Software is furnished to do so, subject
30 * conditions:
31 *
32 * The above copyright notice and this per
33 * included in all copies or substantial p
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHO
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L
37 * OF MERCHANTABILITY, FITNESS FOR A PARTI
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE
40 * WHETHER IN AN ACTION OF CONTRACT, TORT
41 * FROM, OUT OF OR IN CONNECTION WITH THE
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include <dt-bindings/interrupt-controller/arm
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
51
52 / {
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 aliases {
58 ethernet0 = &gmac;
59 };
60
61 chosen {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
66 framebuffer-lcd0-hdmi {
67 compatible = "allwinne
68 "simple-f
69 allwinner,pipeline = "
70 clocks = <&ccu CLK_AHB
71 <&ccu CLK_AHB
72 <&ccu CLK_TCO
73 <&ccu CLK_HDM
74 status = "disabled";
75 };
76
77 framebuffer-lcd0 {
78 compatible = "allwinne
79 "simple-f
80 allwinner,pipeline = "
81 clocks = <&ccu CLK_AHB
82 <&ccu CLK_DE_
83 <&ccu CLK_DRA
84 status = "disabled";
85 };
86
87 framebuffer-lcd0-tve0 {
88 compatible = "allwinne
89 "simple-f
90 allwinner,pipeline = "
91 clocks = <&ccu CLK_AHB
92 <&ccu CLK_AHB
93 <&ccu CLK_DE_
94 <&ccu CLK_DRA
95 status = "disabled";
96 };
97 };
98
99 cpus {
100 #address-cells = <1>;
101 #size-cells = <0>;
102
103 cpu0: cpu@0 {
104 compatible = "arm,cort
105 device_type = "cpu";
106 reg = <0>;
107 clocks = <&ccu CLK_CPU
108 clock-latency = <24414
109 operating-points =
110 /* kHz uV *
111 <960000 140000
112 <912000 140000
113 <864000 130000
114 <720000 120000
115 <528000 110000
116 <312000 100000
117 <144000 100000
118 #cooling-cells = <2>;
119 };
120
121 cpu1: cpu@1 {
122 compatible = "arm,cort
123 device_type = "cpu";
124 reg = <1>;
125 clocks = <&ccu CLK_CPU
126 clock-latency = <24414
127 operating-points =
128 /* kHz uV *
129 <960000 140000
130 <912000 140000
131 <864000 130000
132 <720000 120000
133 <528000 110000
134 <312000 100000
135 <144000 100000
136 #cooling-cells = <2>;
137 };
138 };
139
140 thermal-zones {
141 cpu-thermal {
142 /* milliseconds */
143 polling-delay-passive
144 polling-delay = <1000>
145 thermal-sensors = <&rt
146
147 cooling-maps {
148 map0 {
149 trip =
150 coolin
151
152 };
153 };
154
155 trips {
156 cpu_alert0: cp
157 /* mil
158 temper
159 hyster
160 type =
161 };
162
163 cpu_crit: cpu-
164 /* mil
165 temper
166 hyster
167 type =
168 };
169 };
170 };
171 };
172
173 reserved-memory {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 ranges;
177
178 /* Address must be kept in the
179 default-pool {
180 compatible = "shared-d
181 size = <0x6000000>;
182 alloc-ranges = <0x4000
183 reusable;
184 linux,cma-default;
185 };
186 };
187
188 timer {
189 compatible = "arm,armv7-timer"
190 interrupts = <GIC_PPI 13 (GIC_
191 <GIC_PPI 14 (GIC_
192 <GIC_PPI 11 (GIC_
193 <GIC_PPI 10 (GIC_
194 };
195
196 pmu {
197 compatible = "arm,cortex-a7-pm
198 interrupts = <GIC_SPI 120 IRQ_
199 <GIC_SPI 121 IRQ_
200 };
201
202 clocks {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 ranges;
206
207 osc24M: clk-24M {
208 #clock-cells = <0>;
209 compatible = "fixed-cl
210 clock-frequency = <240
211 clock-output-names = "
212 };
213
214 osc32k: clk-32k {
215 #clock-cells = <0>;
216 compatible = "fixed-cl
217 clock-frequency = <327
218 clock-output-names = "
219 };
220
221 /*
222 * The following two are dummy
223 * used in the gmac_tx clock.
224 * choose one parent depending
225 * mode, using clk_set_rate au
226 *
227 * The actual TX clock rate is
228 * gmac_tx clock.
229 */
230 mii_phy_tx_clk: clk-mii-phy-tx
231 #clock-cells = <0>;
232 compatible = "fixed-cl
233 clock-frequency = <250
234 clock-output-names = "
235 };
236
237 gmac_int_tx_clk: clk-gmac-int-
238 #clock-cells = <0>;
239 compatible = "fixed-cl
240 clock-frequency = <125
241 clock-output-names = "
242 };
243
244 gmac_tx_clk: clk@1c20164 {
245 #clock-cells = <0>;
246 compatible = "allwinne
247 reg = <0x01c20164 0x4>
248 clocks = <&mii_phy_tx_
249 clock-output-names = "
250 };
251 };
252
253
254 de: display-engine {
255 compatible = "allwinner,sun7i-
256 allwinner,pipelines = <&fe0>,
257 status = "disabled";
258 };
259
260 soc {
261 compatible = "simple-bus";
262 #address-cells = <1>;
263 #size-cells = <1>;
264 ranges;
265
266 system-control@1c00000 {
267 compatible = "allwinne
268 "allwinne
269 reg = <0x01c00000 0x30
270 #address-cells = <1>;
271 #size-cells = <1>;
272 ranges;
273
274 sram_a: sram@0 {
275 compatible = "
276 reg = <0x00000
277 #address-cells
278 #size-cells =
279 ranges = <0 0x
280
281 emac_sram: sra
282 compat
283
284 reg =
285 status
286 };
287 };
288
289 sram_d: sram@10000 {
290 compatible = "
291 reg = <0x00010
292 #address-cells
293 #size-cells =
294 ranges = <0 0x
295
296 otg_sram: sram
297 compat
298
299 reg =
300 status
301 };
302 };
303
304 sram_c: sram@1d00000 {
305 compatible = "
306 reg = <0x01d00
307 #address-cells
308 #size-cells =
309 ranges = <0 0x
310
311 ve_sram: sram-
312 compat
313
314 reg =
315 };
316 };
317 };
318
319 nmi_intc: interrupt-controller
320 compatible = "allwinne
321 interrupt-controller;
322 #interrupt-cells = <2>
323 reg = <0x01c00030 0x0c
324 interrupts = <GIC_SPI
325 };
326
327 dma: dma-controller@1c02000 {
328 compatible = "allwinne
329 reg = <0x01c02000 0x10
330 interrupts = <GIC_SPI
331 clocks = <&ccu CLK_AHB
332 #dma-cells = <2>;
333 };
334
335 nfc: nand-controller@1c03000 {
336 compatible = "allwinne
337 reg = <0x01c03000 0x10
338 interrupts = <GIC_SPI
339 clocks = <&ccu CLK_AHB
340 clock-names = "ahb", "
341 dmas = <&dma SUN4I_DMA
342 dma-names = "rxtx";
343 status = "disabled";
344 #address-cells = <1>;
345 #size-cells = <0>;
346 };
347
348 spi0: spi@1c05000 {
349 compatible = "allwinne
350 reg = <0x01c05000 0x10
351 interrupts = <GIC_SPI
352 clocks = <&ccu CLK_AHB
353 clock-names = "ahb", "
354 dmas = <&dma SUN4I_DMA
355 <&dma SUN4I_DMA
356 dma-names = "rx", "tx"
357 status = "disabled";
358 #address-cells = <1>;
359 #size-cells = <0>;
360 num-cs = <4>;
361 };
362
363 spi1: spi@1c06000 {
364 compatible = "allwinne
365 reg = <0x01c06000 0x10
366 interrupts = <GIC_SPI
367 clocks = <&ccu CLK_AHB
368 clock-names = "ahb", "
369 dmas = <&dma SUN4I_DMA
370 <&dma SUN4I_DMA
371 dma-names = "rx", "tx"
372 status = "disabled";
373 #address-cells = <1>;
374 #size-cells = <0>;
375 num-cs = <1>;
376 };
377
378 csi0: csi@1c09000 {
379 compatible = "allwinne
380 reg = <0x01c09000 0x10
381 interrupts = <GIC_SPI
382 clocks = <&ccu CLK_AHB
383 clock-names = "bus", "
384 resets = <&ccu RST_CSI
385 status = "disabled";
386 };
387
388 emac: ethernet@1c0b000 {
389 compatible = "allwinne
390 reg = <0x01c0b000 0x10
391 interrupts = <GIC_SPI
392 clocks = <&ccu CLK_AHB
393 allwinner,sram = <&ema
394 status = "disabled";
395 };
396
397 mdio: mdio@1c0b080 {
398 compatible = "allwinne
399 reg = <0x01c0b080 0x14
400 status = "disabled";
401 #address-cells = <1>;
402 #size-cells = <0>;
403 };
404
405 tcon0: lcd-controller@1c0c000
406 compatible = "allwinne
407 "allwinne
408 reg = <0x01c0c000 0x10
409 interrupts = <GIC_SPI
410 resets = <&ccu RST_TCO
411 reset-names = "lcd", "
412 clocks = <&ccu CLK_AHB
413 <&ccu CLK_TCO
414 <&ccu CLK_TCO
415 clock-names = "ahb",
416 "tcon-ch
417 "tcon-ch
418 clock-output-names = "
419 #clock-cells = <0>;
420 dmas = <&dma SUN4I_DMA
421
422 ports {
423 #address-cells
424 #size-cells =
425
426 tcon0_in: port
427 #addre
428 #size-
429 reg =
430
431 tcon0_
432
433
434 };
435
436 tcon0_
437
438
439 };
440 };
441
442 tcon0_out: por
443 #addre
444 #size-
445 reg =
446
447 tcon0_
448
449
450
451 };
452 };
453 };
454 };
455
456 tcon1: lcd-controller@1c0d000
457 compatible = "allwinne
458 "allwinne
459 reg = <0x01c0d000 0x10
460 interrupts = <GIC_SPI
461 resets = <&ccu RST_TCO
462 reset-names = "lcd";
463 clocks = <&ccu CLK_AHB
464 <&ccu CLK_TCO
465 <&ccu CLK_TCO
466 clock-names = "ahb",
467 "tcon-ch
468 "tcon-ch
469 clock-output-names = "
470 #clock-cells = <0>;
471 dmas = <&dma SUN4I_DMA
472
473 ports {
474 #address-cells
475 #size-cells =
476
477 tcon1_in: port
478 #addre
479 #size-
480 reg =
481
482 tcon1_
483
484
485 };
486
487 tcon1_
488
489
490 };
491 };
492
493 tcon1_out: por
494 #addre
495 #size-
496 reg =
497
498 tcon1_
499
500
501
502 };
503 };
504 };
505 };
506
507 video-codec@1c0e000 {
508 compatible = "allwinne
509 reg = <0x01c0e000 0x10
510 clocks = <&ccu CLK_AHB
511 <&ccu CLK_DRA
512 clock-names = "ahb", "
513 resets = <&ccu RST_VE>
514 interrupts = <GIC_SPI
515 allwinner,sram = <&ve_
516 };
517
518 mmc0: mmc@1c0f000 {
519 compatible = "allwinne
520 reg = <0x01c0f000 0x10
521 clocks = <&ccu CLK_AHB
522 <&ccu CLK_MMC
523 <&ccu CLK_MMC
524 <&ccu CLK_MMC
525 clock-names = "ahb",
526 "mmc",
527 "output"
528 "sample"
529 interrupts = <GIC_SPI
530 pinctrl-names = "defau
531 pinctrl-0 = <&mmc0_pin
532 status = "disabled";
533 #address-cells = <1>;
534 #size-cells = <0>;
535 };
536
537 mmc1: mmc@1c10000 {
538 compatible = "allwinne
539 reg = <0x01c10000 0x10
540 clocks = <&ccu CLK_AHB
541 <&ccu CLK_MMC
542 <&ccu CLK_MMC
543 <&ccu CLK_MMC
544 clock-names = "ahb",
545 "mmc",
546 "output"
547 "sample"
548 interrupts = <GIC_SPI
549 status = "disabled";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 };
553
554 mmc2: mmc@1c11000 {
555 compatible = "allwinne
556 reg = <0x01c11000 0x10
557 clocks = <&ccu CLK_AHB
558 <&ccu CLK_MMC
559 <&ccu CLK_MMC
560 <&ccu CLK_MMC
561 clock-names = "ahb",
562 "mmc",
563 "output"
564 "sample"
565 interrupts = <GIC_SPI
566 pinctrl-names = "defau
567 pinctrl-0 = <&mmc2_pin
568 status = "disabled";
569 #address-cells = <1>;
570 #size-cells = <0>;
571 };
572
573 mmc3: mmc@1c12000 {
574 compatible = "allwinne
575 reg = <0x01c12000 0x10
576 clocks = <&ccu CLK_AHB
577 <&ccu CLK_MMC
578 <&ccu CLK_MMC
579 <&ccu CLK_MMC
580 clock-names = "ahb",
581 "mmc",
582 "output"
583 "sample"
584 interrupts = <GIC_SPI
585 pinctrl-names = "defau
586 pinctrl-0 = <&mmc3_pin
587 status = "disabled";
588 #address-cells = <1>;
589 #size-cells = <0>;
590 };
591
592 usb_otg: usb@1c13000 {
593 compatible = "allwinne
594 reg = <0x01c13000 0x04
595 clocks = <&ccu CLK_AHB
596 interrupts = <GIC_SPI
597 interrupt-names = "mc"
598 phys = <&usbphy 0>;
599 phy-names = "usb";
600 extcon = <&usbphy 0>;
601 allwinner,sram = <&otg
602 dr_mode = "otg";
603 status = "disabled";
604 };
605
606 usbphy: phy@1c13400 {
607 #phy-cells = <1>;
608 compatible = "allwinne
609 reg = <0x01c13400 0x10
610 reg-names = "phy_ctrl"
611 clocks = <&ccu CLK_USB
612 clock-names = "usb_phy
613 resets = <&ccu RST_USB
614 <&ccu RST_USB
615 <&ccu RST_USB
616 reset-names = "usb0_re
617 status = "disabled";
618 };
619
620 ehci0: usb@1c14000 {
621 compatible = "allwinne
622 reg = <0x01c14000 0x10
623 interrupts = <GIC_SPI
624 clocks = <&ccu CLK_AHB
625 phys = <&usbphy 1>;
626 phy-names = "usb";
627 status = "disabled";
628 };
629
630 ohci0: usb@1c14400 {
631 compatible = "allwinne
632 reg = <0x01c14400 0x10
633 interrupts = <GIC_SPI
634 clocks = <&ccu CLK_USB
635 phys = <&usbphy 1>;
636 phy-names = "usb";
637 status = "disabled";
638 };
639
640 crypto: crypto-engine@1c15000
641 compatible = "allwinne
642 "allwinne
643 reg = <0x01c15000 0x10
644 interrupts = <GIC_SPI
645 clocks = <&ccu CLK_AHB
646 clock-names = "ahb", "
647 };
648
649 hdmi: hdmi@1c16000 {
650 compatible = "allwinne
651 "allwinne
652 reg = <0x01c16000 0x10
653 interrupts = <GIC_SPI
654 clocks = <&ccu CLK_AHB
655 <&ccu CLK_PLL
656 <&ccu CLK_PLL
657 clock-names = "ahb", "
658 dmas = <&dma SUN4I_DMA
659 <&dma SUN4I_DMA
660 <&dma SUN4I_DMA
661 dma-names = "ddc-tx",
662 status = "disabled";
663
664 ports {
665 #address-cells
666 #size-cells =
667
668 hdmi_in: port@
669 #addre
670 #size-
671 reg =
672
673 hdmi_i
674
675
676 };
677
678 hdmi_i
679
680
681 };
682 };
683
684 hdmi_out: port
685 reg =
686 };
687 };
688 };
689
690 spi2: spi@1c17000 {
691 compatible = "allwinne
692 reg = <0x01c17000 0x10
693 interrupts = <GIC_SPI
694 clocks = <&ccu CLK_AHB
695 clock-names = "ahb", "
696 dmas = <&dma SUN4I_DMA
697 <&dma SUN4I_DMA
698 dma-names = "rx", "tx"
699 status = "disabled";
700 #address-cells = <1>;
701 #size-cells = <0>;
702 num-cs = <1>;
703 };
704
705 ahci: sata@1c18000 {
706 compatible = "allwinne
707 reg = <0x01c18000 0x10
708 interrupts = <GIC_SPI
709 clocks = <&ccu CLK_AHB
710 status = "disabled";
711 };
712
713 ehci1: usb@1c1c000 {
714 compatible = "allwinne
715 reg = <0x01c1c000 0x10
716 interrupts = <GIC_SPI
717 clocks = <&ccu CLK_AHB
718 phys = <&usbphy 2>;
719 phy-names = "usb";
720 status = "disabled";
721 };
722
723 ohci1: usb@1c1c400 {
724 compatible = "allwinne
725 reg = <0x01c1c400 0x10
726 interrupts = <GIC_SPI
727 clocks = <&ccu CLK_USB
728 phys = <&usbphy 2>;
729 phy-names = "usb";
730 status = "disabled";
731 };
732
733 csi1: csi@1c1d000 {
734 compatible = "allwinne
735 "allwinne
736 reg = <0x01c1d000 0x10
737 interrupts = <GIC_SPI
738 clocks = <&ccu CLK_AHB
739 clock-names = "bus", "
740 resets = <&ccu RST_CSI
741 status = "disabled";
742 };
743
744 spi3: spi@1c1f000 {
745 compatible = "allwinne
746 reg = <0x01c1f000 0x10
747 interrupts = <GIC_SPI
748 clocks = <&ccu CLK_AHB
749 clock-names = "ahb", "
750 dmas = <&dma SUN4I_DMA
751 <&dma SUN4I_DMA
752 dma-names = "rx", "tx"
753 status = "disabled";
754 #address-cells = <1>;
755 #size-cells = <0>;
756 num-cs = <1>;
757 };
758
759 ccu: clock@1c20000 {
760 compatible = "allwinne
761 reg = <0x01c20000 0x40
762 clocks = <&osc24M>, <&
763 clock-names = "hosc",
764 #clock-cells = <1>;
765 #reset-cells = <1>;
766 };
767
768 pio: pinctrl@1c20800 {
769 compatible = "allwinne
770 reg = <0x01c20800 0x40
771 interrupts = <GIC_SPI
772 clocks = <&ccu CLK_APB
773 clock-names = "apb", "
774 gpio-controller;
775 interrupt-controller;
776 #interrupt-cells = <3>
777 #gpio-cells = <3>;
778
779 /omit-if-no-ref/
780 can_pa_pins: can-pa-pi
781 pins = "PA16",
782 function = "ca
783 };
784
785 /omit-if-no-ref/
786 can_ph_pins: can-ph-pi
787 pins = "PH20",
788 function = "ca
789 };
790
791 /omit-if-no-ref/
792 clk_out_a_pin: clk-out
793 pins = "PI12";
794 function = "cl
795 };
796
797 /omit-if-no-ref/
798 clk_out_b_pin: clk-out
799 pins = "PI13";
800 function = "cl
801 };
802
803 /omit-if-no-ref/
804 csi0_8bits_pins: csi-8
805 pins = "PE0",
806 "PE6",
807 "PE11";
808 function = "cs
809 };
810
811 /omit-if-no-ref/
812 csi0_clk_pin: csi-clk-
813 pins = "PE1";
814 function = "cs
815 };
816
817 /omit-if-no-ref/
818 csi1_8bits_pg_pins: cs
819 pins = "PG0",
820 "PG6",
821 "PG11";
822 function = "cs
823 };
824
825 /omit-if-no-ref/
826 csi1_24bits_ph_pins: c
827 pins = "PH0",
828 "PH5",
829 "PH10",
830 "PH15",
831 "PH20",
832 "PH25",
833 function = "cs
834 };
835
836 /omit-if-no-ref/
837 csi1_clk_pg_pin: csi1-
838 pins = "PG1";
839 function = "cs
840 };
841
842 /omit-if-no-ref/
843 emac_pa_pins: emac-pa-
844 pins = "PA0",
845 "PA3",
846 "PA7",
847 "PA11",
848 "PA15",
849 function = "em
850 };
851
852 /omit-if-no-ref/
853 emac_ph_pins: emac-ph-
854 pins = "PH8",
855 "PH14",
856 "PH18",
857 "PH22",
858 "PH26";
859 function = "em
860 };
861
862 /omit-if-no-ref/
863 gmac_mii_pins: gmac-mi
864 pins = "PA0",
865 "PA3",
866 "PA7",
867 "PA11",
868 "PA15",
869 function = "gm
870 };
871
872 /omit-if-no-ref/
873 gmac_rgmii_pins: gmac-
874 pins = "PA0",
875 "PA3",
876 "PA7",
877 "PA11",
878 "PA15",
879 function = "gm
880 /*
881 * data lines
882 * and need a
883 */
884 drive-strength
885 };
886
887 /omit-if-no-ref/
888 i2c0_pins: i2c0-pins {
889 pins = "PB0",
890 function = "i2
891 };
892
893 /omit-if-no-ref/
894 i2c1_pins: i2c1-pins {
895 pins = "PB18",
896 function = "i2
897 };
898
899 /omit-if-no-ref/
900 i2c2_pins: i2c2-pins {
901 pins = "PB20",
902 function = "i2
903 };
904
905 /omit-if-no-ref/
906 i2c3_pins: i2c3-pins {
907 pins = "PI0",
908 function = "i2
909 };
910
911 /omit-if-no-ref/
912 ir0_rx_pin: ir0-rx-pin
913 pins = "PB4";
914 function = "ir
915 };
916
917 /omit-if-no-ref/
918 ir0_tx_pin: ir0-tx-pin
919 pins = "PB3";
920 function = "ir
921 };
922
923 /omit-if-no-ref/
924 ir1_rx_pin: ir1-rx-pin
925 pins = "PB23";
926 function = "ir
927 };
928
929 /omit-if-no-ref/
930 ir1_tx_pin: ir1-tx-pin
931 pins = "PB22";
932 function = "ir
933 };
934
935 /omit-if-no-ref/
936 lcd_lvds0_pins: lcd-lv
937 pins = "PD0",
938 "PD5",
939 function = "lv
940 };
941
942 /omit-if-no-ref/
943 lcd_lvds1_pins: lcd-lv
944 pins = "PD10",
945 "PD15",
946 function = "lv
947 };
948
949 /omit-if-no-ref/
950 mmc0_pins: mmc0-pins {
951 pins = "PF0",
952 "PF3",
953 function = "mm
954 drive-strength
955 bias-pull-up;
956 };
957
958 /omit-if-no-ref/
959 mmc2_pins: mmc2-pins {
960 pins = "PC6",
961 "PC9",
962 function = "mm
963 drive-strength
964 bias-pull-up;
965 };
966
967 /omit-if-no-ref/
968 mmc3_pins: mmc3-pins {
969 pins = "PI4",
970 "PI7",
971 function = "mm
972 drive-strength
973 bias-pull-up;
974 };
975
976 /omit-if-no-ref/
977 ps2_0_pins: ps2-0-pins
978 pins = "PI20",
979 function = "ps
980 };
981
982 /omit-if-no-ref/
983 ps2_1_ph_pins: ps2-1-p
984 pins = "PH12",
985 function = "ps
986 };
987
988 /omit-if-no-ref/
989 pwm0_pin: pwm0-pin {
990 pins = "PB2";
991 function = "pw
992 };
993
994 /omit-if-no-ref/
995 pwm1_pin: pwm1-pin {
996 pins = "PI3";
997 function = "pw
998 };
999
1000 /omit-if-no-ref/
1001 spdif_tx_pin: spdif-t
1002 pins = "PB13"
1003 function = "s
1004 bias-pull-up;
1005 };
1006
1007 /omit-if-no-ref/
1008 spi0_pi_pins: spi0-pi
1009 pins = "PI11"
1010 function = "s
1011 };
1012
1013 /omit-if-no-ref/
1014 spi0_cs0_pi_pin: spi0
1015 pins = "PI10"
1016 function = "s
1017 };
1018
1019 /omit-if-no-ref/
1020 spi0_cs1_pi_pin: spi0
1021 pins = "PI14"
1022 function = "s
1023 };
1024
1025 /omit-if-no-ref/
1026 spi1_pi_pins: spi1-pi
1027 pins = "PI17"
1028 function = "s
1029 };
1030
1031 /omit-if-no-ref/
1032 spi1_cs0_pi_pin: spi1
1033 pins = "PI16"
1034 function = "s
1035 };
1036
1037 /omit-if-no-ref/
1038 spi2_pb_pins: spi2-pb
1039 pins = "PB15"
1040 function = "s
1041 };
1042
1043 /omit-if-no-ref/
1044 spi2_cs0_pb_pin: spi2
1045 pins = "PB14"
1046 function = "s
1047 };
1048
1049 /omit-if-no-ref/
1050 spi2_pc_pins: spi2-pc
1051 pins = "PC20"
1052 function = "s
1053 };
1054
1055 /omit-if-no-ref/
1056 spi2_cs0_pc_pin: spi2
1057 pins = "PC19"
1058 function = "s
1059 };
1060
1061 /omit-if-no-ref/
1062 uart0_pb_pins: uart0-
1063 pins = "PB22"
1064 function = "u
1065 };
1066
1067 /omit-if-no-ref/
1068 uart0_pf_pins: uart0-
1069 pins = "PF2",
1070 function = "u
1071 };
1072
1073 /omit-if-no-ref/
1074 uart1_pa_pins: uart1-
1075 pins = "PA10"
1076 function = "u
1077 };
1078
1079 /omit-if-no-ref/
1080 uart1_cts_rts_pa_pins
1081 pins = "PA12"
1082 function = "u
1083 };
1084
1085 /omit-if-no-ref/
1086 uart2_pa_pins: uart2-
1087 pins = "PA2",
1088 function = "u
1089 };
1090
1091 /omit-if-no-ref/
1092 uart2_cts_rts_pa_pins
1093 pins = "PA0",
1094 function = "u
1095 };
1096
1097 /omit-if-no-ref/
1098 uart2_pi_pins: uart2-
1099 pins = "PI18"
1100 function = "u
1101 };
1102
1103 /omit-if-no-ref/
1104 uart2_cts_rts_pi_pins
1105 pins = "PI16"
1106 function = "u
1107 };
1108
1109 /omit-if-no-ref/
1110 uart3_pg_pins: uart3-
1111 pins = "PG6",
1112 function = "u
1113 };
1114
1115 /omit-if-no-ref/
1116 uart3_cts_rts_pg_pins
1117 pins = "PG8",
1118 function = "u
1119 };
1120
1121 /omit-if-no-ref/
1122 uart3_ph_pins: uart3-
1123 pins = "PH0",
1124 function = "u
1125 };
1126
1127 /omit-if-no-ref/
1128 uart3_cts_rts_ph_pins
1129 pins = "PH2",
1130 function = "u
1131 };
1132
1133 /omit-if-no-ref/
1134 uart4_pg_pins: uart4-
1135 pins = "PG10"
1136 function = "u
1137 };
1138
1139 /omit-if-no-ref/
1140 uart4_ph_pins: uart4-
1141 pins = "PH4",
1142 function = "u
1143 };
1144
1145 /omit-if-no-ref/
1146 uart5_ph_pins: uart5-
1147 pins = "PH6",
1148 function = "u
1149 };
1150
1151 /omit-if-no-ref/
1152 uart5_pi_pins: uart5-
1153 pins = "PI10"
1154 function = "u
1155 };
1156
1157 /omit-if-no-ref/
1158 uart6_pa_pins: uart6-
1159 pins = "PA12"
1160 function = "u
1161 };
1162
1163 /omit-if-no-ref/
1164 uart6_pi_pins: uart6-
1165 pins = "PI12"
1166 function = "u
1167 };
1168
1169 /omit-if-no-ref/
1170 uart7_pa_pins: uart7-
1171 pins = "PA14"
1172 function = "u
1173 };
1174
1175 /omit-if-no-ref/
1176 uart7_pi_pins: uart7-
1177 pins = "PI20"
1178 function = "u
1179 };
1180 };
1181
1182 timer@1c20c00 {
1183 compatible = "allwinn
1184 reg = <0x01c20c00 0x9
1185 interrupts = <GIC_SPI
1186 <GIC_SPI
1187 <GIC_SPI
1188 <GIC_SPI
1189 <GIC_SPI
1190 <GIC_SPI
1191 clocks = <&osc24M>;
1192 };
1193
1194 wdt: watchdog@1c20c90 {
1195 compatible = "allwinn
1196 reg = <0x01c20c90 0x1
1197 interrupts = <GIC_SPI
1198 clocks = <&osc24M>;
1199 };
1200
1201 rtc: rtc@1c20d00 {
1202 compatible = "allwinn
1203 reg = <0x01c20d00 0x2
1204 interrupts = <GIC_SPI
1205 };
1206
1207 pwm: pwm@1c20e00 {
1208 compatible = "allwinn
1209 reg = <0x01c20e00 0xc
1210 clocks = <&osc24M>;
1211 #pwm-cells = <3>;
1212 status = "disabled";
1213 };
1214
1215 spdif: spdif@1c21000 {
1216 #sound-dai-cells = <0
1217 compatible = "allwinn
1218 reg = <0x01c21000 0x4
1219 interrupts = <GIC_SPI
1220 clocks = <&ccu CLK_AP
1221 clock-names = "apb",
1222 dmas = <&dma SUN4I_DM
1223 <&dma SUN4I_DM
1224 dma-names = "rx", "tx
1225 status = "disabled";
1226 };
1227
1228 ir0: ir@1c21800 {
1229 compatible = "allwinn
1230 clocks = <&ccu CLK_AP
1231 clock-names = "apb",
1232 interrupts = <GIC_SPI
1233 reg = <0x01c21800 0x4
1234 status = "disabled";
1235 };
1236
1237 ir1: ir@1c21c00 {
1238 compatible = "allwinn
1239 clocks = <&ccu CLK_AP
1240 clock-names = "apb",
1241 interrupts = <GIC_SPI
1242 reg = <0x01c21c00 0x4
1243 status = "disabled";
1244 };
1245
1246 i2s1: i2s@1c22000 {
1247 #sound-dai-cells = <0
1248 compatible = "allwinn
1249 reg = <0x01c22000 0x4
1250 interrupts = <GIC_SPI
1251 clocks = <&ccu CLK_AP
1252 clock-names = "apb",
1253 dmas = <&dma SUN4I_DM
1254 <&dma SUN4I_DM
1255 dma-names = "rx", "tx
1256 status = "disabled";
1257 };
1258
1259 i2s0: i2s@1c22400 {
1260 #sound-dai-cells = <0
1261 compatible = "allwinn
1262 reg = <0x01c22400 0x4
1263 interrupts = <GIC_SPI
1264 clocks = <&ccu CLK_AP
1265 clock-names = "apb",
1266 dmas = <&dma SUN4I_DM
1267 <&dma SUN4I_DM
1268 dma-names = "rx", "tx
1269 status = "disabled";
1270 };
1271
1272 lradc: lradc@1c22800 {
1273 compatible = "allwinn
1274 reg = <0x01c22800 0x1
1275 interrupts = <GIC_SPI
1276 status = "disabled";
1277 };
1278
1279 codec: codec@1c22c00 {
1280 #sound-dai-cells = <0
1281 compatible = "allwinn
1282 reg = <0x01c22c00 0x4
1283 interrupts = <GIC_SPI
1284 clocks = <&ccu CLK_AP
1285 clock-names = "apb",
1286 dmas = <&dma SUN4I_DM
1287 <&dma SUN4I_DM
1288 dma-names = "rx", "tx
1289 status = "disabled";
1290 };
1291
1292 sid: eeprom@1c23800 {
1293 compatible = "allwinn
1294 reg = <0x01c23800 0x2
1295 };
1296
1297 i2s2: i2s@1c24400 {
1298 #sound-dai-cells = <0
1299 compatible = "allwinn
1300 reg = <0x01c24400 0x4
1301 interrupts = <GIC_SPI
1302 clocks = <&ccu CLK_AP
1303 clock-names = "apb",
1304 dmas = <&dma SUN4I_DM
1305 <&dma SUN4I_DM
1306 dma-names = "rx", "tx
1307 status = "disabled";
1308 };
1309
1310 rtp: rtp@1c25000 {
1311 compatible = "allwinn
1312 reg = <0x01c25000 0x1
1313 interrupts = <GIC_SPI
1314 #thermal-sensor-cells
1315 };
1316
1317 uart0: serial@1c28000 {
1318 compatible = "snps,dw
1319 reg = <0x01c28000 0x4
1320 interrupts = <GIC_SPI
1321 reg-shift = <2>;
1322 reg-io-width = <4>;
1323 clocks = <&ccu CLK_AP
1324 status = "disabled";
1325 };
1326
1327 uart1: serial@1c28400 {
1328 compatible = "snps,dw
1329 reg = <0x01c28400 0x4
1330 interrupts = <GIC_SPI
1331 reg-shift = <2>;
1332 reg-io-width = <4>;
1333 clocks = <&ccu CLK_AP
1334 status = "disabled";
1335 };
1336
1337 uart2: serial@1c28800 {
1338 compatible = "snps,dw
1339 reg = <0x01c28800 0x4
1340 interrupts = <GIC_SPI
1341 reg-shift = <2>;
1342 reg-io-width = <4>;
1343 clocks = <&ccu CLK_AP
1344 status = "disabled";
1345 };
1346
1347 uart3: serial@1c28c00 {
1348 compatible = "snps,dw
1349 reg = <0x01c28c00 0x4
1350 interrupts = <GIC_SPI
1351 reg-shift = <2>;
1352 reg-io-width = <4>;
1353 clocks = <&ccu CLK_AP
1354 status = "disabled";
1355 };
1356
1357 uart4: serial@1c29000 {
1358 compatible = "snps,dw
1359 reg = <0x01c29000 0x4
1360 interrupts = <GIC_SPI
1361 reg-shift = <2>;
1362 reg-io-width = <4>;
1363 clocks = <&ccu CLK_AP
1364 status = "disabled";
1365 };
1366
1367 uart5: serial@1c29400 {
1368 compatible = "snps,dw
1369 reg = <0x01c29400 0x4
1370 interrupts = <GIC_SPI
1371 reg-shift = <2>;
1372 reg-io-width = <4>;
1373 clocks = <&ccu CLK_AP
1374 status = "disabled";
1375 };
1376
1377 uart6: serial@1c29800 {
1378 compatible = "snps,dw
1379 reg = <0x01c29800 0x4
1380 interrupts = <GIC_SPI
1381 reg-shift = <2>;
1382 reg-io-width = <4>;
1383 clocks = <&ccu CLK_AP
1384 status = "disabled";
1385 };
1386
1387 uart7: serial@1c29c00 {
1388 compatible = "snps,dw
1389 reg = <0x01c29c00 0x4
1390 interrupts = <GIC_SPI
1391 reg-shift = <2>;
1392 reg-io-width = <4>;
1393 clocks = <&ccu CLK_AP
1394 status = "disabled";
1395 };
1396
1397 ps20: ps2@1c2a000 {
1398 compatible = "allwinn
1399 reg = <0x01c2a000 0x4
1400 interrupts = <GIC_SPI
1401 clocks = <&ccu CLK_AP
1402 status = "disabled";
1403 };
1404
1405 ps21: ps2@1c2a400 {
1406 compatible = "allwinn
1407 reg = <0x01c2a400 0x4
1408 interrupts = <GIC_SPI
1409 clocks = <&ccu CLK_AP
1410 status = "disabled";
1411 };
1412
1413 i2c0: i2c@1c2ac00 {
1414 compatible = "allwinn
1415 "allwinn
1416 reg = <0x01c2ac00 0x4
1417 interrupts = <GIC_SPI
1418 clocks = <&ccu CLK_AP
1419 pinctrl-names = "defa
1420 pinctrl-0 = <&i2c0_pi
1421 status = "disabled";
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1424 };
1425
1426 i2c1: i2c@1c2b000 {
1427 compatible = "allwinn
1428 "allwinn
1429 reg = <0x01c2b000 0x4
1430 interrupts = <GIC_SPI
1431 clocks = <&ccu CLK_AP
1432 pinctrl-names = "defa
1433 pinctrl-0 = <&i2c1_pi
1434 status = "disabled";
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1437 };
1438
1439 i2c2: i2c@1c2b400 {
1440 compatible = "allwinn
1441 "allwinn
1442 reg = <0x01c2b400 0x4
1443 interrupts = <GIC_SPI
1444 clocks = <&ccu CLK_AP
1445 pinctrl-names = "defa
1446 pinctrl-0 = <&i2c2_pi
1447 status = "disabled";
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1450 };
1451
1452 i2c3: i2c@1c2b800 {
1453 compatible = "allwinn
1454 "allwinn
1455 reg = <0x01c2b800 0x4
1456 interrupts = <GIC_SPI
1457 clocks = <&ccu CLK_AP
1458 pinctrl-names = "defa
1459 pinctrl-0 = <&i2c3_pi
1460 status = "disabled";
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 };
1464
1465 can0: can@1c2bc00 {
1466 compatible = "allwinn
1467 "allwinn
1468 reg = <0x01c2bc00 0x4
1469 interrupts = <GIC_SPI
1470 clocks = <&ccu CLK_AP
1471 status = "disabled";
1472 };
1473
1474 i2c4: i2c@1c2c000 {
1475 compatible = "allwinn
1476 "allwinn
1477 reg = <0x01c2c000 0x4
1478 interrupts = <GIC_SPI
1479 clocks = <&ccu CLK_AP
1480 status = "disabled";
1481 #address-cells = <1>;
1482 #size-cells = <0>;
1483 };
1484
1485 mali: gpu@1c40000 {
1486 compatible = "allwinn
1487 reg = <0x01c40000 0x1
1488 interrupts = <GIC_SPI
1489 <GIC_SPI
1490 <GIC_SPI
1491 <GIC_SPI
1492 <GIC_SPI
1493 <GIC_SPI
1494 <GIC_SPI
1495 interrupt-names = "gp
1496 "gp
1497 "pp
1498 "pp
1499 "pp
1500 "pp
1501 "pm
1502 clocks = <&ccu CLK_AH
1503 clock-names = "bus",
1504 resets = <&ccu RST_GP
1505
1506 assigned-clocks = <&c
1507 assigned-clock-rates
1508 };
1509
1510 gmac: ethernet@1c50000 {
1511 compatible = "allwinn
1512 reg = <0x01c50000 0x1
1513 interrupts = <GIC_SPI
1514 interrupt-names = "ma
1515 clocks = <&ccu CLK_AH
1516 clock-names = "stmmac
1517 snps,pbl = <2>;
1518 snps,fixed-burst;
1519 snps,force_sf_dma_mod
1520 status = "disabled";
1521
1522 gmac_mdio: mdio {
1523 compatible =
1524 #address-cell
1525 #size-cells =
1526 };
1527 };
1528
1529 hstimer@1c60000 {
1530 compatible = "allwinn
1531 reg = <0x01c60000 0x1
1532 interrupts = <GIC_SPI
1533 <GIC_SPI
1534 <GIC_SPI
1535 <GIC_SPI
1536 clocks = <&ccu CLK_AH
1537 };
1538
1539 gic: interrupt-controller@1c8
1540 compatible = "arm,gic
1541 reg = <0x01c81000 0x1
1542 <0x01c82000 0x2
1543 <0x01c84000 0x2
1544 <0x01c86000 0x2
1545 interrupt-controller;
1546 #interrupt-cells = <3
1547 interrupts = <GIC_PPI
1548 };
1549
1550 fe0: display-frontend@1e00000
1551 compatible = "allwinn
1552 reg = <0x01e00000 0x2
1553 interrupts = <GIC_SPI
1554 clocks = <&ccu CLK_AH
1555 <&ccu CLK_DR
1556 clock-names = "ahb",
1557 "ram";
1558 resets = <&ccu RST_DE
1559
1560 ports {
1561 #address-cell
1562 #size-cells =
1563
1564 fe0_out: port
1565 #addr
1566 #size
1567 reg =
1568
1569 fe0_o
1570
1571
1572 };
1573
1574 fe0_o
1575
1576
1577 };
1578 };
1579 };
1580 };
1581
1582 fe1: display-frontend@1e20000
1583 compatible = "allwinn
1584 reg = <0x01e20000 0x2
1585 interrupts = <GIC_SPI
1586 clocks = <&ccu CLK_AH
1587 <&ccu CLK_DR
1588 clock-names = "ahb",
1589 "ram";
1590 resets = <&ccu RST_DE
1591
1592 ports {
1593 #address-cell
1594 #size-cells =
1595
1596 fe1_out: port
1597 #addr
1598 #size
1599 reg =
1600
1601 fe1_o
1602
1603
1604 };
1605
1606 fe1_o
1607
1608
1609 };
1610 };
1611 };
1612 };
1613
1614 be1: display-backend@1e40000
1615 compatible = "allwinn
1616 reg = <0x01e40000 0x1
1617 interrupts = <GIC_SPI
1618 clocks = <&ccu CLK_AH
1619 <&ccu CLK_DR
1620 clock-names = "ahb",
1621 "ram";
1622 resets = <&ccu RST_DE
1623
1624 ports {
1625 #address-cell
1626 #size-cells =
1627
1628 be1_in: port@
1629 #addr
1630 #size
1631 reg =
1632
1633 be1_i
1634
1635
1636 };
1637
1638 be1_i
1639
1640
1641 };
1642 };
1643
1644 be1_out: port
1645 #addr
1646 #size
1647 reg =
1648
1649 be1_o
1650
1651
1652 };
1653
1654 be1_o
1655
1656
1657 };
1658 };
1659 };
1660 };
1661
1662 be0: display-backend@1e60000
1663 compatible = "allwinn
1664 reg = <0x01e60000 0x1
1665 interrupts = <GIC_SPI
1666 clocks = <&ccu CLK_AH
1667 <&ccu CLK_DR
1668 clock-names = "ahb",
1669 "ram";
1670 resets = <&ccu RST_DE
1671
1672 ports {
1673 #address-cell
1674 #size-cells =
1675
1676 be0_in: port@
1677 #addr
1678 #size
1679 reg =
1680
1681 be0_i
1682
1683
1684 };
1685
1686 be0_i
1687
1688
1689 };
1690 };
1691
1692 be0_out: port
1693 #addr
1694 #size
1695 reg =
1696
1697 be0_o
1698
1699
1700 };
1701
1702 be0_o
1703
1704
1705 };
1706 };
1707 };
1708 };
1709 };
1710 };
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