1 /*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it
7 * of the GPL or the X11 license, at your opti
8 * licensing only applies to this file, and no
9 * whole.
10 *
11 * a) This file is free software; you can red
12 * modify it under the terms of the GNU Ge
13 * published by the Free Software Foundati
14 * License, or (at your option) any later
15 *
16 * This file is distributed in the hope th
17 * but WITHOUT ANY WARRANTY; without even
18 * MERCHANTABILITY or FITNESS FOR A PARTIC
19 * GNU General Public License for more det
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of c
24 * obtaining a copy of this software and a
25 * files (the "Software"), to deal in the
26 * restriction, including without limitati
27 * copy, modify, merge, publish, distribut
28 * sell copies of the Software, and to per
29 * Software is furnished to do so, subject
30 * conditions:
31 *
32 * The above copyright notice and this per
33 * included in all copies or substantial p
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHO
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L
37 * OF MERCHANTABILITY, FITNESS FOR A PARTI
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE
40 * WHETHER IN AN ACTION OF CONTRACT, TORT
41 * FROM, OUT OF OR IN CONNECTION WITH THE
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
47
48 / {
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points
51 opp-shared;
52
53 opp-120000000 {
54 opp-hz = /bits/ 64 <12
55 opp-microvolt = <10400
56 clock-latency-ns = <24
57 };
58
59 opp-240000000 {
60 opp-hz = /bits/ 64 <24
61 opp-microvolt = <10400
62 clock-latency-ns = <24
63 };
64
65 opp-312000000 {
66 opp-hz = /bits/ 64 <31
67 opp-microvolt = <10400
68 clock-latency-ns = <24
69 };
70
71 opp-408000000 {
72 opp-hz = /bits/ 64 <40
73 opp-microvolt = <10400
74 clock-latency-ns = <24
75 };
76
77 opp-480000000 {
78 opp-hz = /bits/ 64 <48
79 opp-microvolt = <10400
80 clock-latency-ns = <24
81 };
82
83 opp-504000000 {
84 opp-hz = /bits/ 64 <50
85 opp-microvolt = <10400
86 clock-latency-ns = <24
87 };
88
89 opp-600000000 {
90 opp-hz = /bits/ 64 <60
91 opp-microvolt = <10400
92 clock-latency-ns = <24
93 };
94
95 opp-648000000 {
96 opp-hz = /bits/ 64 <64
97 opp-microvolt = <10400
98 clock-latency-ns = <24
99 };
100
101 opp-720000000 {
102 opp-hz = /bits/ 64 <72
103 opp-microvolt = <11000
104 clock-latency-ns = <24
105 };
106
107 opp-816000000 {
108 opp-hz = /bits/ 64 <81
109 opp-microvolt = <11000
110 clock-latency-ns = <24
111 };
112
113 opp-912000000 {
114 opp-hz = /bits/ 64 <91
115 opp-microvolt = <12000
116 clock-latency-ns = <24
117 };
118
119 opp-1008000000 {
120 opp-hz = /bits/ 64 <10
121 opp-microvolt = <12000
122 clock-latency-ns = <24
123 };
124 };
125
126 cpus {
127 cpu@0 {
128 clocks = <&ccu CLK_CPU
129 clock-names = "cpu";
130 operating-points-v2 =
131 #cooling-cells = <2>;
132 };
133
134 cpu1: cpu@1 {
135 clocks = <&ccu CLK_CPU
136 clock-names = "cpu";
137 operating-points-v2 =
138 #cooling-cells = <2>;
139 };
140
141 cpu2: cpu@2 {
142 compatible = "arm,cort
143 device_type = "cpu";
144 reg = <2>;
145 clocks = <&ccu CLK_CPU
146 clock-names = "cpu";
147 operating-points-v2 =
148 #cooling-cells = <2>;
149 };
150
151 cpu3: cpu@3 {
152 compatible = "arm,cort
153 device_type = "cpu";
154 reg = <3>;
155 clocks = <&ccu CLK_CPU
156 clock-names = "cpu";
157 operating-points-v2 =
158 #cooling-cells = <2>;
159 };
160 };
161
162 iio-hwmon {
163 compatible = "iio-hwmon";
164 io-channels = <&ths>;
165 };
166
167 mali_opp_table: opp-table-gpu {
168 compatible = "operating-points
169
170 opp-144000000 {
171 opp-hz = /bits/ 64 <14
172 };
173
174 opp-240000000 {
175 opp-hz = /bits/ 64 <24
176 };
177
178 opp-384000000 {
179 opp-hz = /bits/ 64 <38
180 };
181 };
182
183 sound: sound {
184 compatible = "simple-audio-car
185 simple-audio-card,name = "sun8
186 simple-audio-card,format = "i2
187 simple-audio-card,frame-master
188 simple-audio-card,bitclock-mas
189 simple-audio-card,mclk-fs = <1
190 simple-audio-card,aux-devs = <
191 simple-audio-card,routing =
192 "Left DAC", "DACL",
193 "Right DAC", "DACR";
194 status = "disabled";
195
196 simple-audio-card,cpu {
197 sound-dai = <&dai>;
198 };
199
200 link_codec: simple-audio-card,
201 sound-dai = <&codec 0>
202 };
203 };
204
205 soc {
206 video-codec@1c0e000 {
207 compatible = "allwinne
208 reg = <0x01c0e000 0x10
209 clocks = <&ccu CLK_BUS
210 <&ccu CLK_DRA
211 clock-names = "ahb", "
212 resets = <&ccu RST_BUS
213 interrupts = <GIC_SPI
214 allwinner,sram = <&ve_
215 };
216
217 crypto: crypto-engine@1c15000
218 compatible = "allwinne
219 reg = <0x01c15000 0x10
220 interrupts = <GIC_SPI
221 clocks = <&ccu CLK_BUS
222 clock-names = "ahb", "
223 resets = <&ccu RST_BUS
224 reset-names = "ahb";
225 };
226
227 dai: dai@1c22c00 {
228 #sound-dai-cells = <0>
229 compatible = "allwinne
230 reg = <0x01c22c00 0x20
231 interrupts = <GIC_SPI
232 clocks = <&ccu CLK_BUS
233 clock-names = "apb", "
234 resets = <&ccu RST_BUS
235 dmas = <&dma 15>, <&dm
236 dma-names = "rx", "tx"
237 status = "disabled";
238 };
239
240 codec: codec@1c22e00 {
241 #sound-dai-cells = <1>
242 compatible = "allwinne
243 reg = <0x01c22e00 0x40
244 interrupts = <GIC_SPI
245 clocks = <&ccu CLK_BUS
246 clock-names = "bus", "
247 status = "disabled";
248 };
249
250 ths: ths@1c25000 {
251 compatible = "allwinne
252 reg = <0x01c25000 0x10
253 #thermal-sensor-cells
254 #io-channel-cells = <0
255 };
256
257 dsi: dsi@1ca0000 {
258 compatible = "allwinne
259 reg = <0x01ca0000 0x10
260 interrupts = <GIC_SPI
261 clocks = <&ccu CLK_BUS
262 <&ccu CLK_DSI
263 clock-names = "bus", "
264 resets = <&ccu RST_BUS
265 phys = <&dphy>;
266 phy-names = "dphy";
267 status = "disabled";
268 #address-cells = <1>;
269 #size-cells = <0>;
270
271 port {
272 dsi_in_tcon0:
273 remote
274 };
275 };
276 };
277
278 dphy: d-phy@1ca1000 {
279 compatible = "allwinne
280 reg = <0x01ca1000 0x10
281 interrupts = <GIC_SPI
282 clocks = <&ccu CLK_BUS
283 <&ccu CLK_DSI
284 clock-names = "bus", "
285 resets = <&ccu RST_BUS
286 status = "disabled";
287 #phy-cells = <0>;
288 };
289 };
290
291 thermal-zones {
292 cpu-thermal {
293 /* milliseconds */
294 polling-delay-passive
295 polling-delay = <1000>
296 thermal-sensors = <&th
297
298 cooling-maps {
299 map0 {
300 trip =
301 coolin
302
303
304
305 };
306 map1 {
307 trip =
308 coolin
309
310
311
312 };
313
314 map2 {
315 trip =
316 coolin
317 };
318
319 map3 {
320 trip =
321 coolin
322 };
323 };
324
325 trips {
326 cpu_alert0: cp
327 /* mil
328 temper
329 hyster
330 type =
331 };
332
333 gpu_alert0: gp
334 /* mil
335 temper
336 hyster
337 type =
338 };
339
340 cpu_alert1: cp
341 /* mil
342 temper
343 hyster
344 type =
345 };
346
347 gpu_alert1: gp
348 /* mil
349 temper
350 hyster
351 type =
352 };
353
354 cpu_crit: cpu-
355 /* mil
356 temper
357 hyster
358 type =
359 };
360 };
361 };
362 };
363 };
364
365 &be0 {
366 compatible = "allwinner,sun8i-a33-disp
367 /* A33 has an extra "SAT" module packe
368 reg = <0x01e60000 0x10000>, <0x01e8000
369 reg-names = "be", "sat";
370 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu C
371 <&ccu CLK_DRAM_DE_BE>, <&ccu
372 clock-names = "ahb", "mod",
373 "ram", "sat";
374 resets = <&ccu RST_BUS_DE_BE>, <&ccu R
375 reset-names = "be", "sat";
376 };
377
378 &ccu {
379 compatible = "allwinner,sun8i-a33-ccu"
380 };
381
382 &de {
383 compatible = "allwinner,sun8i-a33-disp
384 };
385
386 &drc0 {
387 compatible = "allwinner,sun8i-a33-drc"
388 };
389
390 &fe0 {
391 compatible = "allwinner,sun8i-a33-disp
392 };
393
394 &mali {
395 operating-points-v2 = <&mali_opp_table
396 };
397
398 &pio {
399 compatible = "allwinner,sun8i-a33-pinc
400 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVE
401 <GIC_SPI 17 IRQ_TYPE_LEVE
402
403 uart0_pb_pins: uart0-pb-pins {
404 pins = "PB0", "PB1";
405 function = "uart0";
406 };
407
408 };
409
410 &tcon0 {
411 compatible = "allwinner,sun8i-a33-tcon
412 };
413
414 &tcon0_out {
415 #address-cells = <1>;
416 #size-cells = <0>;
417
418 tcon0_out_dsi: endpoint@1 {
419 reg = <1>;
420 remote-endpoint = <&dsi_in_tco
421 };
422 };
423
424 &usb_otg {
425 compatible = "allwinner,sun8i-a33-musb
426 };
427
428 &usbphy {
429 compatible = "allwinner,sun8i-a33-usb-
430 reg = <0x01c19400 0x14>, <0x01c1a800 0
431 reg-names = "phy_ctrl", "pmu1";
432 };
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