1 /*
2 * Device Tree Source for the Axis ARTPEC-6 So
3 *
4 * This file is dual-licensed: you can use it
5 * of the GPL or the X11 license, at your opti
6 * licensing only applies to this file, and no
7 * whole.
8 *
9 * a) This file is free software; you can red
10 * modify it under the terms of the GNU Ge
11 * published by the Free Software Foundati
12 * License, or (at your option) any later
13 *
14 * This file is distributed in the hope th
15 * but WITHOUT ANY WARRANTY; without even
16 * MERCHANTABILITY or FITNESS FOR A PARTIC
17 * GNU General Public License for more det
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of c
22 * obtaining a copy of this software and a
23 * files (the "Software"), to deal in the
24 * restriction, including without limitati
25 * copy, modify, merge, publish, distribut
26 * sell copies of the Software, and to per
27 * Software is furnished to do so, subject
28 * conditions:
29 *
30 * The above copyright notice and this per
31 * included in all copies or substantial p
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHO
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT L
35 * OF MERCHANTABILITY, FITNESS FOR A PARTI
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGE
38 * WHETHER IN AN ACTION OF CONTRACT, TORT
39 * FROM, OUT OF OR IN CONNECTION WITH THE
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/interrupt-controller/arm
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkct
46
47 / {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "axis,artpec6";
51 interrupt-parent = <&intc>;
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 cpu0: cpu@0 {
58 device_type = "cpu";
59 compatible = "arm,cort
60 reg = <0>;
61 next-level-cache = <&p
62 };
63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cort
67 reg = <1>;
68 next-level-cache = <&p
69 };
70 };
71
72 syscon: syscon@f8000000 {
73 compatible = "axis,artpec6-sys
74 reg = <0xf8000000 0x48>;
75 };
76
77 psci {
78 compatible = "arm,psci-0.2", "
79 method = "smc";
80 psci_version = <0x84000000>;
81 cpu_on = <0x84000003>;
82 system_reset = <0x84000009>;
83 };
84
85 scu@faf00000 {
86 compatible = "arm,cortex-a9-sc
87 reg = <0xfaf00000 0x58>;
88 };
89
90 /* Main external clock driving CPU and
91 ext_clk: ext_clk {
92 #clock-cells = <0>;
93 compatible = "fixed-clock";
94 clock-frequency = <50000000>;
95 };
96
97 eth_phy_ref_clk: eth_phy_ref_clk {
98 #clock-cells = <0>;
99 compatible = "fixed-clock";
100 clock-frequency = <125000000>;
101 };
102
103 clkctrl: clkctrl@f8000000 {
104 #clock-cells = <1>;
105 compatible = "axis,artpec6-clk
106 reg = <0xf8000000 0x48>;
107 clocks = <&ext_clk>;
108 clock-names = "sys_refclk";
109 };
110
111 gtimer@faf00200 {
112 compatible = "arm,cortex-a9-gl
113 reg = <0xfaf00200 0x20>;
114 interrupts = <GIC_PPI 11 0xf01
115 clocks = <&clkctrl ARTPEC6_CLK
116 };
117
118 timer@faf00600 {
119 compatible = "arm,cortex-a9-tw
120 reg = <0xfaf00600 0x20>;
121 interrupts = <GIC_PPI 13 0xf04
122 clocks = <&clkctrl ARTPEC6_CLK
123 status = "disabled";
124 };
125
126 intc: interrupt-controller@faf01000 {
127 interrupt-controller;
128 compatible = "arm,cortex-a9-gi
129 #interrupt-cells = <3>;
130 reg = < 0xfaf01000 0x1000 >, <
131 };
132
133 pl310: cache-controller@faf10000 {
134 compatible = "arm,pl310-cache"
135 cache-unified;
136 cache-level = <2>;
137 reg = <0xfaf10000 0x1000>;
138 interrupts = <GIC_SPI 4 IRQ_TY
139 arm,data-latency = <1 1 1>;
140 arm,tag-latency = <1 1 1>;
141 arm,filter-ranges = <0x0 0x800
142 arm,double-linefill = <1>;
143 arm,double-linefill-incr = <0>
144 arm,double-linefill-wrap = <0>
145 prefetch-data = <1>;
146 prefetch-instr = <1>;
147 arm,prefetch-offset = <0>;
148 arm,prefetch-drop = <1>;
149 };
150
151 pmu {
152 compatible = "arm,cortex-a9-pm
153 interrupts = <GIC_SPI 0 IRQ_TY
154 <GIC_SPI 1 IRQ_TYPE_LE
155 interrupt-affinity = <&cpu0>,
156 };
157
158 /*
159 * Both pci nodes cannot be enabled at
160 * leave the unwanted node as disabled
161 */
162 pcie: pcie@f8050000 {
163 compatible = "axis,artpec6-pci
164 reg = <0xf8050000 0x2000
165 0xf8040000 0x1000
166 0xc0000000 0x2000>;
167 reg-names = "dbi", "phy", "con
168 #address-cells = <3>;
169 #size-cells = <2>;
170 device_type = "pci";
171 /* downstream I/O */
172 ranges = <0x81000000 0 0 0xc00
173 /* non-prefetchable
174 0x82000000 0 0xc0012
175 num-lanes = <2>;
176 bus-range = <0x00 0xff>;
177 interrupts = <GIC_SPI 148 IRQ_
178 interrupt-names = "msi";
179 #interrupt-cells = <1>;
180 interrupt-map-mask = <0 0 0 0x
181 interrupt-map = <0 0 0 1 &intc
182 <0 0 0 2 &intc
183 <0 0 0 3 &intc
184 <0 0 0 4 &intc
185 axis,syscon-pcie = <&syscon>;
186 status = "disabled";
187 };
188
189 pcie_ep: pcie_ep@f8050000 {
190 compatible = "axis,artpec6-pci
191 reg = <0xf8050000 0x2000
192 0xf8051000 0x2000
193 0xf8040000 0x1000
194 0xc0000000 0x20000000>;
195 reg-names = "dbi", "dbi2", "ph
196 num-ib-windows = <6>;
197 num-ob-windows = <2>;
198 num-lanes = <2>;
199 axis,syscon-pcie = <&syscon>;
200 status = "disabled";
201 };
202
203 pinctrl: pinctrl@f801d000 {
204 compatible = "axis,artpec6-pin
205 reg = <0xf801d000 0x400>;
206
207 pinctrl_uart0: uart0grp {
208 function = "uart0";
209 groups = "uart0grp2";
210 bias-pull-up;
211 };
212 pinctrl_uart1: uart1grp {
213 function = "uart1";
214 groups = "uart1grp0";
215 bias-pull-up;
216 };
217 pinctrl_uart2: uart2grp {
218 function = "uart2";
219 groups = "uart2grp1";
220 bias-pull-up;
221 };
222 pinctrl_uart3: uart3grp {
223 function = "uart3";
224 groups = "uart3grp0";
225 bias-pull-up;
226 };
227 };
228
229 amba@0 {
230 compatible = "simple-bus";
231 #address-cells = <0x1>;
232 #size-cells = <0x1>;
233 ranges;
234 dma-ranges;
235
236 crypto@f4264000 {
237 compatible = "axis,art
238 reg = <0xf4264000 0x40
239 interrupts = <GIC_SPI
240 };
241
242 dma0: dma@f8019000 {
243 compatible = "renesas,
244 reg = <0xf8019000 0x40
245 interrupts = <GIC_SPI
246 <GIC_SPI
247 <GIC_SPI
248 <GIC_SPI
249 <GIC_SPI
250 <GIC_SPI
251 <GIC_SPI
252 <GIC_SPI
253 <GIC_SPI
254 interrupt-names = "err
255 "ch0
256 "ch4
257 "ch8
258 "ch1
259 clocks = <&clkctrl ART
260 #dma-cells = <2>;
261 dma-channels = <8>;
262 dma-requests = <8>;
263 };
264 dma1: dma@f8019400 {
265 compatible = "renesas,
266 reg = <0xf8019400 0x40
267 interrupts = <GIC_SPI
268 <GIC_SPI
269 <GIC_SPI
270 <GIC_SPI
271 <GIC_SPI
272 <GIC_SPI
273 <GIC_SPI
274 <GIC_SPI
275 <GIC_SPI
276 interrupt-names = "err
277 "ch0
278 "ch4
279 "ch8
280 "ch1
281 clocks = <&clkctrl ART
282 #dma-cells = <2>;
283 dma-channels = <8>;
284 dma-requests = <8>;
285 };
286
287 ethernet: ethernet@f8010000 {
288 clock-names = "stmmace
289 clocks = <&clkctrl ART
290 <&clkctrl ARTP
291 compatible = "snps,dwm
292 interrupts = <GIC_SPI
293 <GIC_SPI
294 interrupt-names = "mac
295 reg = <0xf8010000 0x40
296
297 snps,axi-config = <&st
298 snps,mtl-rx-config = <
299 snps,mtl-tx-config = <
300
301 snps,txpbl = <8>;
302 snps,rxpbl = <2>;
303 snps,aal;
304 snps,tso;
305
306 status = "disabled";
307
308 stmmac_axi_setup: stmm
309 snps,wr_osr_lm
310 snps,rd_osr_lm
311 /* If FB is di
312 * a burst len
313 * maximum ena
314 * (all lesser
315 */
316 snps,blen = <0
317 };
318
319 mtl_rx_setup: rx-queue
320 snps,rx-queues
321 queue0 {};
322 };
323
324 mtl_tx_setup: tx-queue
325 snps,tx-queues
326 queue0 {};
327 queue1 {};
328 };
329 };
330
331 uart0: serial@f8036000 {
332 compatible = "arm,pl01
333 reg = <0xf8036000 0x10
334 interrupts = <GIC_SPI
335 clocks = <&clkctrl ART
336 <&clkctrl ARTP
337 clock-names = "uart_cl
338 pinctrl-names = "defau
339 pinctrl-0 = <&pinctrl_
340 dmas = <&dma0 4 (NBPF_
341 <&dma0 5 (NBPF_
342 dma-names = "rx", "tx"
343 status = "disabled";
344 };
345 uart1: serial@f8037000 {
346 compatible = "arm,pl01
347 reg = <0xf8037000 0x10
348 interrupts = <GIC_SPI
349 clocks = <&clkctrl ART
350 <&clkctrl ARTP
351 clock-names = "uart_cl
352 pinctrl-names = "defau
353 pinctrl-0 = <&pinctrl_
354 dmas = <&dma0 6 (NBPF_
355 <&dma0 7 (NBPF_
356 dma-names = "rx", "tx"
357 status = "disabled";
358 };
359 uart2: serial@f8038000 {
360 compatible = "arm,pl01
361 reg = <0xf8038000 0x10
362 interrupts = <GIC_SPI
363 clocks = <&clkctrl ART
364 <&clkctrl ARTP
365 clock-names = "uart_cl
366 pinctrl-names = "defau
367 pinctrl-0 = <&pinctrl_
368 dmas = <&dma1 0 (NBPF_
369 <&dma1 1 (NBPF_
370 dma-names = "rx", "tx"
371 status = "disabled";
372 };
373 uart3: serial@f8039000 {
374 compatible = "arm,pl01
375 reg = <0xf8039000 0x10
376 interrupts = <GIC_SPI
377 clocks = <&clkctrl ART
378 <&clkctrl ARTP
379 clock-names = "uart_cl
380 pinctrl-names = "defau
381 pinctrl-0 = <&pinctrl_
382 dmas = <&dma1 2 (NBPF_
383 <&dma1 3 (NBPF_
384 dma-names = "rx", "tx"
385 status = "disabled";
386 };
387 };
388 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.