1 /*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2017 Broadcom. All rights re
5 *
6 * Redistribution and use in source and binar
7 * modification, are permitted provided that
8 * are met:
9 *
10 * * Redistributions of source code must re
11 * notice, this list of conditions and th
12 * * Redistributions in binary form must re
13 * notice, this list of conditions and th
14 * the documentation and/or other materia
15 * distribution.
16 * * Neither the name of Broadcom Corporati
17 * contributors may be used to endorse or
18 * from this software without specific pr
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERC
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DI
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAG
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOOD
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISIN
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE P
31 */
32
33 #include <dt-bindings/interrupt-controller/arm
34 #include <dt-bindings/interrupt-controller/irq
35
36 / {
37 compatible = "brcm,hr2";
38 model = "Broadcom Hurricane 2 SoC";
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cort
50 next-level-cache = <&L
51 reg = <0x0>;
52 };
53 };
54
55 pmu {
56 compatible = "arm,cortex-a9-pm
57 interrupts = <GIC_SPI 8 IRQ_TY
58 <GIC_SPI 9 IRQ_TY
59 interrupt-affinity = <&cpu0>;
60 };
61
62 mpcore@19000000 {
63 compatible = "simple-bus";
64 ranges = <0x00000000 0x1900000
65 #address-cells = <1>;
66 #size-cells = <1>;
67
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
70 compatible = "brcm,hr2
71 clocks = <&osc>;
72 reg = <0x0 0x1000>;
73 };
74
75 timer@20200 {
76 compatible = "arm,cort
77 reg = <0x20200 0x100>;
78 interrupts = <GIC_PPI
79 clocks = <&periph_clk>
80 };
81
82 twd-timer@20600 {
83 compatible = "arm,cort
84 reg = <0x20600 0x20>;
85 interrupts = <GIC_PPI
86
87 clocks = <&periph_clk>
88 };
89
90 twd-watchdog@20620 {
91 compatible = "arm,cort
92 reg = <0x20620 0x20>;
93 interrupts = <GIC_PPI
94
95 clocks = <&periph_clk>
96 };
97
98 gic: interrupt-controller@2100
99 compatible = "arm,cort
100 #interrupt-cells = <3>
101 #address-cells = <0>;
102 interrupt-controller;
103 reg = <0x21000 0x1000>
104 <0x20100 0x100>;
105 };
106
107 L2: cache-controller@22000 {
108 compatible = "arm,pl31
109 reg = <0x22000 0x1000>
110 cache-unified;
111 cache-level = <2>;
112 };
113 };
114
115 clocks {
116 #address-cells = <1>;
117 #size-cells = <1>;
118 ranges;
119
120 osc: oscillator {
121 #clock-cells = <0>;
122 compatible = "fixed-cl
123 clock-frequency = <250
124 };
125
126 periph_clk: periph_clk {
127 #clock-cells = <0>;
128 compatible = "fixed-fa
129 clocks = <&a9pll>;
130 clock-div = <2>;
131 clock-mult = <1>;
132 };
133 };
134
135 axi@18000000 {
136 compatible = "simple-bus";
137 ranges = <0x00000000 0x1800000
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 uart0: serial@300 {
142 compatible = "ns16550a
143 reg = <0x0300 0x100>;
144 interrupts = <GIC_SPI
145 clocks = <&osc>;
146 status = "disabled";
147 };
148
149 uart1: serial@400 {
150 compatible = "ns16550a
151 reg = <0x0400 0x100>;
152 interrupts = <GIC_SPI
153 clocks = <&osc>;
154 status = "disabled";
155 };
156
157 dma@20000 {
158 compatible = "arm,pl33
159 reg = <0x20000 0x1000>
160 interrupts = <GIC_SPI
161 <GIC_SPI
162 <GIC_SPI
163 <GIC_SPI
164 <GIC_SPI
165 <GIC_SPI
166 <GIC_SPI
167 <GIC_SPI
168 <GIC_SPI
169 #dma-cells = <1>;
170 status = "disabled";
171 };
172
173 amac0: ethernet@22000 {
174 compatible = "brcm,nsp
175 reg = <0x22000 0x1000>
176 <0x110000 0x1000
177 reg-names = "amac_base
178 interrupts = <GIC_SPI
179 status = "disabled";
180 };
181
182 nand_controller: nand-controll
183 compatible = "brcm,nan
184 reg = <0x26000 0x600>,
185 <0x11b408 0x600>
186 <0x026f00 0x20>;
187 reg-names = "nand", "i
188 interrupts = <GIC_SPI
189
190 #address-cells = <1>;
191 #size-cells = <0>;
192
193 brcm,nand-has-wp;
194 };
195
196 gpiob: gpio@30000 {
197 compatible = "brcm,ipr
198 reg = <0x30000 0x50>;
199 #gpio-cells = <2>;
200 gpio-controller;
201 ngpios = <4>;
202 interrupt-controller;
203 #interrupt-cells = <2>
204 interrupts = <GIC_SPI
205 };
206
207 pwm: pwm@31000 {
208 compatible = "brcm,ipr
209 reg = <0x31000 0x28>;
210 clocks = <&osc>;
211 #pwm-cells = <3>;
212 status = "disabled";
213 };
214
215 rng: rng@33000 {
216 compatible = "brcm,bcm
217 reg = <0x33000 0x14>;
218 };
219
220 qspi: spi@27200 {
221 compatible = "brcm,spi
222 reg = <0x027200 0x184>
223 <0x027000 0x124>
224 <0x11c408 0x004>
225 <0x0273a0 0x01c>
226 reg-names = "mspi", "b
227 "intr_stat
228 interrupts = <GIC_SPI
229 <GIC_SPI
230 <GIC_SPI
231 <GIC_SPI
232 <GIC_SPI
233 <GIC_SPI
234 <GIC_SPI
235 interrupt-names = "spi
236 "spi
237 "spi
238 "spi
239 "spi
240 "msp
241 "msp
242 num-cs = <2>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245
246 /* partitions defined
247 };
248
249 ccbtimer0: timer@34000 {
250 compatible = "arm,sp80
251 reg = <0x34000 0x1000>
252 interrupts = <GIC_SPI
253 <GIC_SPI
254 };
255
256 ccbtimer1: timer@35000 {
257 compatible = "arm,sp80
258 reg = <0x35000 0x1000>
259 interrupts = <GIC_SPI
260 <GIC_SPI
261 };
262
263 i2c0: i2c@38000 {
264 compatible = "brcm,ipr
265 reg = <0x38000 0x50>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 interrupts = <GIC_SPI
269 clock-frequency = <100
270 };
271
272 watchdog: watchdog@39000 {
273 compatible = "arm,sp80
274 reg = <0x39000 0x1000>
275 interrupts = <GIC_SPI
276 };
277
278 i2c1: i2c@3b000 {
279 compatible = "brcm,ipr
280 reg = <0x3b000 0x50>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 interrupts = <GIC_SPI
284 clock-frequency = <100
285 };
286 };
287
288 pflash: nor@20000000 {
289 compatible = "cfi-flash", "jed
290 reg = <0x20000000 0x04000000>;
291 status = "disabled";
292 #address-cells = <1>;
293 #size-cells = <1>;
294
295 /* partitions defined in board
296 };
297
298 pcie0: pcie@18012000 {
299 compatible = "brcm,iproc-pcie"
300 reg = <0x18012000 0x1000>;
301
302 #interrupt-cells = <1>;
303 interrupt-map-mask = <0 0 0 0>
304 interrupt-map = <0 0 0 0 &gic
305
306 linux,pci-domain = <0>;
307
308 bus-range = <0x00 0xff>;
309
310 #address-cells = <3>;
311 #size-cells = <2>;
312 device_type = "pci";
313
314 /* Note: The HW does not suppo
315 * only the memory resource ra
316 */
317 ranges = <0x82000000 0 0x08000
318
319 status = "disabled";
320
321 msi-parent = <&msi0>;
322 msi0: msi {
323 compatible = "brcm,ipr
324 msi-controller;
325 interrupt-parent = <&g
326 interrupts = <GIC_SPI
327 <GIC_SPI
328 <GIC_SPI
329 <GIC_SPI
330 brcm,pcie-msi-inten;
331 };
332 };
333
334 pcie1: pcie@18013000 {
335 compatible = "brcm,iproc-pcie"
336 reg = <0x18013000 0x1000>;
337
338 #interrupt-cells = <1>;
339 interrupt-map-mask = <0 0 0 0>
340 interrupt-map = <0 0 0 0 &gic
341
342 linux,pci-domain = <1>;
343
344 bus-range = <0x00 0xff>;
345
346 #address-cells = <3>;
347 #size-cells = <2>;
348 device_type = "pci";
349
350 /* Note: The HW does not suppo
351 * only the memory resource ra
352 */
353 ranges = <0x82000000 0 0x40000
354
355 status = "disabled";
356
357 msi-parent = <&msi1>;
358 msi1: msi {
359 compatible = "brcm,ipr
360 msi-controller;
361 interrupt-parent = <&g
362 interrupts = <GIC_SPI
363 <GIC_SPI
364 <GIC_SPI
365 <GIC_SPI
366 brcm,pcie-msi-inten;
367 };
368 };
369 };
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