1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Broadcom BCM63138 DSL SoCs Device Tree
4 */
5
6 #include <dt-bindings/interrupt-controller/arm
7 #include <dt-bindings/interrupt-controller/irq
8
9 / {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "brcm,bcm63138", "brcm,bc
13 model = "Broadcom BCM963138 Reference
14 interrupt-parent = <&gic>;
15
16 aliases {
17 uart0 = &serial0;
18 uart1 = &serial1;
19 };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cort
28 next-level-cache = <&L
29 reg = <0>;
30 enable-method = "brcm,
31 };
32
33 cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cort
36 next-level-cache = <&L
37 reg = <1>;
38 enable-method = "brcm,
39 resets = <&pmb0 4 1>;
40 };
41 };
42
43 clocks {
44 /* UBUS peripheral clock */
45 periph_clk: periph_clk {
46 #clock-cells = <0>;
47 compatible = "fixed-cl
48 clock-frequency = <500
49 clock-output-names = "
50 };
51
52 /* peripheral clock for system
53 axi_clk: axi_clk {
54 #clock-cells = <0>;
55 compatible = "fixed-fa
56 clocks = <&armpll>;
57 clock-div = <2>;
58 clock-mult = <1>;
59 };
60
61 /* APB bus clock */
62 apb_clk: apb_clk {
63 #clock-cells = <0>;
64 compatible = "fixed-fa
65 clocks = <&armpll>;
66 clock-div = <4>;
67 clock-mult = <1>;
68 };
69
70 hsspi_pll: hsspi-pll {
71 compatible = "fixed-cl
72 #clock-cells = <0>;
73 clock-frequency = <400
74 };
75 };
76
77 /* ARM bus */
78 axi@80000000 {
79 compatible = "simple-bus";
80 ranges = <0 0x80000000 0x78400
81 #address-cells = <1>;
82 #size-cells = <1>;
83
84 L2: cache-controller@1d000 {
85 compatible = "arm,pl31
86 reg = <0x1d000 0x1000>
87 cache-unified;
88 cache-level = <2>;
89 cache-size = <524288>;
90 cache-sets = <1024>;
91 cache-line-size = <32>
92 interrupts = <GIC_PPI
93 };
94
95 scu: scu@1e000 {
96 compatible = "arm,cort
97 reg = <0x1e000 0x100>;
98 };
99
100 gic: interrupt-controller@1f00
101 compatible = "arm,cort
102 reg = <0x1f000 0x1000
103 0x1e100 0x100>
104 #interrupt-cells = <3>
105 #address-cells = <0>;
106 interrupt-controller;
107 };
108
109 global_timer: timer@1e200 {
110 compatible = "arm,cort
111 reg = <0x1e200 0x20>;
112 interrupts = <GIC_PPI
113 clocks = <&axi_clk>;
114 };
115
116 local_timer: local-timer@1e600
117 compatible = "arm,cort
118 reg = <0x1e600 0x20>;
119 interrupts = <GIC_PPI
120
121 clocks = <&axi_clk>;
122 };
123
124 twd_watchdog: watchdog@1e620 {
125 compatible = "arm,cort
126 reg = <0x1e620 0x20>;
127 interrupts = <GIC_PPI
128
129 };
130
131 armpll: armpll@20000 {
132 #clock-cells = <0>;
133 compatible = "brcm,bcm
134 clocks = <&periph_clk>
135 reg = <0x20000 0xf00>;
136 };
137
138 pmb0: reset-controller@4800c0
139 compatible = "brcm,bcm
140 reg = <0x4800c0 0x10>;
141 #reset-cells = <2>;
142 };
143
144 pmb1: reset-controller@4800e0
145 compatible = "brcm,bcm
146 reg = <0x4800e0 0x10>;
147 #reset-cells = <2>;
148 };
149
150 ahci: sata@a000 {
151 compatible = "brcm,bcm
152 reg-names = "ahci", "t
153 reg = <0xa000 0x9ac>,
154 interrupts = <GIC_SPI
155 #address-cells = <1>;
156 #size-cells = <0>;
157 resets = <&pmb0 3 1>;
158 reset-names = "ahci";
159 status = "disabled";
160
161 sata0: sata-port@0 {
162 reg = <0>;
163 phys = <&sata_
164 };
165 };
166
167 sata_phy: sata-phy@8100 {
168 compatible = "brcm,bcm
169 reg = <0x8100 0x1e00>;
170 reg-names = "phy";
171 #address-cells = <1>;
172 #size-cells = <0>;
173 status = "disabled";
174
175 sata_phy0: sata-phy@0
176 reg = <0>;
177 #phy-cells = <
178 };
179 };
180 };
181
182 /* Legacy UBUS base */
183 ubus@fffe8000 {
184 compatible = "simple-bus";
185 #address-cells = <1>;
186 #size-cells = <1>;
187 ranges = <0 0xfffe8000 0x8100>
188
189 timer: timer@80 {
190 compatible = "brcm,bcm
191 reg = <0x80 0x3c>;
192 };
193
194 serial0: serial@600 {
195 compatible = "brcm,bcm
196 reg = <0x600 0x1b>;
197 interrupts = <GIC_SPI
198 clocks = <&periph_clk>
199 clock-names = "periph"
200 status = "disabled";
201 };
202
203 serial1: serial@620 {
204 compatible = "brcm,bcm
205 reg = <0x620 0x1b>;
206 interrupts = <GIC_SPI
207 clocks = <&periph_clk>
208 clock-names = "periph"
209 status = "disabled";
210 };
211
212 hsspi: spi@1000 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "brcm,bcm
216 reg = <0x1000 0x600>;
217 interrupts = <GIC_SPI
218 clocks = <&hsspi_pll &
219 clock-names = "hsspi",
220 num-cs = <8>;
221 status = "disabled";
222 };
223
224 nand_controller: nand-controll
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "brcm,nan
228 reg = <0x2000 0x600>,
229 reg-names = "nand", "n
230 status = "disabled";
231 interrupts = <GIC_SPI
232 interrupt-names = "nan
233
234 nandcs: nand@0 {
235 compatible = "
236 reg = <0>;
237 };
238 };
239
240 serial@4400 {
241 compatible = "brcm,bcm
242 reg = <0x4400 0x1e0>;
243 interrupts = <GIC_SPI
244 };
245
246 bootlut: bootlut@8000 {
247 compatible = "brcm,bcm
248 reg = <0x8000 0x50>;
249 };
250
251 reboot {
252 compatible = "syscon-r
253 regmap = <&timer>;
254 offset = <0x34>;
255 mask = <1>;
256 };
257 };
258 };
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