1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6 #include <dt-bindings/interrupt-controller/arm
7 #include <dt-bindings/interrupt-controller/irq
8
9 / {
10 compatible = "brcm,bcm6878", "brcm,bcm
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 interrupt-parent = <&gic>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 CA7_0: cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cort
23 reg = <0x0>;
24 next-level-cache = <&L
25 enable-method = "psci"
26 };
27
28 CA7_1: cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cort
31 reg = <0x1>;
32 next-level-cache = <&L
33 enable-method = "psci"
34 };
35
36 L2_0: l2-cache0 {
37 compatible = "cache";
38 cache-level = <2>;
39 cache-unified;
40 };
41 };
42
43 timer {
44 compatible = "arm,armv7-timer"
45 interrupts = <GIC_PPI 13 (GIC_
46 <GIC_PPI 14 (GIC_CPU_M
47 <GIC_PPI 11 (GIC_CPU_M
48 <GIC_PPI 10 (GIC_CPU_M
49 arm,cpu-registers-not-fw-confi
50 };
51
52 pmu: pmu {
53 compatible = "arm,cortex-a7-pm
54 interrupts = <GIC_SPI 9 IRQ_TY
55 <GIC_SPI 10 IRQ_TYPE_L
56 interrupt-affinity = <&CA7_0>,
57 };
58
59 clocks: clocks {
60 periph_clk: periph-clk {
61 compatible = "fixed-cl
62 #clock-cells = <0>;
63 clock-frequency = <200
64 };
65
66 uart_clk: uart-clk {
67 compatible = "fixed-fa
68 #clock-cells = <0>;
69 clocks = <&periph_clk>
70 clock-div = <4>;
71 clock-mult = <1>;
72 };
73
74 hsspi_pll: hsspi-pll {
75 compatible = "fixed-cl
76 #clock-cells = <0>;
77 clock-frequency = <200
78 };
79 };
80
81 psci {
82 compatible = "arm,psci-0.2";
83 method = "smc";
84 };
85
86 axi@81000000 {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges = <0 0x81000000 0x8000>
91
92 gic: interrupt-controller@1000
93 compatible = "arm,cort
94 #interrupt-cells = <3>
95 interrupt-controller;
96 reg = <0x1000 0x1000>,
97 <0x2000 0x2000
98 <0x4000 0x2000
99 <0x6000 0x2000
100 interrupts = <GIC_PPI
101 IRQ_TY
102 };
103 };
104
105 bus@ff800000 {
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges = <0 0xff800000 0x80000
110
111 hsspi: spi@1000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "brcm,bcm
115 reg = <0x1000 0x600>;
116 interrupts = <GIC_SPI
117 clocks = <&hsspi_pll &
118 clock-names = "hsspi",
119 num-cs = <8>;
120 status = "disabled";
121 };
122
123 nand_controller: nand-controll
124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "brcm,nan
127 reg = <0x1800 0x600>,
128 reg-names = "nand", "n
129 status = "disabled";
130
131 nandcs: nand@0 {
132 compatible = "
133 reg = <0>;
134 };
135 };
136
137 uart0: serial@12000 {
138 compatible = "arm,pl01
139 reg = <0x12000 0x1000>
140 interrupts = <GIC_SPI
141 clocks = <&uart_clk>,
142 clock-names = "uartclk
143 status = "disabled";
144 };
145 };
146 };
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