1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * sam9x60.dtsi - Device Tree Include file for
4 *
5 * Copyright (C) 2019 Microchip Technology Inc
6 *
7 * Author: Sandeep Sheriker M <sandeepsheriker.
8 */
9
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
17
18 / {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 model = "Microchip SAM9X60 SoC";
22 compatible = "microchip,sam9x60";
23 interrupt-parent = <&aic>;
24
25 aliases {
26 serial0 = &dbgu;
27 gpio0 = &pioA;
28 gpio1 = &pioB;
29 gpio2 = &pioC;
30 gpio3 = &pioD;
31 tcb0 = &tcb0;
32 tcb1 = &tcb1;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 compatible = "arm,arm9
41 device_type = "cpu";
42 reg = <0>;
43 };
44 };
45
46 memory@20000000 {
47 device_type = "memory";
48 reg = <0x20000000 0x10000000>;
49 };
50
51 clocks {
52 slow_xtal: slow_xtal {
53 compatible = "fixed-cl
54 #clock-cells = <0>;
55 };
56
57 main_xtal: main_xtal {
58 compatible = "fixed-cl
59 #clock-cells = <0>;
60 };
61 };
62
63 sram: sram@300000 {
64 compatible = "mmio-sram";
65 reg = <0x00300000 0x100000>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0 0x00300000 0x10000
69 };
70
71 ahb {
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 usb0: gadget@500000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "microchi
81 reg = <0x00500000 0x10
82 0xf803c000 0x4
83 interrupts = <23 IRQ_T
84 clocks = <&pmc PMC_TYP
85 clock-names = "pclk",
86 assigned-clocks = <&pm
87 assigned-clock-rates =
88 status = "disabled";
89 };
90
91 usb1: ohci@600000 {
92 compatible = "atmel,at
93 reg = <0x00600000 0x10
94 interrupts = <22 IRQ_T
95 clocks = <&pmc PMC_TYP
96 clock-names = "ohci_cl
97 status = "disabled";
98 };
99
100 usb2: ehci@700000 {
101 compatible = "atmel,at
102 reg = <0x00700000 0x10
103 interrupts = <22 IRQ_T
104 clocks = <&pmc PMC_TYP
105 clock-names = "usb_clk
106 assigned-clocks = <&pm
107 assigned-clock-rates =
108 status = "disabled";
109 };
110
111 ebi: ebi@10000000 {
112 compatible = "microchi
113 #address-cells = <2>;
114 #size-cells = <1>;
115 atmel,smc = <&smc>;
116 microchip,sfr = <&sfr>
117 reg = <0x10000000 0x60
118 ranges = <0x0 0x0 0x10
119 0x1 0x0 0x20
120 0x2 0x0 0x30
121 0x3 0x0 0x40
122 0x4 0x0 0x50
123 0x5 0x0 0x60
124 clocks = <&pmc PMC_TYP
125 status = "disabled";
126
127 nand_controller: nand-
128 compatible = "
129 ecc-engine = <
130 #address-cells
131 #size-cells =
132 ranges;
133 status = "disa
134 };
135 };
136
137 sdmmc0: sdio-host@80000000 {
138 compatible = "microchi
139 reg = <0x80000000 0x30
140 interrupts = <12 IRQ_T
141 clocks = <&pmc PMC_TYP
142 clock-names = "hclock"
143 assigned-clocks = <&pm
144 assigned-clock-rates =
145 status = "disabled";
146 };
147
148 sdmmc1: sdio-host@90000000 {
149 compatible = "microchi
150 reg = <0x90000000 0x30
151 interrupts = <26 IRQ_T
152 clocks = <&pmc PMC_TYP
153 clock-names = "hclock"
154 assigned-clocks = <&pm
155 assigned-clock-rates =
156 status = "disabled";
157 };
158
159 apb {
160 compatible = "simple-b
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164
165 flx4: flexcom@f0000000
166 compatible = "
167 reg = <0xf0000
168 clocks = <&pmc
169 #address-cells
170 #size-cells =
171 ranges = <0x0
172 status = "disa
173
174 uart4: serial@
175 compat
176 reg =
177 interr
178 dmas =
179
180
181
182
183
184
185
186 dma-na
187 clocks
188 clock-
189 atmel,
190 atmel,
191 atmel,
192 status
193 };
194
195 spi4: spi@400
196 compat
197 reg =
198 interr
199 clocks
200 clock-
201 dmas =
202
203
204
205
206
207
208
209 dma-na
210 atmel,
211 status
212 };
213
214 i2c4: i2c@600
215 compat
216 reg =
217 interr
218 #addre
219 #size-
220 clocks
221 dmas =
222
223
224
225
226
227
228
229 dma-na
230 atmel,
231 status
232 };
233 };
234
235 flx5: flexcom@f0004000
236 compatible = "
237 reg = <0xf0004
238 clocks = <&pmc
239 #address-cells
240 #size-cells =
241 ranges = <0x0
242 status = "disa
243
244 uart5: serial@
245 compat
246 reg =
247 atmel,
248 interr
249 dmas =
250
251
252
253
254
255
256
257 dma-na
258 clocks
259 clock-
260 atmel,
261 atmel,
262 atmel,
263 status
264 };
265
266 spi5: spi@400
267 compat
268 reg =
269 interr
270 clocks
271 clock-
272 dmas =
273
274
275
276
277
278
279
280 dma-na
281 atmel,
282 status
283 };
284
285 i2c5: i2c@600
286 compat
287 reg =
288 interr
289 #addre
290 #size-
291 clocks
292 dmas =
293
294
295
296
297
298
299
300 dma-na
301 atmel,
302 status
303 };
304 };
305
306 dma0: dma-controller@f
307 compatible = "
308 reg = <0xf0008
309 interrupts = <
310 #dma-cells = <
311 clocks = <&pmc
312 clock-names =
313 };
314
315 ssc: ssc@f0010000 {
316 compatible = "
317 reg = <0xf0010
318 interrupts = <
319 dmas = <&dma0
320 (AT91_
321 AT91_
322 <&dma0
323 (AT91_
324 AT91_
325 dma-names = "t
326 clocks = <&pmc
327 clock-names =
328 status = "disa
329 };
330
331 qspi: spi@f0014000 {
332 compatible = "
333 reg = <0xf0014
334 reg-names = "q
335 interrupts = <
336 dmas = <&dma0
337 (AT91_
338 AT91_
339 <&dma0
340 (AT91_
341 AT91_
342 dma-names = "t
343 clocks = <&pmc
344 clock-names =
345 atmel,pmc = <&
346 #address-cells
347 #size-cells =
348 status = "disa
349 };
350
351 i2s: i2s@f001c000 {
352 compatible = "
353 reg = <0xf001c
354 interrupts = <
355 dmas = <&dma0
356 (AT91_
357 AT91_
358 <&dma0
359 (AT91_
360 AT91_
361 dma-names = "t
362 clocks = <&pmc
363 clock-names =
364 status = "disa
365 };
366
367 flx11: flexcom@f002000
368 compatible = "
369 reg = <0xf0020
370 clocks = <&pmc
371 #address-cells
372 #size-cells =
373 ranges = <0x0
374 status = "disa
375
376 uart11: serial
377 compat
378 reg =
379 interr
380 dmas =
381
382
383
384
385
386
387
388 dma-na
389 clocks
390 clock-
391 atmel,
392 atmel,
393 atmel,
394 status
395 };
396
397 i2c11: i2c@600
398 compat
399 reg =
400 interr
401 #addre
402 #size-
403 clocks
404 dmas =
405
406
407
408
409
410
411
412 dma-na
413 atmel,
414 status
415 };
416 };
417
418 flx12: flexcom@f002400
419 compatible = "
420 reg = <0xf0024
421 clocks = <&pmc
422 #address-cells
423 #size-cells =
424 ranges = <0x0
425 status = "disa
426
427 uart12: serial
428 compat
429 reg =
430 interr
431 dmas =
432
433
434
435
436
437
438
439 dma-na
440 clocks
441 clock-
442 atmel,
443 atmel,
444 atmel,
445 status
446 };
447
448 i2c12: i2c@600
449 compat
450 reg =
451 interr
452 #addre
453 #size-
454 clocks
455 dmas =
456
457
458
459
460
461
462
463 dma-na
464 atmel,
465 status
466 };
467 };
468
469 pit64b: timer@f0028000
470 compatible = "
471 reg = <0xf0028
472 interrupts = <
473 clocks = <&pmc
474 clock-names =
475 };
476
477 sha: crypto@f002c000 {
478 compatible = "
479 reg = <0xf002c
480 interrupts = <
481 dmas = <&dma0
482 (AT91_
483 AT91_
484 dma-names = "t
485 clocks = <&pmc
486 clock-names =
487 };
488
489 trng: trng@f0030000 {
490 compatible = "
491 reg = <0xf0030
492 interrupts = <
493 clocks = <&pmc
494 };
495
496 aes: crypto@f0034000 {
497 compatible = "
498 reg = <0xf0034
499 interrupts = <
500 dmas = <&dma0
501 (AT91_
502 AT91_
503 <&dma0
504 (AT91_
505 AT91_
506 dma-names = "t
507 clocks = <&pmc
508 clock-names =
509 };
510
511 tdes: crypto@f0038000
512 compatible = "
513 reg = <0xf0038
514 interrupts = <
515 dmas = <&dma0
516 (AT91_
517 AT91_
518 <&dma0
519 (AT91_
520 AT91_
521 dma-names = "t
522 clocks = <&pmc
523 clock-names =
524 };
525
526 classd: classd@f003c00
527 compatible = "
528 reg = <0xf003c
529 interrupts = <
530 dmas = <&dma0
531 (AT91_
532 AT91_
533 dma-names = "t
534 clocks = <&pmc
535 clock-names =
536 status = "disa
537 };
538
539 can0: can@f8000000 {
540 compatible = "
541 reg = <0xf8000
542 interrupts = <
543 clocks = <&pmc
544 clock-names =
545 status = "disa
546 };
547
548 can1: can@f8004000 {
549 compatible = "
550 reg = <0xf8004
551 interrupts = <
552 clocks = <&pmc
553 clock-names =
554 status = "disa
555 };
556
557 tcb0: timer@f8008000 {
558 compatible = "
559 #address-cells
560 #size-cells =
561 reg = <0xf8008
562 interrupts = <
563 clocks = <&pmc
564 clock-names =
565 };
566
567 tcb1: timer@f800c000 {
568 compatible = "
569 #address-cells
570 #size-cells =
571 reg = <0xf800c
572 interrupts = <
573 clocks = <&pmc
574 clock-names =
575 };
576
577 flx6: flexcom@f8010000
578 compatible = "
579 reg = <0xf8010
580 clocks = <&pmc
581 #address-cells
582 #size-cells =
583 ranges = <0x0
584 status = "disa
585
586 uart6: serial@
587 compat
588 reg =
589 interr
590 dmas =
591
592
593
594
595
596
597
598 dma-na
599 clocks
600 clock-
601 atmel,
602 atmel,
603 atmel,
604 status
605 };
606
607 i2c6: i2c@600
608 compat
609 reg =
610 interr
611 #addre
612 #size-
613 clocks
614 dmas =
615
616
617
618
619
620
621
622 dma-na
623 atmel,
624 status
625 };
626 };
627
628 flx7: flexcom@f8014000
629 compatible = "
630 reg = <0xf8014
631 clocks = <&pmc
632 #address-cells
633 #size-cells =
634 ranges = <0x0
635 status = "disa
636
637 uart7: serial@
638 compat
639 reg =
640 interr
641 dmas =
642
643
644
645
646
647
648
649 dma-na
650 clocks
651 clock-
652 atmel,
653 atmel,
654 atmel,
655 status
656 };
657
658 i2c7: i2c@600
659 compat
660 reg =
661 interr
662 #addre
663 #size-
664 clocks
665 dmas =
666
667
668
669
670
671
672
673 dma-na
674 atmel,
675 status
676 };
677 };
678
679 flx8: flexcom@f8018000
680 compatible = "
681 reg = <0xf8018
682 clocks = <&pmc
683 #address-cells
684 #size-cells =
685 ranges = <0x0
686 status = "disa
687
688 uart8: serial@
689 compat
690 reg =
691 interr
692 dmas =
693
694
695
696
697
698
699
700 dma-na
701 clocks
702 clock-
703 atmel,
704 atmel,
705 atmel,
706 status
707 };
708
709 i2c8: i2c@600
710 compat
711 reg =
712 interr
713 #addre
714 #size-
715 clocks
716 dmas =
717
718
719
720
721
722
723
724 dma-na
725 atmel,
726 status
727 };
728 };
729
730 flx0: flexcom@f801c000
731 compatible = "
732 reg = <0xf801c
733 clocks = <&pmc
734 #address-cells
735 #size-cells =
736 ranges = <0x0
737 status = "disa
738
739 uart0: serial@
740 compat
741 reg =
742 interr
743 dmas =
744
745
746
747
748
749
750
751 dma-na
752 clocks
753 clock-
754 atmel,
755 atmel,
756 atmel,
757 status
758 };
759
760 spi0: spi@400
761 compat
762 reg =
763 interr
764 clocks
765 clock-
766 dmas =
767
768
769
770
771
772
773
774 dma-na
775 atmel,
776 status
777 };
778
779 i2c0: i2c@600
780 compat
781 reg =
782 interr
783 #addre
784 #size-
785 clocks
786 dmas =
787
788
789
790
791
792
793
794 dma-na
795 atmel,
796 status
797 };
798 };
799
800 flx1: flexcom@f8020000
801 compatible = "
802 reg = <0xf8020
803 clocks = <&pmc
804 #address-cells
805 #size-cells =
806 ranges = <0x0
807 status = "disa
808
809 uart1: serial@
810 compat
811 reg =
812 interr
813 dmas =
814
815
816
817
818
819
820
821 dma-na
822 clocks
823 clock-
824 atmel,
825 atmel,
826 atmel,
827 status
828 };
829
830 spi1: spi@400
831 compat
832 reg =
833 interr
834 clocks
835 clock-
836 dmas =
837
838
839
840
841
842
843
844 dma-na
845 atmel,
846 status
847 };
848
849 i2c1: i2c@600
850 compat
851 reg =
852 interr
853 #addre
854 #size-
855 clocks
856 dmas =
857
858
859
860
861
862
863
864 dma-na
865 atmel,
866 status
867 };
868 };
869
870 flx2: flexcom@f8024000
871 compatible = "
872 reg = <0xf8024
873 clocks = <&pmc
874 #address-cells
875 #size-cells =
876 ranges = <0x0
877 status = "disa
878
879 uart2: serial@
880 compat
881 reg =
882 interr
883 dmas =
884
885
886
887
888
889
890
891 dma-na
892 clocks
893 clock-
894 atmel,
895 atmel,
896 atmel,
897 status
898 };
899
900 spi2: spi@400
901 compat
902 reg =
903 interr
904 clocks
905 clock-
906 dmas =
907
908
909
910
911
912
913
914 dma-na
915 atmel,
916 status
917 };
918
919 i2c2: i2c@600
920 compat
921 reg =
922 interr
923 #addre
924 #size-
925 clocks
926 dmas =
927
928
929
930
931
932
933
934 dma-na
935 atmel,
936 status
937 };
938 };
939
940 flx3: flexcom@f8028000
941 compatible = "
942 reg = <0xf8028
943 clocks = <&pmc
944 #address-cells
945 #size-cells =
946 ranges = <0x0
947 status = "disa
948
949 uart3: serial@
950 compat
951 reg =
952 interr
953 dmas =
954
955
956
957
958
959
960
961 dma-na
962 clocks
963 clock-
964 atmel,
965 atmel,
966 atmel,
967 status
968 };
969
970 spi3: spi@400
971 compat
972 reg =
973 interr
974 clocks
975 clock-
976 dmas =
977
978
979
980
981
982
983
984 dma-na
985 atmel,
986 status
987 };
988
989 i2c3: i2c@600
990 compat
991 reg =
992 interr
993 #addre
994 #size-
995 clocks
996 dmas =
997
998
999
1000
1001
1002
1003
1004 dma-n
1005 atmel
1006 statu
1007 };
1008 };
1009
1010 macb0: ethernet@f802c
1011 compatible =
1012 reg = <0xf802
1013 interrupts =
1014 clocks = <&pm
1015 clock-names =
1016 status = "dis
1017 };
1018
1019 macb1: ethernet@f8030
1020 compatible =
1021 reg = <0xf803
1022 interrupts =
1023 clocks = <&pm
1024 clock-names =
1025 status = "dis
1026 };
1027
1028 pwm0: pwm@f8034000 {
1029 compatible =
1030 reg = <0xf803
1031 interrupts =
1032 clocks = <&pm
1033 #pwm-cells =
1034 status = "dis
1035 };
1036
1037 hlcdc: hlcdc@f8038000
1038 compatible =
1039 reg = <0xf803
1040 interrupts =
1041 clocks = <&pm
1042 clock-names =
1043 assigned-cloc
1044 assigned-cloc
1045 status = "dis
1046
1047 hlcdc-display
1048 compa
1049 #addr
1050 #size
1051
1052 port@
1053
1054
1055
1056 };
1057 };
1058
1059 hlcdc_pwm: hl
1060 compa
1061 #pwm-
1062 };
1063 };
1064
1065 flx9: flexcom@f804000
1066 compatible =
1067 reg = <0xf804
1068 clocks = <&pm
1069 #address-cell
1070 #size-cells =
1071 ranges = <0x0
1072 status = "dis
1073
1074 uart9: serial
1075 compa
1076 reg =
1077 inter
1078 dmas
1079
1080
1081
1082
1083
1084
1085
1086 dma-n
1087 clock
1088 clock
1089 atmel
1090 atmel
1091 atmel
1092 statu
1093 };
1094
1095 i2c9: i2c@600
1096 compa
1097 reg =
1098 inter
1099 #addr
1100 #size
1101 clock
1102 dmas
1103
1104
1105
1106
1107
1108
1109
1110 dma-n
1111 atmel
1112 statu
1113 };
1114 };
1115
1116 flx10: flexcom@f80440
1117 compatible =
1118 reg = <0xf804
1119 clocks = <&pm
1120 #address-cell
1121 #size-cells =
1122 ranges = <0x0
1123 status = "dis
1124
1125 uart10: seria
1126 compa
1127 reg =
1128 inter
1129 dmas
1130
1131
1132
1133
1134
1135
1136
1137 dma-n
1138 clock
1139 clock
1140 atmel
1141 atmel
1142 atmel
1143 statu
1144 };
1145
1146 i2c10: i2c@60
1147 compa
1148 reg =
1149 inter
1150 #addr
1151 #size
1152 clock
1153 dmas
1154
1155
1156
1157
1158
1159
1160
1161 dma-n
1162 atmel
1163 statu
1164 };
1165 };
1166
1167 isi: isi@f8048000 {
1168 compatible =
1169 reg = <0xf804
1170 interrupts =
1171 clocks = <&pm
1172 clock-names =
1173 status = "dis
1174 port {
1175 #addr
1176 #size
1177 };
1178 };
1179
1180 adc: adc@f804c000 {
1181 compatible =
1182 reg = <0xf804
1183 interrupts =
1184 clocks = <&pm
1185 clock-names =
1186 dmas = <&dma0
1187 dma-names = "
1188 atmel,min-sam
1189 atmel,max-sam
1190 atmel,startup
1191 atmel,trigger
1192 #io-channel-c
1193 status = "dis
1194 };
1195
1196 sfr: sfr@f8050000 {
1197 compatible =
1198 reg = <0xf805
1199 };
1200
1201 matrix: matrix@ffffde
1202 compatible =
1203 reg = <0xffff
1204 };
1205
1206 pmecc: ecc-engine@fff
1207 compatible =
1208 reg = <0xffff
1209 <0xffff
1210 };
1211
1212 mpddrc: mpddrc@ffffe8
1213 compatible =
1214 reg = <0xffff
1215 clocks = <&pm
1216 clock-names =
1217 };
1218
1219 smc: smc@ffffea00 {
1220 compatible =
1221 reg = <0xffff
1222 };
1223
1224 aic: interrupt-contro
1225 compatible =
1226 #interrupt-ce
1227 interrupt-con
1228 reg = <0xffff
1229 atmel,externa
1230 };
1231
1232 dbgu: serial@fffff200
1233 compatible =
1234 reg = <0xffff
1235 atmel,usart-m
1236 interrupts =
1237 dmas = <&dma0
1238 (AT91
1239 AT91
1240 <&dma0
1241 (AT91
1242 AT91
1243 dma-names = "
1244 clocks = <&pm
1245 clock-names =
1246 status = "dis
1247 };
1248
1249 pinctrl: pinctrl@ffff
1250 #address-cell
1251 #size-cells =
1252 compatible =
1253 ranges = <0xf
1254
1255 /* mux-mask c
1256 atmel,mux-mas
1257
1258
1259
1260
1261
1262
1263
1264 pioA: gpio@ff
1265 compa
1266 reg =
1267 inter
1268 #gpio
1269 gpio-
1270 inter
1271 #inte
1272 clock
1273 };
1274
1275 pioB: gpio@ff
1276 compa
1277 reg =
1278 inter
1279 #gpio
1280 gpio-
1281 #gpio
1282 inter
1283 #inte
1284 clock
1285 };
1286
1287 pioC: gpio@ff
1288 compa
1289 reg =
1290 inter
1291 #gpio
1292 gpio-
1293 inter
1294 #inte
1295 clock
1296 };
1297
1298 pioD: gpio@ff
1299 compa
1300 reg =
1301 inter
1302 #gpio
1303 gpio-
1304 #gpio
1305 inter
1306 #inte
1307 clock
1308 };
1309 };
1310
1311 pmc: clock-controller
1312 compatible =
1313 reg = <0xffff
1314 interrupts =
1315 #clock-cells
1316 clocks = <&cl
1317 clock-names =
1318 };
1319
1320 reset_controller: res
1321 compatible =
1322 reg = <0xffff
1323 clocks = <&cl
1324 };
1325
1326 shutdown_controller:
1327 compatible =
1328 reg = <0xffff
1329 clocks = <&cl
1330 #address-cell
1331 #size-cells =
1332 atmel,wakeup-
1333 atmel,wakeup-
1334 status = "dis
1335 };
1336
1337 rtt: rtc@fffffe20 {
1338 compatible =
1339 reg = <0xffff
1340 interrupts =
1341 clocks = <&cl
1342 };
1343
1344 pit: timer@fffffe40 {
1345 compatible =
1346 reg = <0xffff
1347 interrupts =
1348 clocks = <&pm
1349 };
1350
1351 clk32k: clock-control
1352 compatible =
1353 reg = <0xffff
1354 clocks = <&sl
1355 #clock-cells
1356 };
1357
1358 gpbr: syscon@fffffe60
1359 compatible =
1360 reg = <0xffff
1361 };
1362
1363 rtc: rtc@fffffea8 {
1364 compatible =
1365 reg = <0xffff
1366 interrupts =
1367 clocks = <&cl
1368 };
1369
1370 watchdog: watchdog@ff
1371 compatible =
1372 reg = <0xffff
1373 interrupts =
1374 clocks = <&cl
1375 status = "dis
1376 };
1377 };
1378 };
1379 };
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