1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright 2013 Eukréa Electromatique <deni 4 * Based on imx35-pinfunc.h in the same direct 5 * Copyright 2013 Freescale Semiconductor, Inc 6 */ 7 8 #ifndef __DTS_IMX25_PINFUNC_H 9 #define __DTS_IMX25_PINFUNC_H 10 11 /* 12 * The pin function ID is a tuple of 13 * <mux_reg conf_reg input_reg mux_mode input_ 14 */ 15 16 #define MX25_PAD_A10__A10 17 #define MX25_PAD_A10__GPIO_4_0 18 19 #define MX25_PAD_A13__A13 20 #define MX25_PAD_A13__GPIO_4_1 21 #define MX25_PAD_A13__LCDC_CLS 22 23 #define MX25_PAD_A14__A14 24 #define MX25_PAD_A14__GPIO_2_0 25 #define MX25_PAD_A14__SIM1_CLK1 26 #define MX25_PAD_A14__LCDC_SPL 27 28 #define MX25_PAD_A15__A15 29 #define MX25_PAD_A15__GPIO_2_1 30 #define MX25_PAD_A15__SIM1_RST1 31 #define MX25_PAD_A15__LCDC_PS 32 33 #define MX25_PAD_A16__A16 34 #define MX25_PAD_A16__GPIO_2_2 35 #define MX25_PAD_A16__SIM1_VEN1 36 #define MX25_PAD_A16__LCDC_REV 37 38 #define MX25_PAD_A17__A17 39 #define MX25_PAD_A17__GPIO_2_3 40 #define MX25_PAD_A17__SIM1_TX 41 #define MX25_PAD_A17__FEC_TX_ERR 42 43 #define MX25_PAD_A18__A18 44 #define MX25_PAD_A18__GPIO_2_4 45 #define MX25_PAD_A18__SIM1_PD1 46 #define MX25_PAD_A18__FEC_COL 47 48 #define MX25_PAD_A19__A19 49 #define MX25_PAD_A19__GPIO_2_5 50 #define MX25_PAD_A19__SIM1_RX1 51 #define MX25_PAD_A19__FEC_RX_ERR 52 53 #define MX25_PAD_A20__A20 54 #define MX25_PAD_A20__GPIO_2_6 55 #define MX25_PAD_A20__SIM2_CLK1 56 #define MX25_PAD_A20__FEC_RDATA2 57 58 #define MX25_PAD_A21__A21 59 #define MX25_PAD_A21__GPIO_2_7 60 #define MX25_PAD_A21__SIM2_RST1 61 #define MX25_PAD_A21__FEC_RDATA3 62 63 #define MX25_PAD_A22__A22 64 #define MX25_PAD_A22__GPIO_2_8 65 #define MX25_PAD_A22__SIM2_VEN1 66 #define MX25_PAD_A22__FEC_TDATA2 67 68 #define MX25_PAD_A23__A23 69 #define MX25_PAD_A23__GPIO_2_9 70 #define MX25_PAD_A23__SIM2_TX1 71 #define MX25_PAD_A23__FEC_TDATA3 72 73 #define MX25_PAD_A24__A24 74 #define MX25_PAD_A24__GPIO_2_10 75 #define MX25_PAD_A24__SIM2_PD1 76 #define MX25_PAD_A24__FEC_RX_CLK 77 78 #define MX25_PAD_A25__A25 79 #define MX25_PAD_A25__GPIO_2_11 80 #define MX25_PAD_A25__FEC_CRS 81 82 #define MX25_PAD_EB0__EB0 83 #define MX25_PAD_EB0__AUD4_TXD 84 #define MX25_PAD_EB0__GPIO_2_12 85 #define MX25_PAD_EB0__CSPI3_SS0 86 87 #define MX25_PAD_EB1__EB1 88 #define MX25_PAD_EB1__AUD4_RXD 89 #define MX25_PAD_EB1__GPIO_2_13 90 #define MX25_PAD_EB1__CSPI3_SS1 91 92 #define MX25_PAD_OE__OE 93 #define MX25_PAD_OE__AUD4_TXC 94 #define MX25_PAD_OE__GPIO_2_14 95 96 #define MX25_PAD_CS0__CS0 97 #define MX25_PAD_CS0__GPIO_4_2 98 99 #define MX25_PAD_CS1__CS1 100 #define MX25_PAD_CS1__NF_CE3 101 #define MX25_PAD_CS1__GPIO_4_3 102 103 #define MX25_PAD_CS4__CS4 104 #define MX25_PAD_CS4__NF_CE1 105 #define MX25_PAD_CS4__UART5_CTS 106 #define MX25_PAD_CS4__GPIO_3_20 107 #define MX25_PAD_CS4__CSPI3_MOSI 108 109 #define MX25_PAD_CS5__CS5 110 #define MX25_PAD_CS5__NF_CE2 111 #define MX25_PAD_CS5__UART5_RTS 112 #define MX25_PAD_CS5__GPIO_3_21 113 #define MX25_PAD_CS5__CSPI3_MISO 114 115 #define MX25_PAD_NF_CE0__NF_CE0 116 #define MX25_PAD_NF_CE0__CSPI1_SS3 117 #define MX25_PAD_NF_CE0__GPIO_3_22 118 119 #define MX25_PAD_ECB__ECB 120 #define MX25_PAD_ECB__UART5_TXD 121 #define MX25_PAD_ECB__GPIO_3_23 122 #define MX25_PAD_ECB__CSPI3_SCLK 123 124 #define MX25_PAD_LBA__LBA 125 #define MX25_PAD_LBA__UART5_RXD 126 #define MX25_PAD_LBA__GPIO_3_24 127 #define MX25_PAD_LBA__CSPI3_RDY 128 129 #define MX25_PAD_BCLK__BCLK 130 #define MX25_PAD_BCLK__GPIO_4_4 131 132 #define MX25_PAD_RW__RW 133 #define MX25_PAD_RW__AUD4_TXFS 134 #define MX25_PAD_RW__GPIO_3_25 135 136 #define MX25_PAD_NFWE_B__NFWE_B 137 #define MX25_PAD_NFWE_B__GPIO_3_26 138 139 #define MX25_PAD_NFRE_B__NFRE_B 140 #define MX25_PAD_NFRE_B__GPIO_3_27 141 142 #define MX25_PAD_NFALE__NFALE 143 #define MX25_PAD_NFALE__GPIO_3_28 144 145 #define MX25_PAD_NFCLE__NFCLE 146 #define MX25_PAD_NFCLE__GPIO_3_29 147 148 #define MX25_PAD_NFWP_B__NFWP_B 149 #define MX25_PAD_NFWP_B__GPIO_3_30 150 151 #define MX25_PAD_NFRB__NFRB 152 #define MX25_PAD_NFRB__GPIO_3_31 153 154 #define MX25_PAD_D15__D15 155 #define MX25_PAD_D15__LD16 156 #define MX25_PAD_D15__GPIO_4_5 157 #define MX25_PAD_D15__ESDHC1_DAT7 158 159 #define MX25_PAD_D14__D14 160 #define MX25_PAD_D14__LD17 161 #define MX25_PAD_D14__GPIO_4_6 162 #define MX25_PAD_D14__ESDHC1_DAT6 163 164 #define MX25_PAD_D13__D13 165 #define MX25_PAD_D13__LD18 166 #define MX25_PAD_D13__GPIO_4_7 167 #define MX25_PAD_D13__ESDHC1_DAT5 168 169 #define MX25_PAD_D12__D12 170 #define MX25_PAD_D12__GPIO_4_8 171 #define MX25_PAD_D12__ESDHC1_DAT4 172 173 #define MX25_PAD_D11__D11 174 #define MX25_PAD_D11__GPIO_4_9 175 #define MX25_PAD_D11__USBOTG_PWR 176 177 #define MX25_PAD_D10__D10 178 #define MX25_PAD_D10__GPIO_4_10 179 #define MX25_PAD_D10__USBOTG_OC 180 181 #define MX25_PAD_D9__D9 182 #define MX25_PAD_D9__GPIO_4_11 183 #define MX25_PAD_D9__USBH2_PWR 184 185 #define MX25_PAD_D8__D8 186 #define MX25_PAD_D8__GPIO_4_12 187 #define MX25_PAD_D8__USBH2_OC 188 189 #define MX25_PAD_D7__D7 190 #define MX25_PAD_D7__GPIO_4_13 191 192 #define MX25_PAD_D6__D6 193 #define MX25_PAD_D6__GPIO_4_14 194 195 #define MX25_PAD_D5__D5 196 #define MX25_PAD_D5__GPIO_4_15 197 198 #define MX25_PAD_D4__D4 199 #define MX25_PAD_D4__GPIO_4_16 200 201 #define MX25_PAD_D3__D3 202 #define MX25_PAD_D3__GPIO_4_17 203 204 #define MX25_PAD_D2__D2 205 #define MX25_PAD_D2__GPIO_4_18 206 207 #define MX25_PAD_D1__D1 208 #define MX25_PAD_D1__GPIO_4_19 209 210 #define MX25_PAD_D0__D0 211 #define MX25_PAD_D0__GPIO_4_20 212 213 #define MX25_PAD_LD0__LD0 214 #define MX25_PAD_LD0__CSI_D0 215 #define MX25_PAD_LD0__GPIO_2_15 216 217 #define MX25_PAD_LD1__LD1 218 #define MX25_PAD_LD1__CSI_D1 219 #define MX25_PAD_LD1__GPIO_2_16 220 221 #define MX25_PAD_LD2__LD2 222 #define MX25_PAD_LD2__GPIO_2_17 223 224 #define MX25_PAD_LD3__LD3 225 #define MX25_PAD_LD3__GPIO_2_18 226 227 #define MX25_PAD_LD4__LD4 228 #define MX25_PAD_LD4__GPIO_2_19 229 230 #define MX25_PAD_LD5__LD5 231 #define MX25_PAD_LD5__GPIO_1_19 232 233 #define MX25_PAD_LD6__LD6 234 #define MX25_PAD_LD6__GPIO_1_20 235 236 #define MX25_PAD_LD7__LD7 237 #define MX25_PAD_LD7__GPIO_1_21 238 239 #define MX25_PAD_LD8__LD8 240 #define MX25_PAD_LD8__UART4_RXD 241 #define MX25_PAD_LD8__FEC_TX_ERR 242 /* SION must be set; see the comment for MX25_ 243 #define MX25_PAD_LD8__ESDHC2_CMD 244 245 #define MX25_PAD_LD9__LD9 246 #define MX25_PAD_LD9__UART4_TXD 247 #define MX25_PAD_LD9__FEC_COL 248 #define MX25_PAD_LD9__ESDHC2_CLK 249 250 #define MX25_PAD_LD10__LD10 251 #define MX25_PAD_LD10__UART4_RTS 252 #define MX25_PAD_LD10__FEC_RX_ERR 253 254 #define MX25_PAD_LD11__LD11 255 #define MX25_PAD_LD11__UART4_CTS 256 #define MX25_PAD_LD11__FEC_RDATA2 257 #define MX25_PAD_LD11__ESDHC2_DAT1 258 259 #define MX25_PAD_LD12__LD12 260 #define MX25_PAD_LD12__CSPI2_MOSI 261 #define MX25_PAD_LD12__KPP_ROW6 262 #define MX25_PAD_LD12__FEC_RDATA3 263 264 #define MX25_PAD_LD13__LD13 265 #define MX25_PAD_LD13__CSPI2_MISO 266 #define MX25_PAD_LD13__KPP_ROW7 267 #define MX25_PAD_LD13__FEC_TDATA2 268 269 #define MX25_PAD_LD14__LD14 270 #define MX25_PAD_LD14__CSPI2_SCLK 271 #define MX25_PAD_LD14__FEC_TDATA3 272 273 #define MX25_PAD_LD15__LD15 274 #define MX25_PAD_LD15__CSPI2_RDY 275 #define MX25_PAD_LD15__FEC_RX_CLK 276 277 #define MX25_PAD_HSYNC__HSYNC 278 #define MX25_PAD_HSYNC__GPIO_1_22 279 280 #define MX25_PAD_VSYNC__VSYNC 281 #define MX25_PAD_VSYNC__GPIO_1_23 282 283 #define MX25_PAD_LSCLK__LSCLK 284 #define MX25_PAD_LSCLK__GPIO_1_24 285 286 #define MX25_PAD_OE_ACD__OE_ACD 287 #define MX25_PAD_OE_ACD__CSPI2_SS0 288 #define MX25_PAD_OE_ACD__GPIO_1_25 289 290 #define MX25_PAD_CONTRAST__CONTRAST 291 #define MX25_PAD_CONTRAST__GPT4_CAPIN1 292 #define MX25_PAD_CONTRAST__CSPI2_SS1 293 #define MX25_PAD_CONTRAST__PWM4_PWMO 294 #define MX25_PAD_CONTRAST__FEC_CRS 295 #define MX25_PAD_CONTRAST__USBH2_PWR 296 297 #define MX25_PAD_PWM__PWM 298 #define MX25_PAD_PWM__GPIO_1_26 299 #define MX25_PAD_PWM__USBH2_OC 300 301 #define MX25_PAD_CSI_D2__CSI_D2 302 #define MX25_PAD_CSI_D2__UART5_RXD 303 #define MX25_PAD_CSI_D2__SIM1_CLK0 304 #define MX25_PAD_CSI_D2__GPIO_1_27 305 #define MX25_PAD_CSI_D2__CSPI3_MOSI 306 307 #define MX25_PAD_CSI_D3__CSI_D3 308 #define MX25_PAD_CSI_D3__UART5_TXD 309 #define MX25_PAD_CSI_D3__SIM1_RST0 310 #define MX25_PAD_CSI_D3__GPIO_1_28 311 #define MX25_PAD_CSI_D3__CSPI3_MISO 312 313 #define MX25_PAD_CSI_D4__CSI_D4 314 #define MX25_PAD_CSI_D4__UART5_RTS 315 #define MX25_PAD_CSI_D4__SIM1_VEN0 316 #define MX25_PAD_CSI_D4__GPIO_1_29 317 #define MX25_PAD_CSI_D4__CSPI3_SCLK 318 319 #define MX25_PAD_CSI_D5__CSI_D5 320 #define MX25_PAD_CSI_D5__UART5_CTS 321 #define MX25_PAD_CSI_D5__SIM1_TX0 322 #define MX25_PAD_CSI_D5__GPIO_1_30 323 #define MX25_PAD_CSI_D5__CSPI3_RDY 324 325 #define MX25_PAD_CSI_D6__CSI_D6 326 /* SION must be set; see the comment for MX25_ 327 #define MX25_PAD_CSI_D6__ESDHC2_CMD 328 #define MX25_PAD_CSI_D6__SIM1_PD0 329 #define MX25_PAD_CSI_D6__GPIO_1_31 330 #define MX25_PAD_CSI_D6__CSPI3_SS0 331 332 #define MX25_PAD_CSI_D7__CSI_D7 333 #define MX25_PAD_CSI_D7__ESDHC2_CLK 334 #define MX25_PAD_CSI_D7__GPIO_1_6 335 #define MX25_PAD_CSI_D7__CSPI3_SS1 336 337 #define MX25_PAD_CSI_D8__CSI_D8 338 #define MX25_PAD_CSI_D8__AUD6_RXC 339 #define MX25_PAD_CSI_D8__GPIO_1_7 340 #define MX25_PAD_CSI_D8__CSPI3_SS2 341 342 #define MX25_PAD_CSI_D9__CSI_D9 343 #define MX25_PAD_CSI_D9__AUD6_RXFS 344 #define MX25_PAD_CSI_D9__GPIO_4_21 345 #define MX25_PAD_CSI_D9__CSPI3_SS3 346 347 #define MX25_PAD_CSI_MCLK__CSI_MCLK 348 #define MX25_PAD_CSI_MCLK__AUD6_TXD 349 #define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 350 #define MX25_PAD_CSI_MCLK__GPIO_1_8 351 352 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC 353 #define MX25_PAD_CSI_VSYNC__AUD6_RXD 354 #define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 355 #define MX25_PAD_CSI_VSYNC__GPIO_1_9 356 357 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC 358 #define MX25_PAD_CSI_HSYNC__AUD6_TXC 359 #define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 360 #define MX25_PAD_CSI_HSYNC__GPIO_1_10 361 362 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 363 #define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 364 #define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 365 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11 366 367 #define MX25_PAD_I2C1_CLK__I2C1_CLK 368 #define MX25_PAD_I2C1_CLK__GPIO_1_12 369 370 #define MX25_PAD_I2C1_DAT__I2C1_DAT 371 #define MX25_PAD_I2C1_DAT__GPIO_1_13 372 373 #define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 374 #define MX25_PAD_CSPI1_MOSI__UART3_RXD 375 #define MX25_PAD_CSPI1_MOSI__GPIO_1_14 376 377 #define MX25_PAD_CSPI1_MISO__CSPI1_MISO 378 #define MX25_PAD_CSPI1_MISO__UART3_TXD 379 #define MX25_PAD_CSPI1_MISO__GPIO_1_15 380 381 #define MX25_PAD_CSPI1_SS0__CSPI1_SS0 382 #define MX25_PAD_CSPI1_SS0__PWM2_PWMO 383 #define MX25_PAD_CSPI1_SS0__GPIO_1_16 384 385 #define MX25_PAD_CSPI1_SS1__CSPI1_SS1 386 #define MX25_PAD_CSPI1_SS1__I2C3_DAT 387 #define MX25_PAD_CSPI1_SS1__UART3_RTS 388 #define MX25_PAD_CSPI1_SS1__GPIO_1_17 389 390 #define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 391 #define MX25_PAD_CSPI1_SCLK__UART3_CTS 392 #define MX25_PAD_CSPI1_SCLK__GPIO_1_18 393 394 #define MX25_PAD_CSPI1_RDY__CSPI1_RDY 395 #define MX25_PAD_CSPI1_RDY__GPIO_2_22 396 397 #define MX25_PAD_UART1_RXD__UART1_RXD 398 #define MX25_PAD_UART1_RXD__UART2_DTR 399 #define MX25_PAD_UART1_RXD__GPIO_4_22 400 401 #define MX25_PAD_UART1_TXD__UART1_TXD 402 #define MX25_PAD_UART1_TXD__UART2_DSR 403 #define MX25_PAD_UART1_TXD__GPIO_4_23 404 405 #define MX25_PAD_UART1_RTS__UART1_RTS 406 #define MX25_PAD_UART1_RTS__CSI_D0 407 #define MX25_PAD_UART1_RTS__GPT3_CAPIN1 408 #define MX25_PAD_UART1_RTS__UART2_DCD 409 #define MX25_PAD_UART1_RTS__GPIO_4_24 410 411 #define MX25_PAD_UART1_CTS__UART1_CTS 412 #define MX25_PAD_UART1_CTS__CSI_D1 413 #define MX25_PAD_UART1_CTS__UART2_RI 414 #define MX25_PAD_UART1_CTS__GPIO_4_25 415 416 #define MX25_PAD_UART2_RXD__UART2_RXD 417 #define MX25_PAD_UART2_RXD__GPIO_4_26 418 419 #define MX25_PAD_UART2_TXD__UART2_TXD 420 #define MX25_PAD_UART2_TXD__GPIO_4_27 421 422 #define MX25_PAD_UART2_RTS__UART2_RTS 423 #define MX25_PAD_UART2_RTS__FEC_COL 424 #define MX25_PAD_UART2_RTS__GPT1_CAPIN1 425 #define MX25_PAD_UART2_RTS__GPIO_4_28 426 #define MX25_PAD_UART2_RTS__CSPI2_SS3 427 428 #define MX25_PAD_UART2_CTS__UART2_CTS 429 #define MX25_PAD_UART2_CTS__FEC_RX_ERR 430 #define MX25_PAD_UART2_CTS__GPIO_4_29 431 #define MX25_PAD_UART2_CTS__CSPI3_SS3 432 433 /* 434 * Removing the SION bit from MX25_PAD_*__ESDH 435 * card. According to the i.MX25 reference man 436 * Rev. 2 from 01/2011) this pin is bidirectio 437 * bug that configuring the ESDHCn_CMD functio 438 * for this pin. 439 * This might have side effects for other hard 440 * that pin and use the respective function as 441 */ 442 #define MX25_PAD_SD1_CMD__ESDHC1_CMD 443 #define MX25_PAD_SD1_CMD__CSPI2_MOSI 444 #define MX25_PAD_SD1_CMD__FEC_RDATA2 445 #define MX25_PAD_SD1_CMD__GPIO_2_23 446 447 #define MX25_PAD_SD1_CLK__ESDHC1_CLK 448 #define MX25_PAD_SD1_CLK__CSPI2_MISO 449 #define MX25_PAD_SD1_CLK__FEC_RDATA3 450 #define MX25_PAD_SD1_CLK__GPIO_2_24 451 452 #define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 453 #define MX25_PAD_SD1_DATA0__CSPI2_SCLK 454 #define MX25_PAD_SD1_DATA0__GPIO_2_25 455 456 #define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 457 #define MX25_PAD_SD1_DATA1__CSPI2_RDY 458 #define MX25_PAD_SD1_DATA1__AUD7_RXD 459 #define MX25_PAD_SD1_DATA1__GPIO_2_26 460 461 #define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 462 #define MX25_PAD_SD1_DATA2__CSPI2_SS0 463 #define MX25_PAD_SD1_DATA2__FEC_RX_CLK 464 #define MX25_PAD_SD1_DATA2__GPIO_2_27 465 466 #define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 467 #define MX25_PAD_SD1_DATA3__CSPI2_SS1 468 #define MX25_PAD_SD1_DATA3__FEC_CRS 469 #define MX25_PAD_SD1_DATA3__GPIO_2_28 470 471 #define MX25_PAD_KPP_ROW0__KPP_ROW0 472 #define MX25_PAD_KPP_ROW0__UART3_RXD 473 #define MX25_PAD_KPP_ROW0__UART1_DTR 474 #define MX25_PAD_KPP_ROW0__GPIO_2_29 475 476 #define MX25_PAD_KPP_ROW1__KPP_ROW1 477 #define MX25_PAD_KPP_ROW1__UART3_TXD 478 #define MX25_PAD_KPP_ROW1__UART1_DSR 479 #define MX25_PAD_KPP_ROW1__GPIO_2_30 480 481 #define MX25_PAD_KPP_ROW2__KPP_ROW2 482 #define MX25_PAD_KPP_ROW2__UART3_RTS 483 #define MX25_PAD_KPP_ROW2__CSI_D0 484 #define MX25_PAD_KPP_ROW2__UART1_DCD 485 #define MX25_PAD_KPP_ROW2__GPIO_2_31 486 487 #define MX25_PAD_KPP_ROW3__KPP_ROW3 488 #define MX25_PAD_KPP_ROW3__UART3_CTS 489 #define MX25_PAD_KPP_ROW3__CSI_D1 490 #define MX25_PAD_KPP_ROW3__UART1_RI 491 #define MX25_PAD_KPP_ROW3__GPIO_3_0 492 493 #define MX25_PAD_KPP_COL0__KPP_COL0 494 #define MX25_PAD_KPP_COL0__UART4_RXD 495 #define MX25_PAD_KPP_COL0__AUD5_TXD 496 #define MX25_PAD_KPP_COL0__GPIO_3_1 497 498 #define MX25_PAD_KPP_COL1__KPP_COL1 499 #define MX25_PAD_KPP_COL1__UART4_TXD 500 #define MX25_PAD_KPP_COL1__AUD5_RXD 501 #define MX25_PAD_KPP_COL1__GPIO_3_2 502 503 #define MX25_PAD_KPP_COL2__KPP_COL2 504 #define MX25_PAD_KPP_COL2__UART4_RTS 505 #define MX25_PAD_KPP_COL2__AUD5_TXC 506 #define MX25_PAD_KPP_COL2__GPIO_3_3 507 508 #define MX25_PAD_KPP_COL3__KPP_COL3 509 #define MX25_PAD_KPP_COL3__UART4_CTS 510 #define MX25_PAD_KPP_COL3__AUD5_TXFS 511 #define MX25_PAD_KPP_COL3__GPIO_3_4 512 513 #define MX25_PAD_FEC_MDC__FEC_MDC 514 /* SION must be set; see the comment for MX25_ 515 #define MX25_PAD_FEC_MDC__ESDHC2_CMD 516 #define MX25_PAD_FEC_MDC__AUD4_TXD 517 #define MX25_PAD_FEC_MDC__GPIO_3_5 518 519 #define MX25_PAD_FEC_MDIO__FEC_MDIO 520 #define MX25_PAD_FEC_MDIO__AUD4_RXD 521 #define MX25_PAD_FEC_MDIO__GPIO_3_6 522 523 #define MX25_PAD_FEC_TDATA0__FEC_TDATA0 524 #define MX25_PAD_FEC_TDATA0__GPIO_3_7 525 526 #define MX25_PAD_FEC_TDATA1__FEC_TDATA1 527 #define MX25_PAD_FEC_TDATA1__AUD4_TXFS 528 #define MX25_PAD_FEC_TDATA1__GPIO_3_8 529 530 #define MX25_PAD_FEC_TX_EN__FEC_TX_EN 531 #define MX25_PAD_FEC_TX_EN__GPIO_3_9 532 #define MX25_PAD_FEC_TX_EN__KPP_ROW4 533 534 #define MX25_PAD_FEC_RDATA0__FEC_RDATA0 535 #define MX25_PAD_FEC_RDATA0__GPIO_3_10 536 #define MX25_PAD_FEC_RDATA0__KPP_ROW5 537 538 #define MX25_PAD_FEC_RDATA1__FEC_RDATA1 539 /* 540 * According to the i.MX25 Reference manual (I 541 * 01/2011) this is CAN1_TX but that's wrong. 542 */ 543 #define MX25_PAD_FEC_RDATA1__CAN2_TX 544 #define MX25_PAD_FEC_RDATA1__GPIO_3_11 545 546 #define MX25_PAD_FEC_RX_DV__FEC_RX_DV 547 /* 548 * According to the i.MX25 Reference manual (I 549 * 01/2011) this is CAN1_RX but that's wrong. 550 */ 551 #define MX25_PAD_FEC_RX_DV__CAN2_RX 552 #define MX25_PAD_FEC_RX_DV__GPIO_3_12 553 554 #define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 555 #define MX25_PAD_FEC_TX_CLK__GPIO_3_13 556 557 #define MX25_PAD_RTCK__RTCK 558 #define MX25_PAD_RTCK__OWIRE 559 #define MX25_PAD_RTCK__GPIO_3_14 560 561 #define MX25_PAD_TDO__TDO 562 563 #define MX25_PAD_DE_B__DE_B 564 #define MX25_PAD_DE_B__GPIO_2_20 565 566 #define MX25_PAD_GPIO_A__GPIO_1_0 567 #define MX25_PAD_GPIO_A__CAN1_TX 568 #define MX25_PAD_GPIO_A__USBOTG_PWR 569 570 #define MX25_PAD_GPIO_B__GPIO_1_1 571 #define MX25_PAD_GPIO_B__USBOTG_OC 572 #define MX25_PAD_GPIO_B__CAN1_RX 573 574 #define MX25_PAD_GPIO_C__GPIO_1_2 575 #define MX25_PAD_GPIO_C__PWM4_PWMO 576 #define MX25_PAD_GPIO_C__I2C2_SCL 577 #define MX25_PAD_GPIO_C__KPP_COL4 578 #define MX25_PAD_GPIO_C__GPT2_CAPIN1 579 #define MX25_PAD_GPIO_C__CSPI1_SS2 580 #define MX25_PAD_GPIO_C__CAN2_TX 581 #define MX25_PAD_GPIO_C__CSPI2_SS2 582 583 #define MX25_PAD_GPIO_D__GPIO_1_3 584 #define MX25_PAD_GPIO_D__I2C2_SDA 585 #define MX25_PAD_GPIO_D__CAN2_RX 586 #define MX25_PAD_GPIO_D__CSPI3_SS2 587 588 #define MX25_PAD_GPIO_E__GPIO_1_4 589 #define MX25_PAD_GPIO_E__I2C3_CLK 590 #define MX25_PAD_GPIO_E__LD16 591 #define MX25_PAD_GPIO_E__AUD7_TXD 592 #define MX25_PAD_GPIO_E__UART4_RXD 593 594 #define MX25_PAD_GPIO_F__GPIO_1_5 595 #define MX25_PAD_GPIO_F__LD17 596 #define MX25_PAD_GPIO_F__AUD7_TXC 597 #define MX25_PAD_GPIO_F__UART4_TXD 598 599 #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 600 #define MX25_PAD_EXT_ARMCLK__GPIO_3_15 601 602 #define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 603 #define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 604 605 #define MX25_PAD_VSTBY_REQ__VSTBY_REQ 606 #define MX25_PAD_VSTBY_REQ__AUD7_TXFS 607 #define MX25_PAD_VSTBY_REQ__GPIO_3_17 608 #define MX25_PAD_VSTBY_REQ__UART4_RTS 609 610 #define MX25_PAD_VSTBY_ACK__VSTBY_ACK 611 #define MX25_PAD_VSTBY_ACK__CSPI1_SS3 612 #define MX25_PAD_VSTBY_ACK__GPIO_3_18 613 614 #define MX25_PAD_POWER_FAIL__POWER_FAIL 615 #define MX25_PAD_POWER_FAIL__AUD7_RXD 616 #define MX25_PAD_POWER_FAIL__GPIO_3_19 617 #define MX25_PAD_POWER_FAIL__UART4_CTS 618 619 #define MX25_PAD_CLKO__CLKO 620 #define MX25_PAD_CLKO__GPIO_2_21 621 622 #define MX25_PAD_BOOT_MODE0__BOOT_MODE0 623 #define MX25_PAD_BOOT_MODE0__GPIO_4_30 624 625 #define MX25_PAD_BOOT_MODE1__BOOT_MODE1 626 #define MX25_PAD_BOOT_MODE1__GPIO_4_31 627 628 /* 629 * Compatibility defines for out-of-tree users 630 * use of one of them. 631 */ 632 #define MX25_PAD_D15__SDHC1_DAT7 633 #define MX25_PAD_D14__SDHC1_DAT6 634 #define MX25_PAD_D13__SDHC1_DAT5 635 #define MX25_PAD_D12__SDHC1_DAT4 636 #define MX25_PAD_LD8__SDHC2_CMD 637 #define MX25_PAD_LD9__SDHC2_CLK 638 #define MX25_PAD_LD11__SDHC2_DAT1 639 #define MX25_PAD_CSI_D6__SDHC2_CMD 640 #define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 641 #define MX25_PAD_CSI_MCLK__SDHC2_DAT0 642 #define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 643 #define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 644 #define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 645 #define MX25_PAD_SD1_CMD__SD1_CMD 646 #define MX25_PAD_SD1_CLK__SD1_CLK 647 #define MX25_PAD_SD1_DATA0__SD1_DATA0 648 #define MX25_PAD_SD1_DATA1__SD1_DATA1 649 #define MX25_PAD_SD1_DATA2__SD1_DATA2 650 #define MX25_PAD_SD1_DATA3__SD1_DATA3 651 652 #endif /* __DTS_IMX25_PINFUNC_H */ 653
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