1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc 4 * Copyright 2017-2018 NXP. 5 * 6 */ 7 8 #ifndef __DTS_IMX6SLL_PINFUNC_H 9 #define __DTS_IMX6SLL_PINFUNC_H 10 11 /* 12 * The pin function ID is a tuple of 13 * <mux_reg conf_reg input_reg mux_mode input_ 14 */ 15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CL 20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 25 #define MX6SLL_PAD_REF_CLK_24M__SD3_WP 26 #define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CL 27 #define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 28 #define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 29 #define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 30 #define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 31 #define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 32 #define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 33 #define MX6SLL_PAD_PWM1__PWM1_OUT 34 #define MX6SLL_PAD_PWM1__CCM_CLKO 35 #define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 36 #define MX6SLL_PAD_PWM1__CSI_MCLK 37 #define MX6SLL_PAD_PWM1__GPIO3_IO23 38 #define MX6SLL_PAD_PWM1__EPIT1_OUT 39 #define MX6SLL_PAD_KEY_COL0__KEY_COL0 40 #define MX6SLL_PAD_KEY_COL0__I2C2_SCL 41 #define MX6SLL_PAD_KEY_COL0__LCD_DATA00 42 #define MX6SLL_PAD_KEY_COL0__SD1_CD_B 43 #define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 44 #define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 45 #define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 46 #define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 47 #define MX6SLL_PAD_KEY_ROW0__SD1_WP 48 #define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 49 #define MX6SLL_PAD_KEY_COL1__KEY_COL1 50 #define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 51 #define MX6SLL_PAD_KEY_COL1__LCD_DATA02 52 #define MX6SLL_PAD_KEY_COL1__SD3_DATA4 53 #define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 54 #define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 55 #define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 56 #define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 57 #define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 58 #define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 59 #define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 60 #define MX6SLL_PAD_KEY_COL2__KEY_COL2 61 #define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 62 #define MX6SLL_PAD_KEY_COL2__LCD_DATA04 63 #define MX6SLL_PAD_KEY_COL2__CSI_DATA12 64 #define MX6SLL_PAD_KEY_COL2__SD3_DATA6 65 #define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 66 #define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 67 #define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 68 #define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 69 #define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 70 #define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 71 #define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 72 #define MX6SLL_PAD_KEY_COL3__KEY_COL3 73 #define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 74 #define MX6SLL_PAD_KEY_COL3__LCD_DATA06 75 #define MX6SLL_PAD_KEY_COL3__CSI_DATA14 76 #define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 77 #define MX6SLL_PAD_KEY_COL3__SD1_RESET 78 #define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 79 #define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 80 #define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 81 #define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 82 #define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 83 #define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 84 #define MX6SLL_PAD_KEY_COL4__KEY_COL4 85 #define MX6SLL_PAD_KEY_COL4__AUD6_RXD 86 #define MX6SLL_PAD_KEY_COL4__LCD_DATA08 87 #define MX6SLL_PAD_KEY_COL4__CSI_DATA16 88 #define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 89 #define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 90 #define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 91 #define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 92 #define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 93 #define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 94 #define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 95 #define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 96 #define MX6SLL_PAD_KEY_COL5__KEY_COL5 97 #define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 98 #define MX6SLL_PAD_KEY_COL5__LCD_DATA10 99 #define MX6SLL_PAD_KEY_COL5__CSI_DATA18 100 #define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 101 #define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 102 #define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 103 #define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 104 #define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 105 #define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 106 #define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 107 #define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 108 #define MX6SLL_PAD_KEY_COL6__KEY_COL6 109 #define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 110 #define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 111 #define MX6SLL_PAD_KEY_COL6__LCD_DATA12 112 #define MX6SLL_PAD_KEY_COL6__CSI_DATA20 113 #define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 114 #define MX6SLL_PAD_KEY_COL6__SD3_RESET 115 #define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 116 #define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 117 #define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 118 #define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 119 #define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 120 #define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 121 #define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 122 #define MX6SLL_PAD_KEY_COL7__KEY_COL7 123 #define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 124 #define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 125 #define MX6SLL_PAD_KEY_COL7__LCD_DATA14 126 #define MX6SLL_PAD_KEY_COL7__CSI_DATA22 127 #define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 128 #define MX6SLL_PAD_KEY_COL7__SD1_WP 129 #define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 130 #define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 131 #define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 132 #define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 133 #define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 134 #define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 135 #define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 136 #define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 137 #define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 138 #define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 139 #define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 140 #define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 141 #define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 142 #define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 143 #define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 144 #define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 145 #define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 146 #define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 147 #define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 148 #define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 149 #define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 150 #define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 151 #define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 152 #define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 153 #define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 154 #define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 155 #define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 156 #define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 157 #define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 158 #define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 159 #define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 160 #define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 161 #define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 162 #define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 163 #define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 164 #define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 165 #define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 166 #define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 167 #define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 168 #define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 169 #define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 170 #define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 171 #define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 172 #define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 173 #define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 174 #define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 175 #define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 176 #define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 177 #define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 178 #define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 179 #define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 180 #define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 181 #define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 182 #define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 183 #define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 184 #define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 185 #define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 186 #define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 187 #define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 188 #define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 189 #define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 190 #define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 191 #define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 192 #define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 193 #define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 194 #define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 195 #define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 196 #define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 197 #define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 198 #define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 199 #define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 200 #define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 201 #define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 202 #define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 203 #define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 204 #define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 205 #define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 206 #define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 207 #define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 208 #define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 209 #define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 210 #define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 211 #define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 212 #define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 213 #define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 214 #define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 215 #define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 216 #define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 217 #define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 218 #define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 219 #define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 220 #define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 221 #define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 222 #define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 223 #define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 224 #define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 225 #define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 226 #define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 227 #define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 228 #define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 229 #define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 230 #define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 231 #define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 232 #define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 233 #define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 234 #define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 235 #define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 236 #define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 237 #define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 238 #define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 239 #define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 240 #define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 241 #define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 242 #define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 243 #define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 244 #define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 245 #define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 246 #define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 247 #define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 248 #define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 249 #define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 250 #define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 251 #define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 252 #define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 253 #define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 254 #define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 255 #define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 256 #define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 257 #define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 258 #define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 259 #define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 260 #define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 261 #define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 262 #define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 263 #define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 264 #define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 265 #define MX6SLL_PAD_EPDC_GDRL__SD2_WP 266 #define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 267 #define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 268 #define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 269 #define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 270 #define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 271 #define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 272 #define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 273 #define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 274 #define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 275 #define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 276 #define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 277 #define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 278 #define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 279 #define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 280 #define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 281 #define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 282 #define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 283 #define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 284 #define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 285 #define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 286 #define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 287 #define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 288 #define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 289 #define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 290 #define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 291 #define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 292 #define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 293 #define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CT 294 #define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 295 #define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 296 #define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 297 #define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CT 298 #define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 299 #define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 300 #define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 301 #define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CT 302 #define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 303 #define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 304 #define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 305 #define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CT 306 #define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 307 #define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 308 #define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 309 #define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 310 #define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 311 #define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 312 #define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 313 #define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 314 #define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 315 #define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 316 #define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 317 #define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 318 #define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 319 #define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STA 320 #define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 321 #define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 322 #define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 323 #define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 324 #define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAK 325 #define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 326 #define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 327 #define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 328 #define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 329 #define MX6SLL_PAD_LCD_CLK__LCD_CLK 330 #define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 331 #define MX6SLL_PAD_LCD_CLK__PWM4_OUT 332 #define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 333 #define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 334 #define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 335 #define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 336 #define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 337 #define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 338 #define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 339 #define MX6SLL_PAD_LCD_HSYNC__LCD_CS 340 #define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 341 #define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 342 #define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 343 #define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 344 #define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 345 #define MX6SLL_PAD_LCD_VSYNC__LCD_RS 346 #define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 347 #define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 348 #define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 349 #define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 350 #define MX6SLL_PAD_LCD_RESET__LCD_RESET 351 #define MX6SLL_PAD_LCD_RESET__LCD_BUSY 352 #define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 353 #define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 354 #define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 355 #define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 356 #define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 357 #define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 358 #define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 359 #define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 360 #define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 361 #define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 362 #define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 363 #define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 364 #define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 365 #define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 366 #define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 367 #define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 368 #define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 369 #define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 370 #define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 371 #define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 372 #define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 373 #define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 374 #define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 375 #define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 376 #define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 377 #define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 378 #define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 379 #define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 380 #define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 381 #define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 382 #define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 383 #define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 384 #define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 385 #define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 386 #define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 387 #define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 388 #define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 389 #define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 390 #define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 391 #define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_D 392 #define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 393 #define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 394 #define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 395 #define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 396 #define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 397 #define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 398 #define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 399 #define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 400 #define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 401 #define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 402 #define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 403 #define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 404 #define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 405 #define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 406 #define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 407 #define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 408 #define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 409 #define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 410 #define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 411 #define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 412 #define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 413 #define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 414 #define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 415 #define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 416 #define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 417 #define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 418 #define MX6SLL_PAD_LCD_DATA08__KEY_COL0 419 #define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 420 #define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 421 #define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 422 #define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 423 #define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 424 #define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 425 #define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 426 #define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 427 #define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 428 #define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 429 #define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 430 #define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 431 #define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 432 #define MX6SLL_PAD_LCD_DATA10__KEY_COL1 433 #define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 434 #define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 435 #define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 436 #define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 437 #define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 438 #define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 439 #define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 440 #define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 441 #define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 442 #define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 443 #define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 444 #define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 445 #define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 446 #define MX6SLL_PAD_LCD_DATA12__KEY_COL2 447 #define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 448 #define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 449 #define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 450 #define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 451 #define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 452 #define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 453 #define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 454 #define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 455 #define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 456 #define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 457 #define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 458 #define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 459 #define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 460 #define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 461 #define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 462 #define MX6SLL_PAD_LCD_DATA14__KEY_COL3 463 #define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 464 #define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 465 #define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 466 #define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 467 #define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 468 #define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 469 #define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 470 #define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 471 #define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 472 #define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 473 #define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 474 #define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 475 #define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 476 #define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 477 #define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 478 #define MX6SLL_PAD_LCD_DATA16__KEY_COL4 479 #define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 480 #define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 481 #define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 482 #define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 483 #define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 484 #define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 485 #define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 486 #define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 487 #define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 488 #define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 489 #define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 490 #define MX6SLL_PAD_LCD_DATA18__KEY_COL5 491 #define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 492 #define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 493 #define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 494 #define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 495 #define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 496 #define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 497 #define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 498 #define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 499 #define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 500 #define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 501 #define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 502 #define MX6SLL_PAD_LCD_DATA20__KEY_COL6 503 #define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 504 #define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 505 #define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 506 #define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 507 #define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 508 #define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 509 #define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 510 #define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 511 #define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 512 #define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 513 #define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 514 #define MX6SLL_PAD_LCD_DATA22__KEY_COL7 515 #define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 516 #define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 517 #define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 518 #define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 519 #define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 520 #define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 521 #define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 522 #define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 523 #define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 524 #define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 525 #define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 526 #define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 527 #define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 528 #define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 529 #define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 530 #define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 531 #define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 532 #define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 533 #define MX6SLL_PAD_AUD_RXC__AUD3_RXC 534 #define MX6SLL_PAD_AUD_RXC__I2C1_SDA 535 #define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 536 #define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 537 #define MX6SLL_PAD_AUD_RXC__I2C3_SDA 538 #define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 539 #define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 540 #define MX6SLL_PAD_AUD_RXD__AUD3_RXD 541 #define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 542 #define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 543 #define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 544 #define MX6SLL_PAD_AUD_RXD__SD1_LCTL 545 #define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 546 #define MX6SLL_PAD_AUD_TXC__AUD3_TXC 547 #define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 548 #define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 549 #define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 550 #define MX6SLL_PAD_AUD_TXC__SD2_LCTL 551 #define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 552 #define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 553 #define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 554 #define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 555 #define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 556 #define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 557 #define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 558 #define MX6SLL_PAD_AUD_TXD__AUD3_TXD 559 #define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 560 #define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 561 #define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 562 #define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 563 #define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 564 #define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 565 #define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 566 #define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 567 #define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 568 #define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 569 #define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 570 #define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 571 #define MX6SLL_PAD_UART1_RXD__PWM1_OUT 572 #define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 573 #define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 574 #define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 575 #define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 576 #define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 577 #define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 578 #define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 579 #define MX6SLL_PAD_UART1_TXD__PWM2_OUT 580 #define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 581 #define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 582 #define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 583 #define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 584 #define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 585 #define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 586 #define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 587 #define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 588 #define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 589 #define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 590 #define MX6SLL_PAD_I2C1_SCL__SD3_RESET 591 #define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 592 #define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 593 #define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 594 #define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 595 #define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 596 #define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 597 #define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 598 #define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 599 #define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 600 #define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 601 #define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 602 #define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 603 #define MX6SLL_PAD_I2C2_SCL__SD3_WP 604 #define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 605 #define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 606 #define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 607 #define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 608 #define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 609 #define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 610 #define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 611 #define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 612 #define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 613 #define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 614 #define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 615 #define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 616 #define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 617 #define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 618 #define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 619 #define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 620 #define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 621 #define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 622 #define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 623 #define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 624 #define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 625 #define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 626 #define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 627 #define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 628 #define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 629 #define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 630 #define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 631 #define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 632 #define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 633 #define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 634 #define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 635 #define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 636 #define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 637 #define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 638 #define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 639 #define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 640 #define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 641 #define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 642 #define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 643 #define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 644 #define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 645 #define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 646 #define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 647 #define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 648 #define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 649 #define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 650 #define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT 651 #define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 652 #define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 653 #define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 654 #define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 655 #define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 656 #define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 657 #define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT 658 #define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 659 #define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 660 #define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 661 #define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 662 #define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 663 #define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 664 #define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 665 #define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 666 #define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 667 #define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 668 #define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 669 #define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 670 #define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 671 #define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 672 #define MX6SLL_PAD_SD1_CLK__SD1_CLK 673 #define MX6SLL_PAD_SD1_CLK__KEY_COL0 674 #define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 675 #define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 676 #define MX6SLL_PAD_SD1_CMD__SD1_CMD 677 #define MX6SLL_PAD_SD1_CMD__KEY_ROW0 678 #define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 679 #define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 680 #define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 681 #define MX6SLL_PAD_SD1_DATA0__KEY_COL1 682 #define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 683 #define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 684 #define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 685 #define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 686 #define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 687 #define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 688 #define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 689 #define MX6SLL_PAD_SD1_DATA2__KEY_COL2 690 #define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 691 #define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 692 #define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 693 #define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 694 #define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 695 #define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 696 #define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 697 #define MX6SLL_PAD_SD1_DATA4__KEY_COL3 698 #define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 699 #define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 700 #define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 701 #define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 702 #define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 703 #define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 704 #define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 705 #define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 706 #define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 707 #define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 708 #define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 709 #define MX6SLL_PAD_SD1_DATA6__KEY_COL4 710 #define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 711 #define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 712 #define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 713 #define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 714 #define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 715 #define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 716 #define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 717 #define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 718 #define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 719 #define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 720 #define MX6SLL_PAD_SD2_RESET__SD2_RESET 721 #define MX6SLL_PAD_SD2_RESET__WDOG2_B 722 #define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 723 #define MX6SLL_PAD_SD2_RESET__CSI_MCLK 724 #define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 725 #define MX6SLL_PAD_SD2_CLK__SD2_CLK 726 #define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 727 #define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 728 #define MX6SLL_PAD_SD2_CLK__CSI_DATA00 729 #define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 730 #define MX6SLL_PAD_SD2_CMD__SD2_CMD 731 #define MX6SLL_PAD_SD2_CMD__AUD4_RXC 732 #define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 733 #define MX6SLL_PAD_SD2_CMD__CSI_DATA01 734 #define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 735 #define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 736 #define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 737 #define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 738 #define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 739 #define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 740 #define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 741 #define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 742 #define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 743 #define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 744 #define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 745 #define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 746 #define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 747 #define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 748 #define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 749 #define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 750 #define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 751 #define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 752 #define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 753 #define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 754 #define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 755 #define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 756 #define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 757 #define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 758 #define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 759 #define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 760 #define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 761 #define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 762 #define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 763 #define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 764 #define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 765 #define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 766 #define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 767 #define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 768 #define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 769 #define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 770 #define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 771 #define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 772 #define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 773 #define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 774 #define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 775 #define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 776 #define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 777 #define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 778 #define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 779 #define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 780 #define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 781 #define MX6SLL_PAD_SD2_DATA6__SD2_WP 782 #define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 783 #define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 784 #define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 785 #define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 786 #define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 787 #define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 788 #define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 789 #define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 790 #define MX6SLL_PAD_SD3_CLK__SD3_CLK 791 #define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 792 #define MX6SLL_PAD_SD3_CLK__KEY_COL5 793 #define MX6SLL_PAD_SD3_CLK__CSI_DATA10 794 #define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 795 #define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 796 #define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 797 #define MX6SLL_PAD_SD3_CMD__SD3_CMD 798 #define MX6SLL_PAD_SD3_CMD__AUD5_RXC 799 #define MX6SLL_PAD_SD3_CMD__KEY_ROW5 800 #define MX6SLL_PAD_SD3_CMD__CSI_DATA11 801 #define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 802 #define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 803 #define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 804 #define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 805 #define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 806 #define MX6SLL_PAD_SD3_DATA0__KEY_COL6 807 #define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 808 #define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 809 #define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 810 #define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 811 #define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 812 #define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 813 #define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 814 #define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 815 #define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 816 #define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 817 #define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 818 #define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 819 #define MX6SLL_PAD_SD3_DATA2__KEY_COL7 820 #define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 821 #define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 822 #define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 823 #define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 824 #define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 825 #define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 826 #define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 827 #define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 828 #define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 829 #define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 830 #define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 831 #define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 832 #define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 833 #define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 834 #define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 835 #define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 836 #define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 837 #define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 838 #define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 839 #define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 840 #define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 841 #define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 842 #define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 843 #define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 844 #define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 845 #define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 846 #define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 847 #define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 848 #define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 849 #define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 850 #define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 851 #define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 852 #define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 853 #define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 854 #define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 855 #define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 856 #define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 857 #define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 858 #define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 859 #define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 860 #define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 861 #define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 862 #define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 863 #define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 864 #define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 865 #define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 866 #define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 867 #define MX6SLL_PAD_GPIO4_IO22__SD1_WP 868 #define MX6SLL_PAD_GPIO4_IO22__SD3_WP 869 #define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 870 #define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 871 #define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 872 #define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 873 #define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 874 #define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 875 #define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 876 #define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 877 #define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 878 #define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 879 880 #endif /* __DTS_IMX6SLL_PINFUNC_H */ 881
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