1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright 2014 - 2015 Freescale Semiconduct 4 */ 5 6 #ifndef __DTS_IMX6UL_PINFUNC_H 7 #define __DTS_IMX6UL_PINFUNC_H 8 9 /* 10 * The pin function ID is a tuple of 11 * <mux_reg conf_reg input_reg mux_mode input_ 12 */ 13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 15 16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 24 #define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 25 #define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 26 27 #define MX6UL_PAD_JTAG_MOD__SJC_MOD 28 #define MX6UL_PAD_JTAG_MOD__GPT2_CLK 29 #define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 30 #define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 31 #define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 32 #define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 33 #define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 34 #define MX6UL_PAD_JTAG_TMS__SJC_TMS 35 #define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 36 #define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 37 #define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 38 #define MX6UL_PAD_JTAG_TMS__CCM_WAIT 39 #define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 40 #define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 41 #define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 42 #define MX6UL_PAD_JTAG_TDO__SJC_TDO 43 #define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 44 #define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 45 #define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 46 #define MX6UL_PAD_JTAG_TDO__CCM_STOP 47 #define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 48 #define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 49 #define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 50 #define MX6UL_PAD_JTAG_TDI__SJC_TDI 51 #define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 52 #define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 53 #define MX6UL_PAD_JTAG_TDI__PWM6_OUT 54 #define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 55 #define MX6UL_PAD_JTAG_TDI__MQS_LEFT 56 #define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 57 #define MX6UL_PAD_JTAG_TCK__SJC_TCK 58 #define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 59 #define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 60 #define MX6UL_PAD_JTAG_TCK__PWM7_OUT 61 #define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 62 #define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 63 #define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 64 #define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 65 #define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 66 #define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 67 #define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 68 #define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 69 #define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 70 #define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OB 71 #define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 72 #define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 73 #define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 74 #define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 75 #define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 76 #define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 77 #define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT 78 #define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 79 #define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 80 #define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 81 #define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 82 #define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 83 #define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 84 #define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 85 #define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 86 #define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT 87 #define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 88 #define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 89 #define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 90 #define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 91 #define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 92 #define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25 93 #define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 94 #define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 95 #define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 96 #define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 97 #define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 98 #define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 99 #define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 100 #define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 101 #define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 102 #define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 103 #define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 104 #define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 105 #define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 106 #define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 107 #define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 108 #define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 109 #define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 110 #define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 111 #define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 112 #define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 113 #define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 114 #define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 115 #define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT 116 #define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 117 #define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 118 #define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 119 #define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 120 #define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 121 #define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 122 #define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 123 #define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 124 #define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT 125 #define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 126 #define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 127 #define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 128 #define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 129 #define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 130 #define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 131 #define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 132 #define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 133 #define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 134 #define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 135 #define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 136 #define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 137 #define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 138 #define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 139 #define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MOD 140 #define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 141 #define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 142 #define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 143 #define MX6UL_PAD_GPIO1_IO07__CCM_STOP 144 #define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 145 #define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 146 #define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 147 #define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 148 #define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 149 #define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 150 #define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 151 #define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 152 #define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 153 #define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 154 #define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 155 #define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 156 #define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 157 #define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 158 #define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 159 #define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 160 #define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 161 #define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 162 #define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 163 #define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 164 #define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 165 #define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 166 #define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 167 #define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 168 #define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 169 #define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 170 #define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 171 #define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 172 #define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 173 #define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 174 #define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 175 #define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 176 #define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 177 #define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 178 #define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 179 #define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 180 #define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 181 #define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 182 #define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 183 #define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 184 #define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 185 #define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVEN 186 #define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 187 #define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 188 #define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 189 #define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 190 #define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 191 #define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 192 #define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 193 #define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVEN 194 #define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 195 #define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 196 #define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 197 #define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 198 #define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 199 #define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 200 #define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 201 #define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 202 #define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 203 #define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 204 #define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 205 #define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 206 #define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 207 #define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 208 #define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 209 #define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 210 #define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 211 #define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 212 #define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 213 #define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 214 #define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 215 #define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 216 #define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 217 #define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 218 #define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 219 #define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 220 #define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 221 #define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 222 #define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 223 #define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 224 #define MX6UL_PAD_UART2_RTS_B__ENET1_COL 225 #define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 226 #define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 227 #define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 228 #define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 229 #define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 230 #define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 231 #define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 232 #define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 233 #define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 234 #define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 235 #define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 236 #define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 237 #define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 238 #define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 239 #define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 240 #define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_I 241 #define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 242 #define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 243 #define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 244 #define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 245 #define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 246 #define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 247 #define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 248 #define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 249 #define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 250 #define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 251 #define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 252 #define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 253 #define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 254 #define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 255 #define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVEN 256 #define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 257 #define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 258 #define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 259 #define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 260 #define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 261 #define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 262 #define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 263 #define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVEN 264 #define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 265 #define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 266 #define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 267 #define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 268 #define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 269 #define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 270 #define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 271 #define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM 272 #define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 273 #define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 274 #define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 275 #define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 276 #define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 277 #define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 278 #define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 279 #define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM 280 #define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 281 #define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 282 #define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 283 #define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 284 #define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 285 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 286 #define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 287 #define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 288 #define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 289 #define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM 290 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 291 #define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 292 #define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 293 #define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 294 #define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 295 #define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_D 296 #define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 297 #define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 298 #define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA0 299 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RT 300 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CT 301 #define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 302 #define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 303 #define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 304 #define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 305 #define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 306 #define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 307 #define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA0 308 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CT 309 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RT 310 #define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 311 #define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 312 #define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 313 #define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 314 #define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 315 #define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 316 #define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 317 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 318 #define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 319 #define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 320 #define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 321 #define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 322 #define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 323 #define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 324 #define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 325 #define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA0 326 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CT 327 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RT 328 #define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 329 #define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 330 #define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 331 #define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 332 #define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 333 #define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELE 334 #define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA0 335 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CT 336 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RT 337 #define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 338 #define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 339 #define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 340 #define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 341 #define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 342 #define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_R 343 #define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 344 #define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 345 #define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 346 #define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 347 #define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 348 #define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 349 #define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 350 #define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 351 #define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_ 352 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 353 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 354 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 355 #define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 356 #define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 357 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 358 #define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 359 #define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 360 #define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 361 #define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 362 #define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 363 #define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 364 #define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 365 #define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 366 #define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 367 #define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 368 #define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 369 #define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 370 #define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA0 371 #define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 372 #define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 373 #define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_T 374 #define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 375 #define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 376 #define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 377 #define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 378 #define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 379 #define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA0 380 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 381 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 382 #define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_C 383 #define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 384 #define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 385 #define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 386 #define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 387 #define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 388 #define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 389 #define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 390 #define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 391 #define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_ 392 #define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 393 #define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 394 #define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 395 #define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 396 #define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_2 397 #define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA0 398 #define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 399 #define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 400 #define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_S 401 #define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 402 #define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 403 #define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 404 #define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 405 #define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 406 #define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA0 407 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 408 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 409 #define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_T 410 #define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 411 #define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 412 #define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 413 #define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 414 #define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 415 #define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 416 #define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 417 #define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 418 #define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 419 #define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 420 #define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERU 421 #define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 422 #define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 423 #define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 424 #define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 425 #define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 426 #define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 427 #define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST 428 #define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 429 #define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 430 #define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 431 #define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 432 #define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 433 #define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 434 #define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 435 #define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 436 #define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 437 #define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 438 #define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 439 #define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 440 #define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 441 #define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 442 #define MX6UL_PAD_LCD_CLK__LCDIF_CLK 443 #define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 444 #define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 445 #define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 446 #define MX6UL_PAD_LCD_CLK__SAI3_MCLK 447 #define MX6UL_PAD_LCD_CLK__EIM_CS2_B 448 #define MX6UL_PAD_LCD_CLK__GPIO3_IO00 449 #define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DE 450 #define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 451 #define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 452 #define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 453 #define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 454 #define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 455 #define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 456 #define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 457 #define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 458 #define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 459 #define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 460 #define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 461 #define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 462 #define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 463 #define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_ 464 #define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 465 #define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 466 #define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 467 #define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 468 #define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 469 #define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 470 #define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 471 #define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 472 #define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 473 #define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 474 #define MX6UL_PAD_LCD_RESET__LCDIF_RESET 475 #define MX6UL_PAD_LCD_RESET__LCDIF_CS 476 #define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 477 #define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 478 #define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 479 #define MX6UL_PAD_LCD_RESET__GPIO3_IO04 480 #define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 481 #define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 482 #define MX6UL_PAD_LCD_DATA00__PWM1_OUT 483 #define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 484 #define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT 485 #define MX6UL_PAD_LCD_DATA00__I2C3_SDA 486 #define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 487 #define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 488 #define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 489 #define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 490 #define MX6UL_PAD_LCD_DATA01__PWM2_OUT 491 #define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 492 #define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT 493 #define MX6UL_PAD_LCD_DATA01__I2C3_SCL 494 #define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 495 #define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 496 #define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 497 #define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 498 #define MX6UL_PAD_LCD_DATA02__PWM3_OUT 499 #define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 500 #define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT 501 #define MX6UL_PAD_LCD_DATA02__I2C4_SDA 502 #define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 503 #define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 504 #define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 505 #define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 506 #define MX6UL_PAD_LCD_DATA03__PWM4_OUT 507 #define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 508 #define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT 509 #define MX6UL_PAD_LCD_DATA03__I2C4_SCL 510 #define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 511 #define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 512 #define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 513 #define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 514 #define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 515 #define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 516 #define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 517 #define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT 518 #define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 519 #define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 520 #define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 521 #define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 522 #define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 523 #define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 524 #define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 525 #define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 526 #define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT 527 #define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 528 #define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 529 #define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 530 #define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 531 #define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 532 #define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 533 #define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 534 #define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 535 #define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT 536 #define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 537 #define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 538 #define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 539 #define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 540 #define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 541 #define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 542 #define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 543 #define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 544 #define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT 545 #define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 546 #define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 547 #define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 548 #define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 549 #define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 550 #define MX6UL_PAD_LCD_DATA08__SPDIF_IN 551 #define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 552 #define MX6UL_PAD_LCD_DATA08__CSI_DATA16 553 #define MX6UL_PAD_LCD_DATA08__EIM_DATA00 554 #define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 555 #define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 556 #define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 557 #define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 558 #define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 559 #define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 560 #define MX6UL_PAD_LCD_DATA09__CSI_DATA17 561 #define MX6UL_PAD_LCD_DATA09__EIM_DATA01 562 #define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 563 #define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 564 #define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 565 #define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 566 #define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 567 #define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE1 568 #define MX6UL_PAD_LCD_DATA10__CSI_DATA18 569 #define MX6UL_PAD_LCD_DATA10__EIM_DATA02 570 #define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 571 #define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 572 #define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 573 #define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 574 #define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 575 #define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE1 576 #define MX6UL_PAD_LCD_DATA11__CSI_DATA19 577 #define MX6UL_PAD_LCD_DATA11__EIM_DATA03 578 #define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 579 #define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 580 #define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 581 #define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 582 #define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 583 #define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE1 584 #define MX6UL_PAD_LCD_DATA12__CSI_DATA20 585 #define MX6UL_PAD_LCD_DATA12__EIM_DATA04 586 #define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 587 #define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 588 #define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 589 #define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 590 #define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 591 #define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE1 592 #define MX6UL_PAD_LCD_DATA13__CSI_DATA21 593 #define MX6UL_PAD_LCD_DATA13__EIM_DATA05 594 #define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 595 #define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 596 #define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 597 #define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 598 #define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 599 #define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE1 600 #define MX6UL_PAD_LCD_DATA14__CSI_DATA22 601 #define MX6UL_PAD_LCD_DATA14__EIM_DATA06 602 #define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 603 #define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 604 #define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 605 #define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 606 #define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 607 #define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE1 608 #define MX6UL_PAD_LCD_DATA15__CSI_DATA23 609 #define MX6UL_PAD_LCD_DATA15__EIM_DATA07 610 #define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 611 #define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 612 #define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 613 #define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 614 #define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 615 #define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 616 #define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_ 617 #define MX6UL_PAD_LCD_DATA16__CSI_DATA01 618 #define MX6UL_PAD_LCD_DATA16__EIM_DATA08 619 #define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 620 #define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 621 #define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 622 #define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 623 #define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 624 #define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 625 #define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_ 626 #define MX6UL_PAD_LCD_DATA17__CSI_DATA00 627 #define MX6UL_PAD_LCD_DATA17__EIM_DATA09 628 #define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 629 #define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 630 #define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 631 #define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 632 #define MX6UL_PAD_LCD_DATA18__PWM5_OUT 633 #define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 634 #define MX6UL_PAD_LCD_DATA18__CSI_DATA10 635 #define MX6UL_PAD_LCD_DATA18__EIM_DATA10 636 #define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 637 #define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 638 #define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 639 #define MX6UL_PAD_LCD_DATA19__EIM_DATA11 640 #define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 641 #define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 642 #define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 643 #define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 644 #define MX6UL_PAD_LCD_DATA19__PWM6_OUT 645 #define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 646 #define MX6UL_PAD_LCD_DATA19__CSI_DATA11 647 #define MX6UL_PAD_LCD_DATA20__EIM_DATA12 648 #define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 649 #define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 650 #define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 651 #define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 652 #define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 653 #define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 654 #define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 655 #define MX6UL_PAD_LCD_DATA20__CSI_DATA12 656 #define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 657 #define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 658 #define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 659 #define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 660 #define MX6UL_PAD_LCD_DATA21__CSI_DATA13 661 #define MX6UL_PAD_LCD_DATA21__EIM_DATA13 662 #define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 663 #define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 664 #define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 665 #define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 666 #define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 667 #define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 668 #define MX6UL_PAD_LCD_DATA22__CSI_DATA14 669 #define MX6UL_PAD_LCD_DATA22__EIM_DATA14 670 #define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 671 #define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 672 #define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 673 #define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 674 #define MX6UL_PAD_LCD_DATA23__MQS_LEFT 675 #define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 676 #define MX6UL_PAD_LCD_DATA23__CSI_DATA15 677 #define MX6UL_PAD_LCD_DATA23__EIM_DATA15 678 #define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 679 #define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 680 #define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 681 #define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 682 #define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 683 #define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 684 #define MX6UL_PAD_NAND_RE_B__KPP_ROW00 685 #define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 686 #define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 687 #define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 688 #define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 689 #define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 690 #define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 691 #define MX6UL_PAD_NAND_WE_B__KPP_COL00 692 #define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 693 #define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 694 #define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 695 #define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 696 #define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 697 #define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 698 #define MX6UL_PAD_NAND_DATA00__KPP_ROW01 699 #define MX6UL_PAD_NAND_DATA00__EIM_AD08 700 #define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 701 #define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 702 #define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 703 #define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 704 #define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 705 #define MX6UL_PAD_NAND_DATA01__KPP_COL01 706 #define MX6UL_PAD_NAND_DATA01__EIM_AD09 707 #define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 708 #define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 709 #define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 710 #define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 711 #define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 712 #define MX6UL_PAD_NAND_DATA02__KPP_ROW02 713 #define MX6UL_PAD_NAND_DATA02__EIM_AD10 714 #define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 715 #define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 716 #define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 717 #define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 718 #define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 719 #define MX6UL_PAD_NAND_DATA03__KPP_COL02 720 #define MX6UL_PAD_NAND_DATA03__EIM_AD11 721 #define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 722 #define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 723 #define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 724 #define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 725 #define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 726 #define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 727 #define MX6UL_PAD_NAND_DATA04__EIM_AD12 728 #define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 729 #define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 730 #define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 731 #define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 732 #define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 733 #define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 734 #define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 735 #define MX6UL_PAD_NAND_DATA05__EIM_AD13 736 #define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 737 #define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 738 #define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 739 #define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 740 #define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 741 #define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 742 #define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 743 #define MX6UL_PAD_NAND_DATA06__EIM_AD14 744 #define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 745 #define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 746 #define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 747 #define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 748 #define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 749 #define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 750 #define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 751 #define MX6UL_PAD_NAND_DATA07__EIM_AD15 752 #define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 753 #define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 754 #define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 755 #define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 756 #define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 757 #define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 758 #define MX6UL_PAD_NAND_ALE__PWM3_OUT 759 #define MX6UL_PAD_NAND_ALE__EIM_ADDR17 760 #define MX6UL_PAD_NAND_ALE__GPIO4_IO10 761 #define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 762 #define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 763 #define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 764 #define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 765 #define MX6UL_PAD_NAND_WP_B__PWM4_OUT 766 #define MX6UL_PAD_NAND_WP_B__EIM_BCLK 767 #define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 768 #define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 769 #define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_ 770 #define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 771 #define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 772 #define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 773 #define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 774 #define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 775 #define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 776 #define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 777 #define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 778 #define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 779 #define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 780 #define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 781 #define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 782 #define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 783 #define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 784 #define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 785 #define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 786 #define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 787 #define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 788 #define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 789 #define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 790 #define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 791 #define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 792 #define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 793 #define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 794 #define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 795 #define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 796 #define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 797 #define MX6UL_PAD_NAND_CLE__EIM_ADDR16 798 #define MX6UL_PAD_NAND_CLE__GPIO4_IO15 799 #define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 800 #define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 801 #define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 802 #define MX6UL_PAD_NAND_DQS__CSI_FIELD 803 #define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 804 #define MX6UL_PAD_NAND_DQS__PWM5_OUT 805 #define MX6UL_PAD_NAND_DQS__EIM_WAIT 806 #define MX6UL_PAD_NAND_DQS__GPIO4_IO16 807 #define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 808 #define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 809 #define MX6UL_PAD_SD1_CMD__USDHC1_CMD 810 #define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 811 #define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 812 #define MX6UL_PAD_SD1_CMD__SPDIF_OUT 813 #define MX6UL_PAD_SD1_CMD__EIM_ADDR19 814 #define MX6UL_PAD_SD1_CMD__GPIO2_IO16 815 #define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 816 #define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 817 #define MX6UL_PAD_SD1_CLK__USDHC1_CLK 818 #define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 819 #define MX6UL_PAD_SD1_CLK__SAI2_MCLK 820 #define MX6UL_PAD_SD1_CLK__SPDIF_IN 821 #define MX6UL_PAD_SD1_CLK__EIM_ADDR20 822 #define MX6UL_PAD_SD1_CLK__GPIO2_IO17 823 #define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 824 #define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 825 #define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 826 #define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 827 #define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 828 #define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 829 #define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 830 #define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 831 #define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 832 #define MX6UL_PAD_SD1_DATA1__GPT2_CLK 833 #define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 834 #define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 835 #define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 836 #define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 837 #define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 838 #define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 839 #define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 840 #define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 841 #define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 842 #define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 843 #define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 844 #define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 845 #define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 846 #define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 847 #define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 848 #define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 849 #define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 850 #define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 851 #define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 852 #define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 853 #define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 854 #define MX6UL_PAD_CSI_MCLK__CSI_MCLK 855 #define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 856 #define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 857 #define MX6UL_PAD_CSI_MCLK__I2C1_SDA 858 #define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 859 #define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 860 #define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 861 #define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 862 #define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 863 #define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 864 #define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 865 #define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 866 #define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 867 #define MX6UL_PAD_CSI_PIXCLK__EIM_OE 868 #define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 869 #define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 870 #define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 871 #define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 872 #define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 873 #define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 874 #define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 875 #define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 876 #define MX6UL_PAD_CSI_VSYNC__EIM_RW 877 #define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 878 #define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 879 #define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 880 #define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 881 #define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 882 #define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 883 #define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 884 #define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 885 #define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 886 #define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 887 #define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 888 #define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 889 #define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 890 #define MX6UL_PAD_CSI_DATA00__CSI_DATA02 891 #define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 892 #define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 893 #define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 894 #define MX6UL_PAD_CSI_DATA00__EIM_AD00 895 #define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 896 #define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 897 #define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 898 #define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 899 #define MX6UL_PAD_CSI_DATA01__CSI_DATA03 900 #define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 901 #define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 902 #define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 903 #define MX6UL_PAD_CSI_DATA01__EIM_AD01 904 #define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 905 #define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 906 #define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 907 #define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 908 #define MX6UL_PAD_CSI_DATA02__CSI_DATA04 909 #define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 910 #define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 911 #define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 912 #define MX6UL_PAD_CSI_DATA02__EIM_AD02 913 #define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 914 #define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 915 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 916 #define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 917 #define MX6UL_PAD_CSI_DATA03__CSI_DATA05 918 #define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 919 #define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 920 #define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 921 #define MX6UL_PAD_CSI_DATA03__EIM_AD03 922 #define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 923 #define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 924 #define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 925 #define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 926 #define MX6UL_PAD_CSI_DATA04__CSI_DATA06 927 #define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 928 #define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 929 #define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 930 #define MX6UL_PAD_CSI_DATA04__EIM_AD04 931 #define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 932 #define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 933 #define MX6UL_PAD_CSI_DATA04__USDHC1_WP 934 #define MX6UL_PAD_CSI_DATA05__CSI_DATA07 935 #define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 936 #define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 937 #define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 938 #define MX6UL_PAD_CSI_DATA05__EIM_AD05 939 #define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 940 #define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 941 #define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 942 #define MX6UL_PAD_CSI_DATA06__CSI_DATA08 943 #define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 944 #define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 945 #define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 946 #define MX6UL_PAD_CSI_DATA06__EIM_AD06 947 #define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 948 #define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 949 #define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 950 #define MX6UL_PAD_CSI_DATA07__CSI_DATA09 951 #define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 952 #define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 953 #define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 954 #define MX6UL_PAD_CSI_DATA07__EIM_AD07 955 #define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 956 #define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 957 #define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 958 959 #endif /* __DTS_IMX6UL_PINFUNC_H */ 960
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