1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2012 Freescale Semiconductor, Inc
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include "imx28-pinfunc.h"
7
8 / {
9 #address-cells = <1>;
10 #size-cells = <1>;
11
12 interrupt-parent = <&icoll>;
13 /*
14 * The decompressor and also some boot
15 * pre-existing /chosen node to be ava
16 * command line and merge other ATAGS
17 */
18 chosen {};
19
20 aliases {
21 ethernet0 = &mac0;
22 ethernet1 = &mac1;
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 gpio2 = &gpio2;
26 gpio3 = &gpio3;
27 gpio4 = &gpio4;
28 saif0 = &saif0;
29 saif1 = &saif1;
30 serial0 = &auart0;
31 serial1 = &auart1;
32 serial2 = &auart2;
33 serial3 = &auart3;
34 serial4 = &auart4;
35 spi0 = &ssp1;
36 spi1 = &ssp2;
37 usbphy0 = &usbphy0;
38 usbphy1 = &usbphy1;
39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 cpu@0 {
46 compatible = "arm,arm9
47 device_type = "cpu";
48 reg = <0>;
49 };
50 };
51
52 apb@80000000 {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 reg = <0x80000000 0x80000>;
57 ranges;
58
59 apbh-bus@80000000 {
60 compatible = "simple-b
61 #address-cells = <1>;
62 #size-cells = <1>;
63 reg = <0x80000000 0x3c
64 ranges;
65
66 icoll: interrupt-contr
67 compatible = "
68 interrupt-cont
69 #interrupt-cel
70 reg = <0x80000
71 };
72
73 hsadc: hsadc@80002000
74 reg = <0x80002
75 interrupts = <
76 dmas = <&dma_a
77 dma-names = "r
78 status = "disa
79 };
80
81 dma_apbh: dma-controll
82 compatible = "
83 reg = <0x80004
84 interrupts = <
85 <
86 <
87 <
88 #dma-cells = <
89 dma-channels =
90 clocks = <&clk
91 };
92
93 perfmon: perfmon@80006
94 reg = <0x80006
95 interrupts = <
96 status = "disa
97 };
98
99 gpmi: nand-controller@
100 compatible = "
101 #address-cells
102 #size-cells =
103 reg = <0x8000c
104 reg-names = "g
105 interrupts = <
106 interrupt-name
107 clocks = <&clk
108 clock-names =
109 assigned-clock
110 assigned-clock
111 dmas = <&dma_a
112 dma-names = "r
113 status = "disa
114 };
115
116 ssp0: spi@80010000 {
117 #address-cells
118 #size-cells =
119 reg = <0x80010
120 interrupts = <
121 clocks = <&clk
122 dmas = <&dma_a
123 dma-names = "r
124 status = "disa
125 };
126
127 ssp1: spi@80012000 {
128 #address-cells
129 #size-cells =
130 reg = <0x80012
131 interrupts = <
132 clocks = <&clk
133 dmas = <&dma_a
134 dma-names = "r
135 status = "disa
136 };
137
138 ssp2: spi@80014000 {
139 #address-cells
140 #size-cells =
141 reg = <0x80014
142 interrupts = <
143 clocks = <&clk
144 dmas = <&dma_a
145 dma-names = "r
146 status = "disa
147 };
148
149 ssp3: spi@80016000 {
150 #address-cells
151 #size-cells =
152 reg = <0x80016
153 interrupts = <
154 clocks = <&clk
155 dmas = <&dma_a
156 dma-names = "r
157 status = "disa
158 };
159
160 pinctrl: pinctrl@80018
161 #address-cells
162 #size-cells =
163 compatible = "
164 reg = <0x80018
165
166 gpio0: gpio@0
167 compat
168 reg =
169 interr
170 gpio-c
171 #gpio-
172 interr
173 #inter
174 };
175
176 gpio1: gpio@1
177 compat
178 reg =
179 interr
180 gpio-c
181 #gpio-
182 interr
183 #inter
184 };
185
186 gpio2: gpio@2
187 compat
188 reg =
189 interr
190 gpio-c
191 #gpio-
192 interr
193 #inter
194 };
195
196 gpio3: gpio@3
197 compat
198 reg =
199 interr
200 gpio-c
201 #gpio-
202 interr
203 #inter
204 };
205
206 gpio4: gpio@4
207 compat
208 reg =
209 interr
210 gpio-c
211 #gpio-
212 interr
213 #inter
214 };
215
216 duart_pins_a:
217 reg =
218 fsl,pi
219
220
221 >;
222 fsl,dr
223 fsl,vo
224 fsl,pu
225 };
226
227 duart_pins_b:
228 reg =
229 fsl,pi
230
231
232 >;
233 fsl,dr
234 fsl,vo
235 fsl,pu
236 };
237
238 duart_4pins_a:
239 reg =
240 fsl,pi
241
242
243
244
245 >;
246 fsl,dr
247 fsl,vo
248 fsl,pu
249 };
250
251 gpmi_pins_a: g
252 reg =
253 fsl,pi
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269 >;
270 fsl,dr
271 fsl,vo
272 fsl,pu
273 };
274
275 gpmi_status_cf
276 reg =
277 fsl,pi
278
279
280
281 >;
282 fsl,dr
283 };
284
285 auart0_pins_a:
286 reg =
287 fsl,pi
288
289
290
291
292 >;
293 fsl,dr
294 fsl,vo
295 fsl,pu
296 };
297
298 auart0_2pins_a
299 reg =
300 fsl,pi
301
302
303 >;
304 fsl,dr
305 fsl,vo
306 fsl,pu
307 };
308
309 auart1_pins_a:
310 reg =
311 fsl,pi
312
313
314
315
316 >;
317 fsl,dr
318 fsl,vo
319 fsl,pu
320 };
321
322 auart1_2pins_a
323 reg =
324 fsl,pi
325
326
327 >;
328 fsl,dr
329 fsl,vo
330 fsl,pu
331 };
332
333 auart2_2pins_a
334 reg =
335 fsl,pi
336
337
338 >;
339 fsl,dr
340 fsl,vo
341 fsl,pu
342 };
343
344 auart2_2pins_b
345 reg =
346 fsl,pi
347
348
349 >;
350 fsl,dr
351 fsl,vo
352 fsl,pu
353 };
354
355 auart2_pins_a:
356 reg =
357 fsl,pi
358
359
360
361
362 >;
363 fsl,dr
364 fsl,vo
365 fsl,pu
366 };
367
368 auart3_pins_a:
369 reg =
370 fsl,pi
371
372
373
374
375 >;
376 fsl,dr
377 fsl,vo
378 fsl,pu
379 };
380
381 auart3_2pins_a
382 reg =
383 fsl,pi
384
385
386 >;
387 fsl,dr
388 fsl,vo
389 fsl,pu
390 };
391
392 auart3_2pins_b
393 reg =
394 fsl,pi
395
396
397 >;
398 fsl,dr
399 fsl,vo
400 fsl,pu
401 };
402
403 auart4_2pins_a
404 reg =
405 fsl,pi
406
407
408 >;
409 fsl,dr
410 fsl,vo
411 fsl,pu
412 };
413
414 auart4_2pins_b
415 reg =
416 fsl,pi
417
418
419 >;
420 fsl,dr
421 fsl,vo
422 fsl,pu
423 };
424
425 mac0_pins_a: m
426 reg =
427 fsl,pi
428
429
430
431
432
433
434
435
436
437 >;
438 fsl,dr
439 fsl,vo
440 fsl,pu
441 };
442
443 mac0_pins_b: m
444 reg =
445 fsl,pi
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464 fsl,dr
465 fsl,vo
466 fsl,pu
467 };
468
469 mac1_pins_a: m
470 reg =
471 fsl,pi
472
473
474
475
476
477
478 >;
479 fsl,dr
480 fsl,vo
481 fsl,pu
482 };
483
484 mmc0_8bit_pins
485 reg =
486 fsl,pi
487
488
489
490
491
492
493
494
495
496
497
498 >;
499 fsl,dr
500 fsl,vo
501 fsl,pu
502 };
503
504 mmc0_4bit_pins
505 reg =
506 fsl,pi
507
508
509
510
511
512
513
514 >;
515 fsl,dr
516 fsl,vo
517 fsl,pu
518 };
519
520 mmc0_cd_cfg: m
521 reg =
522 fsl,pi
523
524 >;
525 fsl,pu
526 };
527
528 mmc0_sck_cfg:
529 reg =
530 fsl,pi
531
532 >;
533 fsl,dr
534 fsl,pu
535 };
536
537 mmc1_4bit_pins
538 reg =
539 fsl,pi
540
541
542
543
544
545
546
547 >;
548 fsl,dr
549 fsl,vo
550 fsl,pu
551 };
552
553 mmc1_cd_cfg: m
554 reg =
555 fsl,pi
556
557 >;
558 fsl,pu
559 };
560
561 mmc1_sck_cfg:
562 reg =
563 fsl,pi
564
565 >;
566 fsl,dr
567 fsl,pu
568 };
569
570
571 mmc2_4bit_pins
572 reg =
573 fsl,pi
574
575
576
577
578
579
580
581 >;
582 fsl,dr
583 fsl,vo
584 fsl,pu
585 };
586
587 mmc2_4bit_pins
588 reg =
589 fsl,pi
590
591
592
593
594
595
596
597 >;
598 fsl,dr
599 fsl,vo
600 fsl,pu
601 };
602
603 mmc2_cd_cfg: m
604 reg =
605 fsl,pi
606
607 >;
608 fsl,pu
609 };
610
611 mmc2_sck_cfg_a
612 reg =
613 fsl,pi
614
615 >;
616 fsl,dr
617 fsl,pu
618 };
619
620 mmc2_sck_cfg_b
621 reg =
622 fsl,pi
623
624 >;
625 fsl,dr
626 fsl,pu
627 };
628
629 i2c0_pins_a: i
630 reg =
631 fsl,pi
632
633
634 >;
635 fsl,dr
636 fsl,vo
637 fsl,pu
638 };
639
640 i2c0_pins_b: i
641 reg =
642 fsl,pi
643
644
645 >;
646 fsl,dr
647 fsl,vo
648 fsl,pu
649 };
650
651 i2c1_pins_a: i
652 reg =
653 fsl,pi
654
655
656 >;
657 fsl,dr
658 fsl,vo
659 fsl,pu
660 };
661
662 i2c1_pins_b: i
663 reg =
664 fsl,pi
665
666
667 >;
668 fsl,dr
669 fsl,vo
670 fsl,pu
671 };
672
673 saif0_pins_a:
674 reg =
675 fsl,pi
676
677
678
679
680 >;
681 fsl,dr
682 fsl,vo
683 fsl,pu
684 };
685
686 saif0_pins_b:
687 reg =
688 fsl,pi
689
690
691
692 >;
693 fsl,dr
694 fsl,vo
695 fsl,pu
696 };
697
698 saif1_pins_a:
699 reg =
700 fsl,pi
701
702 >;
703 fsl,dr
704 fsl,vo
705 fsl,pu
706 };
707
708 pwm0_pins_a: p
709 reg =
710 fsl,pi
711
712 >;
713 fsl,dr
714 fsl,vo
715 fsl,pu
716 };
717
718 pwm2_pins_a: p
719 reg =
720 fsl,pi
721
722 >;
723 fsl,dr
724 fsl,vo
725 fsl,pu
726 };
727
728 pwm3_pins_a: p
729 reg =
730 fsl,pi
731
732 >;
733 fsl,dr
734 fsl,vo
735 fsl,pu
736 };
737
738 pwm3_pins_b: p
739 reg =
740 fsl,pi
741
742 >;
743 fsl,dr
744 fsl,vo
745 fsl,pu
746 };
747
748 pwm4_pins_a: p
749 reg =
750 fsl,pi
751
752 >;
753 fsl,dr
754 fsl,vo
755 fsl,pu
756 };
757
758 lcdif_24bit_pi
759 reg =
760 fsl,pi
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785 >;
786 fsl,dr
787 fsl,vo
788 fsl,pu
789 };
790
791 lcdif_18bit_pi
792 reg =
793 fsl,pi
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812 >;
813 fsl,dr
814 fsl,vo
815 fsl,pu
816 };
817
818 lcdif_16bit_pi
819 reg =
820 fsl,pi
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837 >;
838 fsl,dr
839 fsl,vo
840 fsl,pu
841 };
842
843 lcdif_sync_pin
844 reg =
845 fsl,pi
846
847
848
849
850 >;
851 fsl,dr
852 fsl,vo
853 fsl,pu
854 };
855
856 can0_pins_a: c
857 reg =
858 fsl,pi
859
860
861 >;
862 fsl,dr
863 fsl,vo
864 fsl,pu
865 };
866
867 can1_pins_a: c
868 reg =
869 fsl,pi
870
871
872 >;
873 fsl,dr
874 fsl,vo
875 fsl,pu
876 };
877
878 spi2_pins_a: s
879 reg =
880 fsl,pi
881
882
883
884
885 >;
886 fsl,dr
887 fsl,vo
888 fsl,pu
889 };
890
891 spi3_pins_a: s
892 reg =
893 fsl,pi
894
895
896
897
898
899
900 >;
901 fsl,dr
902 fsl,vo
903 fsl,pu
904 };
905
906 spi3_pins_b: s
907 reg =
908 fsl,pi
909
910
911
912
913 >;
914 fsl,dr
915 fsl,vo
916 fsl,pu
917 };
918
919 usb0_pins_a: u
920 reg =
921 fsl,pi
922
923 >;
924 fsl,dr
925 fsl,vo
926 fsl,pu
927 };
928
929 usb0_pins_b: u
930 reg =
931 fsl,pi
932
933 >;
934 fsl,dr
935 fsl,vo
936 fsl,pu
937 };
938
939 usb1_pins_a: u
940 reg =
941 fsl,pi
942
943 >;
944 fsl,dr
945 fsl,vo
946 fsl,pu
947 };
948
949 usb1_pins_b: u
950 reg =
951 fsl,pi
952
953 >;
954 fsl,dr
955 fsl,vo
956 fsl,pu
957 };
958
959 usb0_id_pins_a
960 reg =
961 fsl,pi
962
963 >;
964 fsl,dr
965 fsl,vo
966 fsl,pu
967 };
968
969 usb0_id_pins_b
970 reg =
971 fsl,pi
972
973 >;
974 fsl,dr
975 fsl,vo
976 fsl,pu
977 };
978
979 };
980
981 digctl: digctl@8001c00
982 compatible = "
983 reg = <0x8001c
984 interrupts = <
985 status = "disa
986 };
987
988 etm: etm@80022000 {
989 reg = <0x80022
990 status = "disa
991 };
992
993 dma_apbx: dma-controll
994 compatible = "
995 reg = <0x80024
996 interrupts = <
997 <
998 <
999 <
1000 #dma-cells =
1001 dma-channels
1002 clocks = <&cl
1003 };
1004
1005 dcp: crypto@80028000
1006 compatible =
1007 reg = <0x8002
1008 interrupts =
1009 status = "oka
1010 };
1011
1012 pxp: pxp@8002a000 {
1013 reg = <0x8002
1014 interrupts =
1015 status = "dis
1016 };
1017
1018 ocotp: efuse@8002c000
1019 compatible =
1020 #address-cell
1021 #size-cells =
1022 reg = <0x8002
1023 clocks = <&cl
1024 };
1025
1026 axi-ahb@8002e000 {
1027 reg = <0x8002
1028 status = "dis
1029 };
1030
1031 lcdif: lcdif@80030000
1032 compatible =
1033 reg = <0x8003
1034 interrupts =
1035 clocks = <&cl
1036 dmas = <&dma_
1037 dma-names = "
1038 status = "dis
1039 };
1040
1041 can0: can@80032000 {
1042 compatible =
1043 reg = <0x8003
1044 interrupts =
1045 clocks = <&cl
1046 clock-names =
1047 status = "dis
1048 };
1049
1050 can1: can@80034000 {
1051 compatible =
1052 reg = <0x8003
1053 interrupts =
1054 clocks = <&cl
1055 clock-names =
1056 status = "dis
1057 };
1058
1059 simdbg: simdbg@8003c0
1060 reg = <0x8003
1061 status = "dis
1062 };
1063
1064 simgpmisel: simgpmise
1065 reg = <0x8003
1066 status = "dis
1067 };
1068
1069 simsspsel: simsspsel@
1070 reg = <0x8003
1071 status = "dis
1072 };
1073
1074 simmemsel: simmemsel@
1075 reg = <0x8003
1076 status = "dis
1077 };
1078
1079 gpiomon: gpiomon@8003
1080 reg = <0x8003
1081 status = "dis
1082 };
1083
1084 simenet: simenet@8003
1085 reg = <0x8003
1086 status = "dis
1087 };
1088
1089 armjtag: armjtag@8003
1090 reg = <0x8003
1091 status = "dis
1092 };
1093 };
1094
1095 apbx-bus@80040000 {
1096 compatible = "simple-
1097 #address-cells = <1>;
1098 #size-cells = <1>;
1099 reg = <0x80040000 0x4
1100 ranges;
1101
1102 clks: clkctrl@8004000
1103 compatible =
1104 reg = <0x8004
1105 #clock-cells
1106 };
1107
1108 saif0: saif@80042000
1109 #sound-dai-ce
1110 compatible =
1111 reg = <0x8004
1112 interrupts =
1113 #clock-cells
1114 clocks = <&cl
1115 dmas = <&dma_
1116 dma-names = "
1117 status = "dis
1118 };
1119
1120 power: power@80044000
1121 reg = <0x8004
1122 status = "dis
1123 };
1124
1125 saif1: saif@80046000
1126 #sound-dai-ce
1127 compatible =
1128 reg = <0x8004
1129 interrupts =
1130 clocks = <&cl
1131 dmas = <&dma_
1132 dma-names = "
1133 status = "dis
1134 };
1135
1136 lradc: lradc@80050000
1137 compatible =
1138 reg = <0x8005
1139 interrupts =
1140
1141 status = "dis
1142 clocks = <&cl
1143 #io-channel-c
1144 };
1145
1146 spdif: spdif@80054000
1147 reg = <0x8005
1148 interrupts =
1149 dmas = <&dma_
1150 dma-names = "
1151 status = "dis
1152 };
1153
1154 mxs_rtc: rtc@80056000
1155 compatible =
1156 reg = <0x8005
1157 interrupts =
1158 };
1159
1160 i2c0: i2c@80058000 {
1161 #address-cell
1162 #size-cells =
1163 compatible =
1164 reg = <0x8005
1165 interrupts =
1166 clock-frequen
1167 dmas = <&dma_
1168 dma-names = "
1169 status = "dis
1170 };
1171
1172 i2c1: i2c@8005a000 {
1173 #address-cell
1174 #size-cells =
1175 compatible =
1176 reg = <0x8005
1177 interrupts =
1178 clock-frequen
1179 dmas = <&dma_
1180 dma-names = "
1181 status = "dis
1182 };
1183
1184 pwm: pwm@80064000 {
1185 compatible =
1186 reg = <0x8006
1187 clocks = <&cl
1188 #pwm-cells =
1189 fsl,pwm-numbe
1190 status = "dis
1191 };
1192
1193 timer: timrot@8006800
1194 compatible =
1195 reg = <0x8006
1196 interrupts =
1197 clocks = <&cl
1198 };
1199
1200 auart0: serial@8006a0
1201 compatible =
1202 reg = <0x8006
1203 interrupts =
1204 dmas = <&dma_
1205 dma-names = "
1206 clocks = <&cl
1207 status = "dis
1208 };
1209
1210 auart1: serial@8006c0
1211 compatible =
1212 reg = <0x8006
1213 interrupts =
1214 dmas = <&dma_
1215 dma-names = "
1216 clocks = <&cl
1217 status = "dis
1218 };
1219
1220 auart2: serial@8006e0
1221 compatible =
1222 reg = <0x8006
1223 interrupts =
1224 dmas = <&dma_
1225 dma-names = "
1226 clocks = <&cl
1227 status = "dis
1228 };
1229
1230 auart3: serial@800700
1231 compatible =
1232 reg = <0x8007
1233 interrupts =
1234 dmas = <&dma_
1235 dma-names = "
1236 clocks = <&cl
1237 status = "dis
1238 };
1239
1240 auart4: serial@800720
1241 compatible =
1242 reg = <0x8007
1243 interrupts =
1244 dmas = <&dma_
1245 dma-names = "
1246 clocks = <&cl
1247 status = "dis
1248 };
1249
1250 duart: serial@8007400
1251 compatible =
1252 reg = <0x8007
1253 interrupts =
1254 clocks = <&cl
1255 clock-names =
1256 status = "dis
1257 };
1258
1259 usbphy0: usbphy@8007c
1260 compatible =
1261 reg = <0x8007
1262 clocks = <&cl
1263 status = "dis
1264 };
1265
1266 usbphy1: usbphy@8007e
1267 compatible =
1268 reg = <0x8007
1269 clocks = <&cl
1270 status = "dis
1271 };
1272 };
1273 };
1274
1275 ahb@80080000 {
1276 compatible = "simple-bus";
1277 #address-cells = <1>;
1278 #size-cells = <1>;
1279 reg = <0x80080000 0x80000>;
1280 ranges;
1281
1282 usb0: usb@80080000 {
1283 compatible = "fsl,imx
1284 reg = <0x80080000 0x1
1285 interrupts = <93>;
1286 clocks = <&clks 60>;
1287 fsl,usbphy = <&usbphy
1288 status = "disabled";
1289 };
1290
1291 usb1: usb@80090000 {
1292 compatible = "fsl,imx
1293 reg = <0x80090000 0x1
1294 interrupts = <92>;
1295 clocks = <&clks 61>;
1296 fsl,usbphy = <&usbphy
1297 dr_mode = "host";
1298 status = "disabled";
1299 };
1300
1301 dflpt: dflpt@800c0000 {
1302 reg = <0x800c0000 0x1
1303 status = "disabled";
1304 };
1305
1306 mac0: ethernet@800f0000 {
1307 compatible = "fsl,imx
1308 reg = <0x800f0000 0x4
1309 interrupts = <101>;
1310 clocks = <&clks 57>,
1311 clock-names = "ipg",
1312 status = "disabled";
1313 };
1314
1315 mac1: ethernet@800f4000 {
1316 compatible = "fsl,imx
1317 reg = <0x800f4000 0x4
1318 interrupts = <102>;
1319 clocks = <&clks 57>,
1320 clock-names = "ipg",
1321 status = "disabled";
1322 };
1323
1324 eth_switch: switch@800f8000 {
1325 reg = <0x800f8000 0x8
1326 status = "disabled";
1327 };
1328 };
1329
1330 iio-hwmon {
1331 compatible = "iio-hwmon";
1332 io-channels = <&lradc 8>;
1333 };
1334 };
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