1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 */
6
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
11 #include "rk3xxx.dtsi"
12
13 / {
14 compatible = "rockchip,rk3188";
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk30
20
21 cpu0: cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cort
24 next-level-cache = <&L
25 reg = <0x0>;
26 clock-latency = <40000
27 clocks = <&cru ARMCLK>
28 operating-points-v2 =
29 resets = <&cru SRST_CO
30 };
31 cpu1: cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cort
34 next-level-cache = <&L
35 reg = <0x1>;
36 operating-points-v2 =
37 resets = <&cru SRST_CO
38 };
39 cpu2: cpu@2 {
40 device_type = "cpu";
41 compatible = "arm,cort
42 next-level-cache = <&L
43 reg = <0x2>;
44 operating-points-v2 =
45 resets = <&cru SRST_CO
46 };
47 cpu3: cpu@3 {
48 device_type = "cpu";
49 compatible = "arm,cort
50 next-level-cache = <&L
51 reg = <0x3>;
52 operating-points-v2 =
53 resets = <&cru SRST_CO
54 };
55 };
56
57 cpu0_opp_table: opp-table-0 {
58 compatible = "operating-points
59 opp-shared;
60
61 opp-312000000 {
62 opp-hz = /bits/ 64 <31
63 opp-microvolt = <87500
64 clock-latency-ns = <40
65 };
66 opp-504000000 {
67 opp-hz = /bits/ 64 <50
68 opp-microvolt = <92500
69 };
70 opp-600000000 {
71 opp-hz = /bits/ 64 <60
72 opp-microvolt = <95000
73 opp-suspend;
74 };
75 opp-816000000 {
76 opp-hz = /bits/ 64 <81
77 opp-microvolt = <97500
78 };
79 opp-1008000000 {
80 opp-hz = /bits/ 64 <10
81 opp-microvolt = <10750
82 };
83 opp-1200000000 {
84 opp-hz = /bits/ 64 <12
85 opp-microvolt = <11500
86 };
87 opp-1416000000 {
88 opp-hz = /bits/ 64 <14
89 opp-microvolt = <12500
90 };
91 opp-1608000000 {
92 opp-hz = /bits/ 64 <16
93 opp-microvolt = <13500
94 };
95 };
96
97 display-subsystem {
98 compatible = "rockchip,display
99 ports = <&vop0_out>, <&vop1_ou
100 };
101
102 sram: sram@10080000 {
103 compatible = "mmio-sram";
104 reg = <0x10080000 0x8000>;
105 #address-cells = <1>;
106 #size-cells = <1>;
107 ranges = <0 0x10080000 0x8000>
108
109 smp-sram@0 {
110 compatible = "rockchip
111 reg = <0x0 0x50>;
112 };
113 };
114
115 vop0: vop@1010c000 {
116 compatible = "rockchip,rk3188-
117 reg = <0x1010c000 0x1000>;
118 interrupts = <GIC_SPI 13 IRQ_T
119 clocks = <&cru ACLK_LCDC0>, <&
120 clock-names = "aclk_vop", "dcl
121 power-domains = <&power RK3188
122 resets = <&cru SRST_LCDC0_AXI>
123 reset-names = "axi", "ahb", "d
124 status = "disabled";
125
126 vop0_out: port {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 };
130 };
131
132 vop1: vop@1010e000 {
133 compatible = "rockchip,rk3188-
134 reg = <0x1010e000 0x1000>;
135 interrupts = <GIC_SPI 14 IRQ_T
136 clocks = <&cru ACLK_LCDC1>, <&
137 clock-names = "aclk_vop", "dcl
138 power-domains = <&power RK3188
139 resets = <&cru SRST_LCDC1_AXI>
140 reset-names = "axi", "ahb", "d
141 status = "disabled";
142
143 vop1_out: port {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 };
147 };
148
149 timer3: timer@2000e000 {
150 compatible = "rockchip,rk3188-
151 reg = <0x2000e000 0x20>;
152 interrupts = <GIC_SPI 46 IRQ_T
153 clocks = <&cru PCLK_TIMER3>, <
154 clock-names = "pclk", "timer";
155 };
156
157 timer6: timer@200380a0 {
158 compatible = "rockchip,rk3188-
159 reg = <0x200380a0 0x20>;
160 interrupts = <GIC_SPI 64 IRQ_T
161 clocks = <&cru PCLK_TIMER0>, <
162 clock-names = "pclk", "timer";
163 };
164
165 i2s0: i2s@1011a000 {
166 compatible = "rockchip,rk3188-
167 reg = <0x1011a000 0x2000>;
168 interrupts = <GIC_SPI 32 IRQ_T
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2s0_bus>;
171 clocks = <&cru SCLK_I2S0>, <&c
172 clock-names = "i2s_clk", "i2s_
173 dmas = <&dmac1_s 6>, <&dmac1_s
174 dma-names = "tx", "rx";
175 rockchip,playback-channels = <
176 rockchip,capture-channels = <2
177 #sound-dai-cells = <0>;
178 status = "disabled";
179 };
180
181 spdif: sound@1011e000 {
182 compatible = "rockchip,rk3188-
183 reg = <0x1011e000 0x2000>;
184 #sound-dai-cells = <0>;
185 clocks = <&cru SCLK_SPDIF>, <&
186 clock-names = "mclk", "hclk";
187 dmas = <&dmac1_s 8>;
188 dma-names = "tx";
189 interrupts = <GIC_SPI 32 IRQ_T
190 pinctrl-names = "default";
191 pinctrl-0 = <&spdif_tx>;
192 status = "disabled";
193 };
194
195 cru: clock-controller@20000000 {
196 compatible = "rockchip,rk3188-
197 reg = <0x20000000 0x1000>;
198 clocks = <&xin24m>;
199 clock-names = "xin24m";
200 rockchip,grf = <&grf>;
201 #clock-cells = <1>;
202 #reset-cells = <1>;
203 };
204
205 efuse: efuse@20010000 {
206 compatible = "rockchip,rk3188-
207 reg = <0x20010000 0x4000>;
208 #address-cells = <1>;
209 #size-cells = <1>;
210 clocks = <&cru PCLK_EFUSE>;
211 clock-names = "pclk_efuse";
212
213 cpu_leakage: cpu_leakage@17 {
214 reg = <0x17 0x1>;
215 };
216 };
217
218 pinctrl: pinctrl {
219 compatible = "rockchip,rk3188-
220 rockchip,grf = <&grf>;
221 rockchip,pmu = <&pmu>;
222
223 #address-cells = <1>;
224 #size-cells = <1>;
225 ranges;
226
227 gpio0: gpio@2000a000 {
228 compatible = "rockchip
229 reg = <0x2000a000 0x10
230 interrupts = <GIC_SPI
231 clocks = <&cru PCLK_GP
232
233 gpio-controller;
234 #gpio-cells = <2>;
235
236 interrupt-controller;
237 #interrupt-cells = <2>
238 };
239
240 gpio1: gpio@2003c000 {
241 compatible = "rockchip
242 reg = <0x2003c000 0x10
243 interrupts = <GIC_SPI
244 clocks = <&cru PCLK_GP
245
246 gpio-controller;
247 #gpio-cells = <2>;
248
249 interrupt-controller;
250 #interrupt-cells = <2>
251 };
252
253 gpio2: gpio@2003e000 {
254 compatible = "rockchip
255 reg = <0x2003e000 0x10
256 interrupts = <GIC_SPI
257 clocks = <&cru PCLK_GP
258
259 gpio-controller;
260 #gpio-cells = <2>;
261
262 interrupt-controller;
263 #interrupt-cells = <2>
264 };
265
266 gpio3: gpio@20080000 {
267 compatible = "rockchip
268 reg = <0x20080000 0x10
269 interrupts = <GIC_SPI
270 clocks = <&cru PCLK_GP
271
272 gpio-controller;
273 #gpio-cells = <2>;
274
275 interrupt-controller;
276 #interrupt-cells = <2>
277 };
278
279 pcfg_pull_up: pcfg-pull-up {
280 bias-pull-up;
281 };
282
283 pcfg_pull_down: pcfg-pull-down
284 bias-pull-down;
285 };
286
287 pcfg_pull_none: pcfg-pull-none
288 bias-disable;
289 };
290
291 emmc {
292 emmc_clk: emmc-clk {
293 rockchip,pins
294 };
295
296 emmc_cmd: emmc-cmd {
297 rockchip,pins
298 };
299
300 emmc_rst: emmc-rst {
301 rockchip,pins
302 };
303
304 /*
305 * The data pins are s
306 * not accessible thro
307 * been already set co
308 * flash/emmc is the b
309 */
310 };
311
312 emac {
313 emac_xfer: emac-xfer {
314 rockchip,pins
315
316
317
318
319
320
321
322 };
323
324 emac_mdio: emac-mdio {
325 rockchip,pins
326
327 };
328 };
329
330 i2c0 {
331 i2c0_xfer: i2c0-xfer {
332 rockchip,pins
333
334 };
335 };
336
337 i2c1 {
338 i2c1_xfer: i2c1-xfer {
339 rockchip,pins
340
341 };
342 };
343
344 i2c2 {
345 i2c2_xfer: i2c2-xfer {
346 rockchip,pins
347
348 };
349 };
350
351 i2c3 {
352 i2c3_xfer: i2c3-xfer {
353 rockchip,pins
354
355 };
356 };
357
358 i2c4 {
359 i2c4_xfer: i2c4-xfer {
360 rockchip,pins
361
362 };
363 };
364
365 lcdc1 {
366 lcdc1_dclk: lcdc1-dclk
367 rockchip,pins
368 };
369
370 lcdc1_den: lcdc1-den {
371 rockchip,pins
372 };
373
374 lcdc1_hsync: lcdc1-hsy
375 rockchip,pins
376 };
377
378 lcdc1_vsync: lcdc1-vsy
379 rockchip,pins
380 };
381
382 lcdc1_rgb24: lcdc1-rgb
383 rockchip,pins
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407 };
408 };
409
410 pwm0 {
411 pwm0_out: pwm0-out {
412 rockchip,pins
413 };
414 };
415
416 pwm1 {
417 pwm1_out: pwm1-out {
418 rockchip,pins
419 };
420 };
421
422 pwm2 {
423 pwm2_out: pwm2-out {
424 rockchip,pins
425 };
426 };
427
428 pwm3 {
429 pwm3_out: pwm3-out {
430 rockchip,pins
431 };
432 };
433
434 spi0 {
435 spi0_clk: spi0-clk {
436 rockchip,pins
437 };
438 spi0_cs0: spi0-cs0 {
439 rockchip,pins
440 };
441 spi0_tx: spi0-tx {
442 rockchip,pins
443 };
444 spi0_rx: spi0-rx {
445 rockchip,pins
446 };
447 spi0_cs1: spi0-cs1 {
448 rockchip,pins
449 };
450 };
451
452 spi1 {
453 spi1_clk: spi1-clk {
454 rockchip,pins
455 };
456 spi1_cs0: spi1-cs0 {
457 rockchip,pins
458 };
459 spi1_rx: spi1-rx {
460 rockchip,pins
461 };
462 spi1_tx: spi1-tx {
463 rockchip,pins
464 };
465 spi1_cs1: spi1-cs1 {
466 rockchip,pins
467 };
468 };
469
470 uart0 {
471 uart0_xfer: uart0-xfer
472 rockchip,pins
473
474 };
475
476 uart0_cts: uart0-cts {
477 rockchip,pins
478 };
479
480 uart0_rts: uart0-rts {
481 rockchip,pins
482 };
483 };
484
485 uart1 {
486 uart1_xfer: uart1-xfer
487 rockchip,pins
488
489 };
490
491 uart1_cts: uart1-cts {
492 rockchip,pins
493 };
494
495 uart1_rts: uart1-rts {
496 rockchip,pins
497 };
498 };
499
500 uart2 {
501 uart2_xfer: uart2-xfer
502 rockchip,pins
503
504 };
505 /* no rts / cts for ua
506 };
507
508 uart3 {
509 uart3_xfer: uart3-xfer
510 rockchip,pins
511
512 };
513
514 uart3_cts: uart3-cts {
515 rockchip,pins
516 };
517
518 uart3_rts: uart3-rts {
519 rockchip,pins
520 };
521 };
522
523 sd0 {
524 sd0_clk: sd0-clk {
525 rockchip,pins
526 };
527
528 sd0_cmd: sd0-cmd {
529 rockchip,pins
530 };
531
532 sd0_cd: sd0-cd {
533 rockchip,pins
534 };
535
536 sd0_wp: sd0-wp {
537 rockchip,pins
538 };
539
540 sd0_pwr: sd0-pwr {
541 rockchip,pins
542 };
543
544 sd0_bus1: sd0-bus-widt
545 rockchip,pins
546 };
547
548 sd0_bus4: sd0-bus-widt
549 rockchip,pins
550
551
552
553 };
554 };
555
556 sd1 {
557 sd1_clk: sd1-clk {
558 rockchip,pins
559 };
560
561 sd1_cmd: sd1-cmd {
562 rockchip,pins
563 };
564
565 sd1_cd: sd1-cd {
566 rockchip,pins
567 };
568
569 sd1_wp: sd1-wp {
570 rockchip,pins
571 };
572
573 sd1_bus1: sd1-bus-widt
574 rockchip,pins
575 };
576
577 sd1_bus4: sd1-bus-widt
578 rockchip,pins
579
580
581
582 };
583 };
584
585 i2s0 {
586 i2s0_bus: i2s0-bus {
587 rockchip,pins
588
589
590
591
592
593 };
594 };
595
596 spdif {
597 spdif_tx: spdif-tx {
598 rockchip,pins
599 };
600 };
601 };
602 };
603
604 &emac {
605 compatible = "rockchip,rk3188-emac";
606 };
607
608 &global_timer {
609 interrupts = <GIC_PPI 11 (GIC_CPU_MASK
610 };
611
612 &local_timer {
613 interrupts = <GIC_PPI 13 (GIC_CPU_MASK
614 };
615
616 &gpu {
617 compatible = "rockchip,rk3188-mali", "
618 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVE
619 <GIC_SPI 8 IRQ_TYPE_LEVEL
620 <GIC_SPI 7 IRQ_TYPE_LEVEL
621 <GIC_SPI 8 IRQ_TYPE_LEVEL
622 <GIC_SPI 7 IRQ_TYPE_LEVEL
623 <GIC_SPI 8 IRQ_TYPE_LEVEL
624 <GIC_SPI 7 IRQ_TYPE_LEVEL
625 <GIC_SPI 8 IRQ_TYPE_LEVEL
626 <GIC_SPI 7 IRQ_TYPE_LEVEL
627 <GIC_SPI 8 IRQ_TYPE_LEVEL
628 interrupt-names = "gp",
629 "gpmmu",
630 "pp0",
631 "ppmmu0",
632 "pp1",
633 "ppmmu1",
634 "pp2",
635 "ppmmu2",
636 "pp3",
637 "ppmmu3";
638 power-domains = <&power RK3188_PD_GPU>
639 };
640
641 &grf {
642 compatible = "rockchip,rk3188-grf", "s
643
644 io_domains: io-domains {
645 compatible = "rockchip,rk3188-
646 status = "disabled";
647 };
648
649 usbphy: usbphy {
650 compatible = "rockchip,rk3188-
651 #address-cells = <1>;
652 #size-cells = <0>;
653 status = "disabled";
654
655 usbphy0: usb-phy@10c {
656 reg = <0x10c>;
657 clocks = <&cru SCLK_OT
658 clock-names = "phyclk"
659 #clock-cells = <0>;
660 #phy-cells = <0>;
661 };
662
663 usbphy1: usb-phy@11c {
664 reg = <0x11c>;
665 clocks = <&cru SCLK_OT
666 clock-names = "phyclk"
667 #clock-cells = <0>;
668 #phy-cells = <0>;
669 };
670 };
671 };
672
673 &i2c0 {
674 compatible = "rockchip,rk3188-i2c";
675 pinctrl-names = "default";
676 pinctrl-0 = <&i2c0_xfer>;
677 };
678
679 &i2c1 {
680 compatible = "rockchip,rk3188-i2c";
681 pinctrl-names = "default";
682 pinctrl-0 = <&i2c1_xfer>;
683 };
684
685 &i2c2 {
686 compatible = "rockchip,rk3188-i2c";
687 pinctrl-names = "default";
688 pinctrl-0 = <&i2c2_xfer>;
689 };
690
691 &i2c3 {
692 compatible = "rockchip,rk3188-i2c";
693 pinctrl-names = "default";
694 pinctrl-0 = <&i2c3_xfer>;
695 };
696
697 &i2c4 {
698 compatible = "rockchip,rk3188-i2c";
699 pinctrl-names = "default";
700 pinctrl-0 = <&i2c4_xfer>;
701 };
702
703 &pmu {
704 power: power-controller {
705 compatible = "rockchip,rk3188-
706 #power-domain-cells = <1>;
707 #address-cells = <1>;
708 #size-cells = <0>;
709
710 power-domain@RK3188_PD_VIO {
711 reg = <RK3188_PD_VIO>;
712 clocks = <&cru ACLK_LC
713 <&cru ACLK_LC
714 <&cru DCLK_LC
715 <&cru DCLK_LC
716 <&cru HCLK_LC
717 <&cru HCLK_LC
718 <&cru SCLK_CI
719 <&cru ACLK_CI
720 <&cru HCLK_CI
721 <&cru ACLK_IP
722 <&cru HCLK_IP
723 <&cru ACLK_RG
724 <&cru HCLK_RG
725 pm_qos = <&qos_lcdc0>,
726 <&qos_lcdc1>,
727 <&qos_cif0>,
728 <&qos_ipp>,
729 <&qos_rga>;
730 #power-domain-cells =
731 };
732
733 power-domain@RK3188_PD_VIDEO {
734 reg = <RK3188_PD_VIDEO
735 clocks = <&cru ACLK_VD
736 <&cru ACLK_VE
737 <&cru HCLK_VD
738 <&cru HCLK_VE
739 pm_qos = <&qos_vpu>;
740 #power-domain-cells =
741 };
742
743 power-domain@RK3188_PD_GPU {
744 reg = <RK3188_PD_GPU>;
745 clocks = <&cru ACLK_GP
746 pm_qos = <&qos_gpu>;
747 #power-domain-cells =
748 };
749 };
750 };
751
752 &pwm0 {
753 pinctrl-names = "default";
754 pinctrl-0 = <&pwm0_out>;
755 };
756
757 &pwm1 {
758 pinctrl-names = "default";
759 pinctrl-0 = <&pwm1_out>;
760 };
761
762 &pwm2 {
763 pinctrl-names = "default";
764 pinctrl-0 = <&pwm2_out>;
765 };
766
767 &pwm3 {
768 pinctrl-names = "default";
769 pinctrl-0 = <&pwm3_out>;
770 };
771
772 &spi0 {
773 compatible = "rockchip,rk3188-spi", "r
774 pinctrl-names = "default";
775 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_
776 };
777
778 &spi1 {
779 compatible = "rockchip,rk3188-spi", "r
780 pinctrl-names = "default";
781 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_
782 };
783
784 &uart0 {
785 compatible = "rockchip,rk3188-uart", "
786 pinctrl-names = "default";
787 pinctrl-0 = <&uart0_xfer>;
788 };
789
790 &uart1 {
791 compatible = "rockchip,rk3188-uart", "
792 pinctrl-names = "default";
793 pinctrl-0 = <&uart1_xfer>;
794 };
795
796 &uart2 {
797 compatible = "rockchip,rk3188-uart", "
798 pinctrl-names = "default";
799 pinctrl-0 = <&uart2_xfer>;
800 };
801
802 &uart3 {
803 compatible = "rockchip,rk3188-uart", "
804 pinctrl-names = "default";
805 pinctrl-0 = <&uart3_xfer>;
806 };
807
808 &vpu {
809 compatible = "rockchip,rk3188-vpu", "r
810 power-domains = <&power RK3188_PD_VIDE
811 };
812
813 &wdt {
814 compatible = "rockchip,rk3188-wdt", "s
815 };
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