1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co.
4 * Copyright (c) 2022 Edgeble AI Technologies
5 */
6
7 / {
8 aliases {
9 ethernet0 = &gmac;
10 mmc0 = &emmc;
11 mmc1 = &sdio;
12 mmc2 = &sdmmc;
13 };
14
15 chosen {
16 stdout-path = "serial2:1500000
17 };
18
19 vcc5v0_sys: regulator-vcc5v0-sys {
20 compatible = "regulator-fixed"
21 regulator-name = "vcc5v0_sys";
22 regulator-always-on;
23 regulator-boot-on;
24 regulator-min-microvolt = <500
25 regulator-max-microvolt = <500
26 };
27
28 sdio_pwrseq: pwrseq-sdio {
29 compatible = "mmc-pwrseq-simpl
30 clocks = <&rk809 1>;
31 clock-names = "ext_clock";
32 pinctrl-names = "default";
33 pinctrl-0 = <&wifi_enable_h>;
34 reset-gpios = <&gpio1 RK_PD0 G
35 };
36 };
37
38 &emmc {
39 bus-width = <8>;
40 cap-mmc-highspeed;
41 mmc-hs200-1_8v;
42 non-removable;
43 pinctrl-names = "default";
44 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emm
45 rockchip,default-sample-phase = <90>;
46 vmmc-supply = <&vcc_3v3>;
47 vqmmc-supply = <&vcc_1v8>;
48 status = "okay";
49 };
50
51 &i2c0 {
52 clock-frequency = <400000>;
53 status = "okay";
54
55 rk809: pmic@20 {
56 compatible = "rockchip,rk809";
57 reg = <0x20>;
58 interrupt-parent = <&gpio0>;
59 interrupts = <RK_PB1 IRQ_TYPE_
60 #clock-cells = <1>;
61 clock-output-names = "rk808-cl
62 pinctrl-names = "default";
63 pinctrl-0 = <&pmic_int_l>;
64 rockchip,system-power-controll
65 wakeup-source;
66
67 vcc1-supply = <&vcc5v0_sys>;
68 vcc2-supply = <&vcc5v0_sys>;
69 vcc3-supply = <&vcc5v0_sys>;
70 vcc4-supply = <&vcc5v0_sys>;
71 vcc5-supply = <&vcc_buck5>;
72 vcc6-supply = <&vcc_buck5>;
73 vcc7-supply = <&vcc5v0_sys>;
74 vcc8-supply = <&vcc3v3_sys>;
75 vcc9-supply = <&vcc5v0_sys>;
76
77 regulators {
78 vdd_npu_vepu: DCDC_REG
79 regulator-name
80 regulator-alwa
81 regulator-boot
82 regulator-init
83 regulator-min-
84 regulator-max-
85 regulator-ramp
86 regulator-stat
87 regula
88 };
89 };
90
91 vdd_arm: DCDC_REG2 {
92 regulator-name
93 regulator-alwa
94 regulator-boot
95 regulator-init
96 regulator-min-
97 regulator-max-
98 regulator-ramp
99 regulator-stat
100 regula
101 };
102 };
103
104 vcc_ddr: DCDC_REG3 {
105 regulator-name
106 regulator-alwa
107 regulator-boot
108 regulator-init
109 regulator-stat
110 regula
111 };
112 };
113
114 vcc3v3_sys: DCDC_REG4
115 regulator-name
116 regulator-alwa
117 regulator-boot
118 regulator-init
119 regulator-min-
120 regulator-max-
121 regulator-stat
122 regula
123 regula
124 };
125 };
126
127 vcc_buck5: DCDC_REG5 {
128 regulator-name
129 regulator-alwa
130 regulator-boot
131 regulator-min-
132 regulator-max-
133 regulator-stat
134 regula
135 regula
136 };
137 };
138
139 vcc_0v8: LDO_REG1 {
140 regulator-name
141 regulator-alwa
142 regulator-boot
143 regulator-min-
144 regulator-max-
145 regulator-stat
146 regula
147 };
148 };
149
150 vcc1v8_pmu: LDO_REG2 {
151 regulator-name
152 regulator-alwa
153 regulator-boot
154 regulator-min-
155 regulator-max-
156 regulator-stat
157 regula
158 regula
159 };
160 };
161
162 vdd0v8_pmu: LDO_REG3 {
163 regulator-name
164 regulator-alwa
165 regulator-boot
166 regulator-min-
167 regulator-max-
168 regulator-stat
169 regula
170 regula
171 };
172 };
173
174 vcc_1v8: LDO_REG4 {
175 regulator-name
176 regulator-alwa
177 regulator-boot
178 regulator-min-
179 regulator-max-
180 regulator-stat
181 regula
182 regula
183 };
184 };
185
186 vcc_dovdd: LDO_REG5 {
187 regulator-name
188 regulator-alwa
189 regulator-boot
190 regulator-min-
191 regulator-max-
192 regulator-stat
193 regula
194 };
195 };
196
197 vcc_dvdd: LDO_REG6 {
198 regulator-name
199 regulator-min-
200 regulator-max-
201 regulator-stat
202 regula
203 };
204 };
205
206 vcc_avdd: LDO_REG7 {
207 regulator-name
208 regulator-min-
209 regulator-max-
210 regulator-stat
211 regula
212 };
213 };
214
215 vccio_sd: LDO_REG8 {
216 regulator-name
217 regulator-alwa
218 regulator-boot
219 regulator-min-
220 regulator-max-
221 regulator-stat
222 regula
223 };
224 };
225
226 vcc3v3_sd: LDO_REG9 {
227 regulator-name
228 regulator-alwa
229 regulator-boot
230 regulator-min-
231 regulator-max-
232 regulator-stat
233 regula
234 };
235 };
236
237 vcc_5v0: SWITCH_REG1 {
238 regulator-name
239 };
240
241 vcc_3v3: SWITCH_REG2 {
242 regulator-name
243 regulator-alwa
244 regulator-boot
245 };
246 };
247 };
248 };
249
250 &i2c2 {
251 status = "okay";
252 clock-frequency = <400000>;
253
254 pcf8563: rtc@51 {
255 compatible = "nxp,pcf8563";
256 reg = <0x51>;
257 #clock-cells = <0>;
258 interrupt-parent = <&gpio0>;
259 interrupts = <RK_PA2 IRQ_TYPE_
260 clock-output-names = "xin32k";
261 };
262 };
263
264 &gmac {
265 assigned-clocks = <&cru CLK_GMAC_SRC_M
266 <&cru CLK_GMAC_TX_RX
267 assigned-clock-parents = <&cru CLK_GMA
268 <&cru RMII_MO
269 assigned-clock-rates = <0>, <50000000>
270 clock_in_out = "output";
271 phy-handle = <&phy>;
272 phy-mode = "rmii";
273 phy-supply = <&vcc_3v3>;
274 pinctrl-names = "default";
275 pinctrl-0 = <&rgmiim1_miim &rgmiim1_rx
276 status = "okay";
277 };
278
279 &mdio {
280 phy: ethernet-phy@0 {
281 compatible = "ethernet-phy-iee
282 reg = <0x0>;
283 pinctrl-names = "default";
284 pinctrl-0 = <ð_phy_rst>;
285 reset-active-low;
286 reset-assert-us = <50000>;
287 reset-deassert-us = <10000>;
288 reset-gpios = <&gpio2 RK_PA6 G
289 };
290 };
291
292 &pinctrl {
293 ethernet {
294 eth_phy_rst: eth-phy-rst {
295 rockchip,pins = <2 RK_
296 };
297 };
298 bt {
299 bt_enable: bt-enable {
300 rockchip,pins = <1 RK_
301 };
302
303 bt_wake_dev: bt-wake-dev {
304 rockchip,pins = <1 RK_
305 };
306
307 bt_wake_host: bt-wake-host {
308 rockchip,pins = <1 RK_
309 };
310 };
311
312 pmic {
313 pmic_int_l: pmic-int-l {
314 rockchip,pins = <0 RK_
315 };
316 };
317
318 wifi {
319 wifi_enable_h: wifi-enable-h {
320 rockchip,pins = <1 RK_
321 };
322 };
323 };
324
325 &pmu_io_domains {
326 pmuio0-supply = <&vcc1v8_pmu>;
327 pmuio1-supply = <&vcc3v3_sys>;
328 vccio1-supply = <&vcc_1v8>;
329 vccio2-supply = <&vccio_sd>;
330 vccio3-supply = <&vcc3v3_sd>;
331 vccio4-supply = <&vcc_dovdd>;
332 vccio5-supply = <&vcc_1v8>;
333 vccio6-supply = <&vcc_1v8>;
334 vccio7-supply = <&vcc_dovdd>;
335 status = "okay";
336 };
337
338 &saradc {
339 vref-supply = <&vcc_1v8>;
340 status = "okay";
341 };
342
343 &sdio {
344 bus-width = <4>;
345 cap-sd-highspeed;
346 cap-sdio-irq;
347 keep-power-in-suspend;
348 max-frequency = <50000000>;
349 mmc-pwrseq = <&sdio_pwrseq>;
350 non-removable;
351 pinctrl-names = "default";
352 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &
353 rockchip,default-sample-phase = <90>;
354 sd-uhs-sdr50;
355 vmmc-supply = <&vcc3v3_sd>;
356 vqmmc-supply = <&vcc_1v8>;
357 status = "okay";
358 };
359
360 &sdmmc {
361 bus-width = <4>;
362 cap-mmc-highspeed;
363 cap-sd-highspeed;
364 card-detect-delay = <200>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &
367 rockchip,default-sample-phase = <90>;
368 sd-uhs-sdr12;
369 sd-uhs-sdr25;
370 sd-uhs-sdr104;
371 vqmmc-supply = <&vccio_sd>;
372 status = "okay";
373 };
374
375 &uart0 {
376 pinctrl-names = "default";
377 pinctrl-0 = <&uart0_xfer &uart0_ctsn &
378 uart-has-rtscts;
379 status = "okay";
380
381 bluetooth {
382 compatible = "realtek,rtl8723d
383 device-wake-gpios = <&gpio1 RK
384 enable-gpios = <&gpio1 RK_PC6
385 host-wake-gpios = <&gpio1 RK_P
386 max-speed = <2000000>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&bt_enable>, <&bt
389 };
390 };
391
392 &uart2 {
393 status = "okay";
394 };
395
396 &uart3 {
397 pinctrl-names = "default";
398 pinctrl-0 = <&uart3m2_xfer>;
399 status = "okay";
400 };
401
402 &uart4 {
403 pinctrl-names = "default";
404 pinctrl-0 = <&uart4m2_xfer>;
405 status = "okay";
406 };
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