1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos5250 based Arndale board de
4 *
5 * Copyright (c) 2013 Samsung Electronics Co.,
6 * http://www.samsung.com
7 */
8
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
15 #include "exynos5250.dtsi"
16
17 / {
18 model = "Insignal Arndale evaluation b
19 compatible = "insignal,arndale", "sams
20
21 memory@40000000 {
22 device_type = "memory";
23 reg = <0x40000000 0x80000000>;
24 };
25
26 aliases {
27 mmc0 = &mmc_0;
28 mmc1 = &mmc_2;
29 };
30
31 chosen {
32 stdout-path = "serial2:115200n
33 };
34
35 gpio-keys {
36 compatible = "gpio-keys";
37
38 key-menu {
39 label = "SW-TACT2";
40 gpios = <&gpx1 4 GPIO_
41 linux,code = <KEY_MENU
42 wakeup-source;
43 };
44
45 key-home {
46 label = "SW-TACT3";
47 gpios = <&gpx1 5 GPIO_
48 linux,code = <KEY_HOME
49 wakeup-source;
50 };
51
52 key-up {
53 label = "SW-TACT4";
54 gpios = <&gpx1 6 GPIO_
55 linux,code = <KEY_UP>;
56 wakeup-source;
57 };
58
59 key-down {
60 label = "SW-TACT5";
61 gpios = <&gpx1 7 GPIO_
62 linux,code = <KEY_DOWN
63 wakeup-source;
64 };
65
66 key-back {
67 label = "SW-TACT6";
68 gpios = <&gpx2 0 GPIO_
69 linux,code = <KEY_BACK
70 wakeup-source;
71 };
72
73 key-wakeup {
74 label = "SW-TACT7";
75 gpios = <&gpx2 1 GPIO_
76 linux,code = <KEY_WAKE
77 wakeup-source;
78 };
79 };
80
81 /*
82 * For unknown reasons HDMI-DDC does n
83 * controllers. Lets use software I2C
84 */
85 i2c_ddc: i2c-10 {
86 compatible = "i2c-gpio";
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2c2_gpio_bus>;
89 sda-gpios = <&gpa0 6 (GPIO_ACT
90 scl-gpios = <&gpa0 7 (GPIO_ACT
91 i2c-gpio,delay-us = <2>;
92 };
93
94 panel: panel {
95 compatible = "boe,hv070wsa-100
96 power-supply = <&vcc_3v3_reg>;
97 enable-gpios = <&gpd1 3 GPIO_A
98 port {
99 panel_ep: endpoint {
100 remote-endpoin
101 };
102 };
103 };
104
105 main_dc_reg: regulator-0 {
106 compatible = "regulator-fixed"
107 regulator-name = "MAIN_DC";
108 regulator-always-on;
109 };
110
111 mmc_reg: regulator-1 {
112 compatible = "regulator-fixed"
113 regulator-name = "VDD_MMC";
114 regulator-min-microvolt = <280
115 regulator-max-microvolt = <280
116 regulator-always-on;
117 };
118
119 reg_hdmi_en: regulator-2 {
120 compatible = "regulator-fixed"
121 regulator-name = "hdmi-en";
122 regulator-always-on;
123 };
124
125 vcc_1v2_reg: regulator-3 {
126 compatible = "regulator-fixed"
127 regulator-name = "VCC_1V2";
128 regulator-min-microvolt = <120
129 regulator-max-microvolt = <120
130 regulator-always-on;
131 };
132
133 vcc_1v8_reg: regulator-4 {
134 compatible = "regulator-fixed"
135 regulator-name = "VCC_1V8";
136 regulator-min-microvolt = <180
137 regulator-max-microvolt = <180
138 regulator-always-on;
139 };
140
141 vcc_3v3_reg: regulator-5 {
142 compatible = "regulator-fixed"
143 regulator-name = "VCC_3V3";
144 regulator-min-microvolt = <330
145 regulator-max-microvolt = <330
146 regulator-always-on;
147 };
148
149 sound {
150 compatible = "samsung,arndale-
151 samsung,audio-cpu = <&i2s0>;
152 samsung,audio-codec = <&wm1811
153 };
154
155 fixed-rate-clocks {
156 xxti {
157 compatible = "samsung,
158 clock-frequency = <240
159 };
160 };
161
162 // SMSC USB3503 connected in hardware
163 usb_hub: usb-hub {
164 compatible = "smsc,usb3503a";
165
166 reset-gpios = <&gpx3 5 GPIO_AC
167 connect-gpios = <&gpd1 7 GPIO_
168 };
169 };
170
171 &clock {
172 assigned-clocks = <&clock CLK_FOUT_EPL
173 assigned-clock-rates = <49152000>;
174 };
175
176 &clock_audss {
177 assigned-clocks = <&clock_audss EXYNOS
178 assigned-clock-parents = <&clock CLK_F
179 };
180
181 &cpu0 {
182 cpu0-supply = <&buck2_reg>;
183 };
184
185 &dsi_0 {
186 vddcore-supply = <&ldo8_reg>;
187 vddio-supply = <&ldo10_reg>;
188 samsung,pll-clock-frequency = <2400000
189 samsung,burst-clock-frequency = <32000
190 samsung,esc-clock-frequency = <1000000
191 status = "okay";
192
193 bridge@0 {
194 reg = <0>;
195 compatible = "toshiba,tc358764
196 vddc-supply = <&vcc_1v2_reg>;
197 vddio-supply = <&vcc_1v8_reg>;
198 vddlvds-supply = <&vcc_3v3_reg
199 reset-gpios = <&gpd1 6 GPIO_AC
200
201 ports {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 port@1 {
205 reg = <1>;
206 bridge_out_ep:
207 remote
208 };
209 };
210 };
211 };
212 };
213
214 &fimd {
215 status = "okay";
216 };
217
218 &hdmi {
219 pinctrl-names = "default";
220 pinctrl-0 = <&hdmi_hpd>;
221 status = "okay";
222 ddc = <&i2c_ddc>;
223 hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>
224 vdd_osc-supply = <&ldo10_reg>;
225 vdd_pll-supply = <&ldo8_reg>;
226 vdd-supply = <&ldo8_reg>;
227 };
228
229 &i2c_0 {
230 status = "okay";
231 samsung,i2c-sda-delay = <100>;
232 samsung,i2c-max-bus-freq = <20000>;
233 samsung,i2c-slave-addr = <0x66>;
234
235 pmic@66 {
236 compatible = "samsung,s5m8767-
237 reg = <0x66>;
238 interrupt-parent = <&gpx3>;
239 interrupts = <2 IRQ_TYPE_LEVEL
240 pinctrl-names = "default";
241 pinctrl-0 = <&s5m8767_irq>;
242 wakeup-source;
243
244 vinb1-supply = <&main_dc_reg>;
245 vinb2-supply = <&main_dc_reg>;
246 vinb3-supply = <&main_dc_reg>;
247 vinb4-supply = <&main_dc_reg>;
248 vinb5-supply = <&main_dc_reg>;
249 vinb6-supply = <&main_dc_reg>;
250 vinb7-supply = <&main_dc_reg>;
251 vinb8-supply = <&main_dc_reg>;
252 vinb9-supply = <&main_dc_reg>;
253
254 vinl1-supply = <&buck7_reg>;
255 vinl2-supply = <&buck7_reg>;
256 vinl3-supply = <&buck7_reg>;
257 vinl4-supply = <&main_dc_reg>;
258 vinl5-supply = <&main_dc_reg>;
259 vinl6-supply = <&main_dc_reg>;
260 vinl7-supply = <&main_dc_reg>;
261 vinl8-supply = <&buck8_reg>;
262 vinl9-supply = <&buck8_reg>;
263
264 s5m8767,pmic-buck-dvs-gpios =
265
266
267 s5m8767,pmic-buck-ds-gpios = <
268 <
269 <
270
271 s5m8767_osc: clocks {
272 compatible = "samsung,
273 #clock-cells = <1>;
274 clock-output-names = "
275 };
276
277 regulators {
278 ldo1_reg: LDO1 {
279 regulator-name
280 regulator-min-
281 regulator-max-
282 regulator-alwa
283 regulator-boot
284 op_mode = <1>;
285 };
286
287 ldo2_reg: LDO2 {
288 regulator-name
289 regulator-min-
290 regulator-max-
291 regulator-alwa
292 regulator-boot
293 op_mode = <1>;
294 };
295
296 ldo3_reg: LDO3 {
297 regulator-name
298 regulator-min-
299 regulator-max-
300 regulator-alwa
301 regulator-boot
302 op_mode = <1>;
303 };
304
305 ldo4_reg: LDO4 {
306 regulator-name
307 regulator-min-
308 regulator-max-
309 regulator-alwa
310 op_mode = <1>;
311 };
312
313 ldo5_reg: LDO5 {
314 regulator-name
315 regulator-min-
316 regulator-max-
317 regulator-alwa
318 regulator-boot
319 op_mode = <1>;
320 };
321
322 ldo6_reg: LDO6 {
323 regulator-name
324 regulator-min-
325 regulator-max-
326 regulator-alwa
327 regulator-boot
328 op_mode = <1>;
329 };
330
331 ldo7_reg: LDO7 {
332 regulator-name
333 regulator-min-
334 regulator-max-
335 regulator-alwa
336 regulator-boot
337 op_mode = <1>;
338 };
339
340 ldo8_reg: LDO8 {
341 regulator-name
342 regulator-min-
343 regulator-max-
344 regulator-alwa
345 regulator-boot
346 op_mode = <1>;
347 };
348
349 ldo9_reg: LDO9 {
350 regulator-name
351 regulator-min-
352 regulator-max-
353 op_mode = <1>;
354 };
355
356 ldo10_reg: LDO10 {
357 regulator-name
358 regulator-min-
359 regulator-max-
360 regulator-alwa
361 regulator-boot
362 op_mode = <1>;
363 };
364
365 ldo11_reg: LDO11 {
366 regulator-name
367 regulator-min-
368 regulator-max-
369 regulator-alwa
370 regulator-boot
371 op_mode = <1>;
372 };
373
374 ldo12_reg: LDO12 {
375 regulator-name
376 regulator-min-
377 regulator-max-
378 regulator-alwa
379 regulator-boot
380 op_mode = <1>;
381 };
382
383 ldo13_reg: LDO13 {
384 regulator-name
385 regulator-min-
386 regulator-max-
387 regulator-alwa
388 regulator-boot
389 op_mode = <1>;
390 };
391
392 ldo14_reg: LDO14 {
393 regulator-name
394 regulator-min-
395 regulator-max-
396 regulator-alwa
397 regulator-boot
398 op_mode = <1>;
399 };
400
401 ldo15_reg: LDO15 {
402 regulator-name
403 regulator-min-
404 regulator-max-
405 regulator-alwa
406 regulator-boot
407 op_mode = <1>;
408 };
409
410 ldo16_reg: LDO16 {
411 regulator-name
412 regulator-min-
413 regulator-max-
414 regulator-alwa
415 regulator-boot
416 op_mode = <1>;
417 };
418
419 ldo17_reg: LDO17 {
420 regulator-name
421 regulator-min-
422 regulator-max-
423 regulator-alwa
424 regulator-boot
425 op_mode = <1>;
426 };
427
428 ldo18_reg: LDO18 {
429 regulator-name
430 regulator-min-
431 regulator-max-
432 op_mode = <1>;
433 };
434
435 ldo22_reg: LDO22 {
436 regulator-name
437 regulator-min-
438 regulator-max-
439 op_mode = <1>;
440 };
441
442 ldo23_reg: LDO23 {
443 regulator-name
444 regulator-min-
445 regulator-max-
446 op_mode = <1>;
447 };
448
449 ldo25_reg: LDO25 {
450 regulator-name
451 regulator-min-
452 regulator-max-
453 op_mode = <1>;
454 };
455
456 ldo26_reg: LDO26 {
457 regulator-name
458 regulator-min-
459 regulator-max-
460 op_mode = <1>;
461 };
462
463 buck1_reg: BUCK1 {
464 regulator-name
465 regulator-min-
466 regulator-max-
467 regulator-alwa
468 regulator-boot
469 op_mode = <1>;
470 };
471
472 buck2_reg: BUCK2 {
473 regulator-name
474 regulator-min-
475 regulator-max-
476 regulator-alwa
477 regulator-boot
478 op_mode = <1>;
479 };
480
481 buck3_reg: BUCK3 {
482 regulator-name
483 regulator-min-
484 regulator-max-
485 regulator-alwa
486 regulator-boot
487 op_mode = <1>;
488 };
489
490 buck4_reg: BUCK4 {
491 regulator-name
492 regulator-min-
493 regulator-max-
494 regulator-alwa
495 regulator-boot
496 op_mode = <1>;
497 };
498
499 buck5_reg: BUCK5 {
500 regulator-name
501 regulator-min-
502 regulator-max-
503 regulator-alwa
504 regulator-boot
505 op_mode = <1>;
506 };
507
508 buck7_reg: BUCK7 {
509 regulator-name
510 regulator-alwa
511 op_mode = <1>;
512 };
513
514 buck8_reg: BUCK8 {
515 regulator-name
516 regulator-alwa
517 op_mode = <1>;
518 };
519
520 buck9_reg: BUCK9 {
521 regulator-name
522 regulator-min-
523 regulator-max-
524 op_mode = <1>;
525 };
526 };
527 };
528 };
529
530 &i2c_3 {
531 status = "okay";
532
533 wm1811: audio-codec@1a {
534 compatible = "wlf,wm1811";
535 reg = <0x1a>;
536 clocks = <&i2s0 CLK_I2S_CDCLK>
537 clock-names = "MCLK1";
538
539 AVDD2-supply = <&main_dc_reg>;
540 CPVDD-supply = <&main_dc_reg>;
541 DBVDD1-supply = <&main_dc_reg>
542 DBVDD2-supply = <&main_dc_reg>
543 DBVDD3-supply = <&main_dc_reg>
544 LDO1VDD-supply = <&main_dc_reg
545 SPKVDD1-supply = <&main_dc_reg
546 SPKVDD2-supply = <&main_dc_reg
547
548 wlf,ldo1ena-gpios = <&gpb0 0 G
549 wlf,ldo2ena-gpios = <&gpb0 1 G
550 };
551 };
552
553 &i2c_8 {
554 status = "okay";
555 /* used by HDMI PHY */
556 samsung,i2c-sda-delay = <100>;
557 samsung,i2c-max-bus-freq = <66000>;
558 };
559
560 &i2c_9 {
561 status = "okay";
562 samsung,i2c-sda-delay = <100>;
563 samsung,i2c-max-bus-freq = <40000>;
564 };
565
566 &i2s0 {
567 assigned-clocks = <&i2s0 CLK_I2S_RCLK_
568 assigned-clock-parents = <&clock_audss
569 status = "okay";
570 };
571
572 &i2s0_bus {
573 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2
574 };
575
576 &mali {
577 mali-supply = <&buck4_reg>;
578 status = "okay";
579 };
580
581 &mixer {
582 status = "okay";
583 };
584
585 &mmc_0 {
586 status = "okay";
587 broken-cd;
588 card-detect-delay = <200>;
589 samsung,dw-mshc-ciu-div = <3>;
590 samsung,dw-mshc-sdr-timing = <2 3>;
591 samsung,dw-mshc-ddr-timing = <1 2>;
592 vmmc-supply = <&mmc_reg>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bu
595 bus-width = <8>;
596 cap-mmc-highspeed;
597 mmc-ddr-1_8v;
598 };
599
600 &mmc_2 {
601 status = "okay";
602 card-detect-delay = <200>;
603 samsung,dw-mshc-ciu-div = <3>;
604 samsung,dw-mshc-sdr-timing = <2 3>;
605 samsung,dw-mshc-ddr-timing = <1 2>;
606 vmmc-supply = <&mmc_reg>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd
609 bus-width = <4>;
610 disable-wp;
611 cap-sd-highspeed;
612 };
613
614 &pinctrl_0 {
615 s5m8767_irq: s5m8767-irq-pins {
616 samsung,pins = "gpx3-2";
617 samsung,pin-pud = <EXYNOS_PIN_
618 };
619 };
620
621 &rtc {
622 clocks = <&clock CLK_RTC>, <&s5m8767_o
623 clock-names = "rtc", "rtc_src";
624 status = "okay";
625 };
626
627 &sata {
628 status = "okay";
629 };
630
631 &sata_phy {
632 status = "okay";
633 samsung,exynos-sataphy-i2c-phandle = <
634 };
635
636 &sata_phy_i2c {
637 status = "okay";
638 };
639
640 &usbdrd {
641 vdd10-supply = <&ldo15_reg>;
642 vdd33-supply = <&ldo12_reg>;
643 };
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