1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2012 Linaro Ltd
4 */
5
6 #include <dt-bindings/interrupt-controller/irq
7 #include <dt-bindings/interrupt-controller/arm
8 #include <dt-bindings/clock/ste-db8500-clkout.
9 #include <dt-bindings/reset/stericsson,db8500-
10 #include <dt-bindings/mfd/dbx500-prcmu.h>
11 #include <dt-bindings/arm/ux500_pm_domains.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 /* This stablilizes the device enumera
20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &i2c4;
26 spi0 = &spi0;
27 spi1 = &spi1;
28 spi2 = &spi2;
29 spi3 = &spi3;
30 serial0 = &serial0;
31 serial1 = &serial1;
32 serial2 = &serial2;
33 };
34
35 chosen {
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41 enable-method = "ste,dbx500-sm
42
43 cpu-map {
44 cluster0 {
45 core0 {
46 cpu =
47 };
48 core1 {
49 cpu =
50 };
51 };
52 };
53 CPU0: cpu@300 {
54 device_type = "cpu";
55 compatible = "arm,cort
56 reg = <0x300>;
57 clocks = <&prcmu_clk P
58 clock-names = "cpu";
59 clock-latency = <20000
60 #cooling-cells = <2>;
61 };
62 CPU1: cpu@301 {
63 device_type = "cpu";
64 compatible = "arm,cort
65 reg = <0x301>;
66 };
67 };
68
69 thermal-zones {
70 /*
71 * Thermal zone for the SoC, u
72 * PRCMU for temperature and t
73 * cooling.
74 */
75 cpu_thermal: cpu-thermal {
76 polling-delay-passive
77 /*
78 * This sensor fires i
79 * zone, so no polling
80 */
81 polling-delay = <0>;
82
83 thermal-sensors = <&th
84
85 trips {
86 cpu_alert: cpu
87 temper
88 hyster
89 type =
90 };
91 cpu-crit {
92 temper
93 hyster
94 type =
95 };
96 };
97
98 cooling-maps {
99 trip = <&cpu_a
100 cooling-device
101 contribution =
102 };
103 };
104 };
105
106 soc {
107 #address-cells = <1>;
108 #size-cells = <1>;
109 compatible = "stericsson,db850
110 interrupt-parent = <&intc>;
111 ranges;
112
113 /*
114 * 640KB ESRAM (embedded stati
115 * into 5 banks of 128 KB each
116 * used by different accelerat
117 * their power domains: ESRAM0
118 * ESRAM 3+4.
119 */
120 sram@40000000 {
121 /* The first (always o
122 compatible = "mmio-sra
123 reg = <0x40000000 0x20
124 #address-cells = <1>;
125 #size-cells = <1>;
126 ranges = <0 0x40000000
127
128 sram@0 {
129 compatible = "
130 reg = <0x0 0x1
131 pool;
132 };
133 lcpa: sram@10000 {
134 /*
135 * This eSRAM
136 * for Logical
137 * where these
138 * This is add
139 * pool is use
140 */
141 compatible = "
142 label = "DMA40
143 reg = <0x10000
144 };
145 sram@10800 {
146 compatible = "
147 reg = <0x10800
148 pool;
149 };
150 };
151 sram@40020000 {
152 /* ESRAM 1+2, 256 KB *
153 compatible = "mmio-sra
154 reg = <0x40020000 0x40
155 #address-cells = <1>;
156 #size-cells = <1>;
157 ranges = <0 0x40020000
158 };
159 sram@40060000 {
160 /* ESRAM 3+4, 256 KB *
161 compatible = "mmio-sra
162 reg = <0x40060000 0x40
163 #address-cells = <1>;
164 #size-cells = <1>;
165 ranges = <0 0x40060000
166
167 lcla: sram@20000 {
168 /*
169 * This eSRAM
170 * for Logical
171 * where these
172 * This is add
173 * pool is use
174 */
175 compatible = "
176 label = "DMA40
177 reg = <0x20000
178 };
179 };
180
181 ptm@801ae000 {
182 compatible = "arm,core
183 reg = <0x801ae000 0x10
184
185 clocks = <&prcmu_clk P
186 clock-names = "apb_pcl
187 cpu = <&CPU0>;
188 out-ports {
189 port {
190 ptm0_o
191
192 };
193 };
194 };
195 };
196
197 ptm@801af000 {
198 compatible = "arm,core
199 reg = <0x801af000 0x10
200
201 clocks = <&prcmu_clk P
202 clock-names = "apb_pcl
203 cpu = <&CPU1>;
204 out-ports {
205 port {
206 ptm1_o
207
208 };
209 };
210 };
211 };
212
213 funnel@801a6000 {
214 compatible = "arm,core
215 reg = <0x801a6000 0x10
216
217 clocks = <&prcmu_clk P
218 clock-names = "apb_pcl
219 out-ports {
220 port {
221 funnel
222
223
224 };
225 };
226 };
227
228 in-ports {
229 #address-cells
230 #size-cells =
231
232 port@0 {
233 reg =
234 funnel
235
236 };
237 };
238
239 port@1 {
240 reg =
241 funnel
242
243 };
244 };
245 };
246 };
247
248 replicator {
249 compatible = "arm,core
250 clocks = <&prcmu_clk P
251 clock-names = "atclk";
252
253 out-ports {
254 #address-cells
255 #size-cells =
256
257 port@0 {
258 reg =
259 replic
260
261 };
262 };
263 port@1 {
264 reg =
265 replic
266
267 };
268 };
269 };
270
271 in-ports {
272 port {
273 replic
274
275 };
276 };
277 };
278 };
279
280 tpiu@80190000 {
281 compatible = "arm,core
282 reg = <0x80190000 0x10
283
284 clocks = <&prcmu_clk P
285 clock-names = "apb_pcl
286 in-ports {
287 port {
288 tpiu_i
289
290 };
291 };
292 };
293 };
294
295 etb@801a4000 {
296 compatible = "arm,core
297 reg = <0x801a4000 0x10
298
299 clocks = <&prcmu_clk P
300 clock-names = "apb_pcl
301 in-ports {
302 port {
303 etb_in
304
305 };
306 };
307 };
308 };
309
310 intc: interrupt-controller@a04
311 compatible = "arm,cort
312 #interrupt-cells = <3>
313 #address-cells = <1>;
314 interrupt-controller;
315 reg = <0xa0411000 0x10
316 <0xa0410100 0x10
317 };
318
319 scu@a0410000 {
320 compatible = "arm,cort
321 reg = <0xa0410000 0x10
322 };
323
324 /*
325 * The backup RAM is used for
326 * and various things like spi
327 */
328 backupram@80150000 {
329 compatible = "ste,dbx5
330 reg = <0x80150000 0x20
331 };
332
333 L2: cache-controller {
334 compatible = "arm,pl31
335 reg = <0xa0412000 0x10
336 interrupts = <GIC_SPI
337 cache-unified;
338 cache-level = <2>;
339 };
340
341 pmu {
342 compatible = "arm,cort
343 interrupts = <GIC_SPI
344 };
345
346 pm_domains: pm_domains0 {
347 compatible = "stericss
348 #power-domain-cells =
349 };
350
351 clocks {
352 compatible = "stericss
353 /*
354 * Registers for the C
355 * groups 1, 2, 3, 5,
356 */
357 reg = <0x8012f000 0x10
358 <0x8000f000 0x1000
359 <0xa03cf000 0x1000
360
361 prcmu_clk: prcmu-clock
362 #clock-cells =
363 };
364
365 prcc_pclk: prcc-periph
366 #clock-cells =
367 };
368
369 prcc_kclk: prcc-kernel
370 #clock-cells =
371 };
372
373 prcc_reset: prcc-reset
374 #reset-cells =
375 };
376
377 rtc_clk: rtc32k-clock
378 #clock-cells =
379 };
380
381 smp_twd_clk: smp-twd-c
382 #clock-cells =
383 };
384
385 clkout_clk: clkout-clo
386 /* Cell 1 id,
387 #clock-cells =
388 };
389 };
390
391 mtu@a03c6000 {
392 /* Nomadik System Time
393 compatible = "st,nomad
394 reg = <0xa03c6000 0x10
395 interrupts = <GIC_SPI
396
397 clocks = <&prcmu_clk P
398 clock-names = "timclk"
399 };
400
401 timer@a0410600 {
402 compatible = "arm,cort
403 reg = <0xa0410600 0x20
404 interrupts = <GIC_PPI
405
406 clocks = <&smp_twd_clk
407 };
408
409 watchdog@a0410620 {
410 compatible = "arm,cort
411 reg = <0xa0410620 0x20
412 interrupts = <GIC_PPI
413 clocks = <&smp_twd_clk
414 };
415
416 rtc@80154000 {
417 compatible = "arm,pl03
418 reg = <0x80154000 0x10
419 interrupts = <GIC_SPI
420
421 clocks = <&rtc_clk>;
422 clock-names = "apb_pcl
423 };
424
425 gpio0: gpio@8012e000 {
426 compatible = "stericss
427 "st,nomadik-gp
428 reg = <0x8012e000 0x80
429 interrupts = <GIC_SPI
430 interrupt-controller;
431 #interrupt-cells = <2>
432 st,supports-sleepmode;
433 gpio-controller;
434 #gpio-cells = <2>;
435 gpio-bank = <0>;
436 gpio-ranges = <&pinctr
437 clocks = <&prcc_pclk 1
438 };
439
440 gpio1: gpio@8012e080 {
441 compatible = "stericss
442 "st,nomadik-gp
443 reg = <0x8012e080 0x80
444 interrupts = <GIC_SPI
445 interrupt-controller;
446 #interrupt-cells = <2>
447 st,supports-sleepmode;
448 gpio-controller;
449 #gpio-cells = <2>;
450 gpio-bank = <1>;
451 gpio-ranges = <&pinctr
452 clocks = <&prcc_pclk 1
453 };
454
455 gpio2: gpio@8000e000 {
456 compatible = "stericss
457 "st,nomadik-gp
458 reg = <0x8000e000 0x80
459 interrupts = <GIC_SPI
460 interrupt-controller;
461 #interrupt-cells = <2>
462 st,supports-sleepmode;
463 gpio-controller;
464 #gpio-cells = <2>;
465 gpio-bank = <2>;
466 gpio-ranges = <&pinctr
467 clocks = <&prcc_pclk 3
468 };
469
470 gpio3: gpio@8000e080 {
471 compatible = "stericss
472 "st,nomadik-gp
473 reg = <0x8000e080 0x80
474 interrupts = <GIC_SPI
475 interrupt-controller;
476 #interrupt-cells = <2>
477 st,supports-sleepmode;
478 gpio-controller;
479 #gpio-cells = <2>;
480 gpio-bank = <3>;
481 gpio-ranges = <&pinctr
482 clocks = <&prcc_pclk 3
483 };
484
485 gpio4: gpio@8000e100 {
486 compatible = "stericss
487 "st,nomadik-gp
488 reg = <0x8000e100 0x80
489 interrupts = <GIC_SPI
490 interrupt-controller;
491 #interrupt-cells = <2>
492 st,supports-sleepmode;
493 gpio-controller;
494 #gpio-cells = <2>;
495 gpio-bank = <4>;
496 gpio-ranges = <&pinctr
497 clocks = <&prcc_pclk 3
498 };
499
500 gpio5: gpio@8000e180 {
501 compatible = "stericss
502 "st,nomadik-gp
503 reg = <0x8000e180 0x80
504 interrupts = <GIC_SPI
505 interrupt-controller;
506 #interrupt-cells = <2>
507 st,supports-sleepmode;
508 gpio-controller;
509 #gpio-cells = <2>;
510 gpio-bank = <5>;
511 gpio-ranges = <&pinctr
512 clocks = <&prcc_pclk 3
513 };
514
515 gpio6: gpio@8011e000 {
516 compatible = "stericss
517 "st,nomadik-gp
518 reg = <0x8011e000 0x80
519 interrupts = <GIC_SPI
520 interrupt-controller;
521 #interrupt-cells = <2>
522 st,supports-sleepmode;
523 gpio-controller;
524 #gpio-cells = <2>;
525 gpio-bank = <6>;
526 gpio-ranges = <&pinctr
527 clocks = <&prcc_pclk 2
528 };
529
530 gpio7: gpio@8011e080 {
531 compatible = "stericss
532 "st,nomadik-gp
533 reg = <0x8011e080 0x80
534 interrupts = <GIC_SPI
535 interrupt-controller;
536 #interrupt-cells = <2>
537 st,supports-sleepmode;
538 gpio-controller;
539 #gpio-cells = <2>;
540 gpio-bank = <7>;
541 gpio-ranges = <&pinctr
542 clocks = <&prcc_pclk 2
543 };
544
545 gpio8: gpio@a03fe000 {
546 compatible = "stericss
547 "st,nomadik-gp
548 reg = <0xa03fe000 0x80
549 interrupts = <GIC_SPI
550 interrupt-controller;
551 #interrupt-cells = <2>
552 st,supports-sleepmode;
553 gpio-controller;
554 #gpio-cells = <2>;
555 gpio-bank = <8>;
556 gpio-ranges = <&pinctr
557 clocks = <&prcc_pclk 5
558 };
559
560 pinctrl: pinctrl {
561 compatible = "stericss
562 nomadik-gpio-chips = <
563
564
565 prcm = <&prcmu>;
566 };
567
568 usb_per5@a03e0000 {
569 compatible = "stericss
570 reg = <0xa03e0000 0x10
571 interrupts = <GIC_SPI
572 interrupt-names = "mc"
573
574 dr_mode = "otg";
575
576 dmas = <&dma 38 0 0x2>
577 <&dma 38 0 0x0>
578 <&dma 37 0 0x2>
579 <&dma 37 0 0x0>
580 <&dma 36 0 0x2>
581 <&dma 36 0 0x0>
582 <&dma 19 0 0x2>
583 <&dma 19 0 0x0>
584 <&dma 18 0 0x2>
585 <&dma 18 0 0x0>
586 <&dma 17 0 0x2>
587 <&dma 17 0 0x0>
588 <&dma 16 0 0x2>
589 <&dma 16 0 0x0>
590 <&dma 39 0 0x2>
591 <&dma 39 0 0x0>
592
593 dma-names = "iep_1_9",
594 "iep_2_10"
595 "iep_3_11"
596 "iep_4_12"
597 "iep_5_13"
598 "iep_6_14"
599 "iep_7_15"
600 "iep_8",
601
602 clocks = <&prcc_pclk 5
603 };
604
605 dma: dma-controller@801C0000 {
606 compatible = "stericss
607 reg = <0x801C0000 0x10
608 reg-names = "base";
609 interrupts = <GIC_SPI
610 sram = <&lcpa>, <&lcla
611
612 #dma-cells = <3>;
613 memcpy-channels = <56
614
615 clocks = <&prcmu_clk P
616 };
617
618 prcmu: prcmu@80157000 {
619 compatible = "stericss
620 reg = <0x80157000 0x20
621 reg-names = "prcmu", "
622 interrupts = <GIC_SPI
623 #address-cells = <1>;
624 #size-cells = <1>;
625 interrupt-controller;
626 #interrupt-cells = <2>
627 ranges;
628
629 prcmu-timer-4@80157450
630 compatible = "
631 reg = <0x80157
632 };
633
634 thermal: thermal@80157
635 compatible = "
636 reg = <0x80157
637 interrupt-pare
638 interrupts = <
639 <
640 interrupt-name
641 #thermal-senso
642 };
643
644 db8500-prcmu-regulator
645 compatible = "
646
647 // DB8500_REGU
648 db8500_vape_re
649 regula
650 };
651
652 // DB8500_REGU
653 db8500_varm_re
654 };
655
656 // DB8500_REGU
657 db8500_vmodem_
658 };
659
660 // DB8500_REGU
661 db8500_vpll_re
662 };
663
664 // DB8500_REGU
665 db8500_vsmps1_
666 };
667
668 // DB8500_REGU
669 db8500_vsmps2_
670 };
671
672 // DB8500_REGU
673 db8500_vsmps3_
674 };
675
676 // DB8500_REGU
677 db8500_vrf1_re
678 };
679
680 // DB8500_REGU
681 db8500_sva_mmd
682 };
683
684 // DB8500_REGU
685 db8500_sva_mmd
686 };
687
688 // DB8500_REGU
689 db8500_sva_pip
690 };
691
692 // DB8500_REGU
693 db8500_sia_mmd
694 };
695
696 // DB8500_REGU
697 db8500_sia_mmd
698 };
699
700 // DB8500_REGU
701 db8500_sia_pip
702 };
703
704 // DB8500_REGU
705 db8500_sga_reg
706 vin-su
707 };
708
709 // DB8500_REGU
710 db8500_b2r2_mc
711 vin-su
712 };
713
714 // DB8500_REGU
715 db8500_esram12
716 };
717
718 // DB8500_REGU
719 db8500_esram12
720 };
721
722 // DB8500_REGU
723 db8500_esram34
724 };
725
726 // DB8500_REGU
727 db8500_esram34
728 };
729 };
730 };
731
732 i2c0: i2c@80004000 {
733 compatible = "stericss
734 reg = <0x80004000 0x10
735 interrupts = <GIC_SPI
736
737 #address-cells = <1>;
738 #size-cells = <0>;
739
740 clock-frequency = <400
741 clocks = <&prcc_kclk 3
742 clock-names = "i2cclk"
743 power-domains = <&pm_d
744 resets = <&prcc_reset
745
746 status = "disabled";
747 };
748
749 i2c1: i2c@80122000 {
750 compatible = "stericss
751 reg = <0x80122000 0x10
752 interrupts = <GIC_SPI
753
754 #address-cells = <1>;
755 #size-cells = <0>;
756
757 clock-frequency = <400
758
759 clocks = <&prcc_kclk 1
760 clock-names = "i2cclk"
761 power-domains = <&pm_d
762 resets = <&prcc_reset
763
764 status = "disabled";
765 };
766
767 i2c2: i2c@80128000 {
768 compatible = "stericss
769 reg = <0x80128000 0x10
770 interrupts = <GIC_SPI
771
772 #address-cells = <1>;
773 #size-cells = <0>;
774
775 clock-frequency = <400
776
777 clocks = <&prcc_kclk 1
778 clock-names = "i2cclk"
779 power-domains = <&pm_d
780 resets = <&prcc_reset
781
782 status = "disabled";
783 };
784
785 i2c3: i2c@80110000 {
786 compatible = "stericss
787 reg = <0x80110000 0x10
788 interrupts = <GIC_SPI
789
790 #address-cells = <1>;
791 #size-cells = <0>;
792
793 clock-frequency = <400
794
795 clocks = <&prcc_kclk 2
796 clock-names = "i2cclk"
797 power-domains = <&pm_d
798 resets = <&prcc_reset
799
800 status = "disabled";
801 };
802
803 i2c4: i2c@8012a000 {
804 compatible = "stericss
805 reg = <0x8012a000 0x10
806 interrupts = <GIC_SPI
807
808 #address-cells = <1>;
809 #size-cells = <0>;
810
811 clock-frequency = <400
812
813 clocks = <&prcc_kclk 1
814 clock-names = "i2cclk"
815 power-domains = <&pm_d
816 resets = <&prcc_reset
817
818 status = "disabled";
819 };
820
821 ssp0: spi@80002000 {
822 compatible = "arm,pl02
823 reg = <0x80002000 0x10
824 interrupts = <GIC_SPI
825 #address-cells = <1>;
826 #size-cells = <0>;
827 clocks = <&prcc_kclk 3
828 clock-names = "sspclk"
829 dmas = <&dma 8 0 0x2>,
830 <&dma 8 0 0x0>;
831 dma-names = "rx", "tx"
832 power-domains = <&pm_d
833 resets = <&prcc_reset
834
835 status = "disabled";
836 };
837
838 ssp1: spi@80003000 {
839 compatible = "arm,pl02
840 reg = <0x80003000 0x10
841 interrupts = <GIC_SPI
842 #address-cells = <1>;
843 #size-cells = <0>;
844 clocks = <&prcc_kclk 3
845 clock-names = "sspclk"
846 dmas = <&dma 9 0 0x2>,
847 <&dma 9 0 0x0>;
848 dma-names = "rx", "tx"
849 power-domains = <&pm_d
850 resets = <&prcc_reset
851
852 status = "disabled";
853 };
854
855 spi0: spi@8011a000 {
856 compatible = "arm,pl02
857 reg = <0x8011a000 0x10
858 interrupts = <GIC_SPI
859 #address-cells = <1>;
860 #size-cells = <0>;
861 /* Same clock wired to
862 clocks = <&prcc_pclk 2
863 clock-names = "sspclk"
864 dmas = <&dma 0 0 0x2>,
865 <&dma 0 0 0x0>;
866 dma-names = "rx", "tx"
867 power-domains = <&pm_d
868
869 status = "disabled";
870 };
871
872 spi1: spi@80112000 {
873 compatible = "arm,pl02
874 reg = <0x80112000 0x10
875 interrupts = <GIC_SPI
876 #address-cells = <1>;
877 #size-cells = <0>;
878 /* Same clock wired to
879 clocks = <&prcc_pclk 2
880 clock-names = "sspclk"
881 dmas = <&dma 35 0 0x2>
882 <&dma 35 0 0x0>
883 dma-names = "rx", "tx"
884 power-domains = <&pm_d
885
886 status = "disabled";
887 };
888
889 spi2: spi@80111000 {
890 compatible = "arm,pl02
891 reg = <0x80111000 0x10
892 interrupts = <GIC_SPI
893 #address-cells = <1>;
894 #size-cells = <0>;
895 /* Same clock wired to
896 clocks = <&prcc_pclk 2
897 clock-names = "sspclk"
898 dmas = <&dma 33 0 0x2>
899 <&dma 33 0 0x0>
900 dma-names = "rx", "tx"
901 power-domains = <&pm_d
902
903 status = "disabled";
904 };
905
906 spi3: spi@80129000 {
907 compatible = "arm,pl02
908 reg = <0x80129000 0x10
909 interrupts = <GIC_SPI
910 #address-cells = <1>;
911 #size-cells = <0>;
912 /* Same clock wired to
913 clocks = <&prcc_pclk 1
914 clock-names = "sspclk"
915 dmas = <&dma 40 0 0x2>
916 <&dma 40 0 0x0>
917 dma-names = "rx", "tx"
918 power-domains = <&pm_d
919 resets = <&prcc_reset
920
921 status = "disabled";
922 };
923
924 serial0: serial@80120000 {
925 compatible = "arm,pl01
926 reg = <0x80120000 0x10
927 interrupts = <GIC_SPI
928
929 dmas = <&dma 13 0 0x2>
930 <&dma 13 0 0x0>
931 dma-names = "rx", "tx"
932
933 clocks = <&prcc_kclk 1
934 clock-names = "uart",
935 resets = <&prcc_reset
936
937 status = "disabled";
938 };
939
940 serial1: serial@80121000 {
941 compatible = "arm,pl01
942 reg = <0x80121000 0x10
943 interrupts = <GIC_SPI
944
945 dmas = <&dma 12 0 0x2>
946 <&dma 12 0 0x0>
947 dma-names = "rx", "tx"
948
949 clocks = <&prcc_kclk 1
950 clock-names = "uart",
951 resets = <&prcc_reset
952
953 status = "disabled";
954 };
955
956 serial2: serial@80007000 {
957 compatible = "arm,pl01
958 reg = <0x80007000 0x10
959 interrupts = <GIC_SPI
960
961 dmas = <&dma 11 0 0x2>
962 <&dma 11 0 0x0>
963 dma-names = "rx", "tx"
964
965 clocks = <&prcc_kclk 3
966 clock-names = "uart",
967 resets = <&prcc_reset
968
969 status = "disabled";
970 };
971
972 mmc@80126000 {
973 compatible = "arm,pl18
974 reg = <0x80126000 0x10
975 interrupts = <GIC_SPI
976
977 dmas = <&dma 29 0 0x2>
978 <&dma 29 0 0x0>
979 dma-names = "rx", "tx"
980
981 clocks = <&prcc_kclk 1
982 clock-names = "sdi", "
983 power-domains = <&pm_d
984 resets = <&prcc_reset
985
986 status = "disabled";
987 };
988
989 mmc@80118000 {
990 compatible = "arm,pl18
991 reg = <0x80118000 0x10
992 interrupts = <GIC_SPI
993
994 dmas = <&dma 32 0 0x2>
995 <&dma 32 0 0x0>
996 dma-names = "rx", "tx"
997
998 clocks = <&prcc_kclk 2
999 clock-names = "sdi", "
1000 power-domains = <&pm_
1001 resets = <&prcc_reset
1002
1003 status = "disabled";
1004 };
1005
1006 mmc@80005000 {
1007 compatible = "arm,pl1
1008 reg = <0x80005000 0x1
1009 interrupts = <GIC_SPI
1010
1011 dmas = <&dma 28 0 0x2
1012 <&dma 28 0 0x0
1013 dma-names = "rx", "tx
1014
1015 clocks = <&prcc_kclk
1016 clock-names = "sdi",
1017 power-domains = <&pm_
1018 resets = <&prcc_reset
1019
1020 status = "disabled";
1021 };
1022
1023 mmc@80119000 {
1024 compatible = "arm,pl1
1025 reg = <0x80119000 0x1
1026 interrupts = <GIC_SPI
1027
1028 dmas = <&dma 41 0 0x2
1029 <&dma 41 0 0x0
1030 dma-names = "rx", "tx
1031
1032 clocks = <&prcc_kclk
1033 clock-names = "sdi",
1034 power-domains = <&pm_
1035 resets = <&prcc_reset
1036
1037 status = "disabled";
1038 };
1039
1040 mmc@80114000 {
1041 compatible = "arm,pl1
1042 reg = <0x80114000 0x1
1043 interrupts = <GIC_SPI
1044
1045 dmas = <&dma 42 0 0x2
1046 <&dma 42 0 0x0
1047 dma-names = "rx", "tx
1048
1049 clocks = <&prcc_kclk
1050 clock-names = "sdi",
1051 power-domains = <&pm_
1052 resets = <&prcc_reset
1053
1054 status = "disabled";
1055 };
1056
1057 mmc@80008000 {
1058 compatible = "arm,pl1
1059 reg = <0x80008000 0x1
1060 interrupts = <GIC_SPI
1061
1062 dmas = <&dma 43 0 0x2
1063 <&dma 43 0 0x0
1064 dma-names = "rx", "tx
1065
1066 clocks = <&prcc_kclk
1067 clock-names = "sdi",
1068 power-domains = <&pm_
1069 resets = <&prcc_reset
1070
1071 status = "disabled";
1072 };
1073
1074 sound {
1075 compatible = "sterics
1076 stericsson,cpu-dai =
1077 };
1078
1079 msp0: msp@80123000 {
1080 compatible = "sterics
1081 reg = <0x80123000 0x1
1082 interrupts = <GIC_SPI
1083 v-ape-supply = <&db85
1084
1085 dmas = <&dma 31 0 0x1
1086 <&dma 31 0 0x1
1087 dma-names = "rx", "tx
1088
1089 clocks = <&prcc_kclk
1090 clock-names = "msp",
1091 resets = <&prcc_reset
1092
1093 status = "disabled";
1094 };
1095
1096 msp1: msp@80124000 {
1097 compatible = "sterics
1098 reg = <0x80124000 0x1
1099 interrupts = <GIC_SPI
1100 v-ape-supply = <&db85
1101
1102 /* This DMA channel o
1103 dmas = <&dma 30 0 0x1
1104 dma-names = "tx";
1105
1106 clocks = <&prcc_kclk
1107 clock-names = "msp",
1108 resets = <&prcc_reset
1109
1110 status = "disabled";
1111 };
1112
1113 // HDMI sound
1114 msp2: msp@80117000 {
1115 compatible = "sterics
1116 reg = <0x80117000 0x1
1117 interrupts = <GIC_SPI
1118 v-ape-supply = <&db85
1119
1120 dmas = <&dma 14 0 0x1
1121 <&dma 14 1 0x1
1122
1123 dma-names = "rx", "tx
1124
1125 clocks = <&prcc_kclk
1126 clock-names = "msp",
1127 resets = <&prcc_reset
1128
1129 status = "disabled";
1130 };
1131
1132 msp3: msp@80125000 {
1133 compatible = "sterics
1134 reg = <0x80125000 0x1
1135 interrupts = <GIC_SPI
1136 v-ape-supply = <&db85
1137
1138 /* This DMA channel o
1139 dmas = <&dma 30 0 0x1
1140 dma-names = "rx";
1141
1142 clocks = <&prcc_kclk
1143 clock-names = "msp",
1144 resets = <&prcc_reset
1145
1146 status = "disabled";
1147 };
1148
1149 external-bus@50000000 {
1150 compatible = "simple-
1151 reg = <0x50000000 0x4
1152 #address-cells = <1>;
1153 #size-cells = <1>;
1154 ranges = <0 0x5000000
1155 status = "disabled";
1156 };
1157
1158 gpu@a0300000 {
1159 /*
1160 * This block is refe
1161 * in documentation b
1162 * MALI-400 GPU block
1163 */
1164 compatible = "sterics
1165 reg = <0xa0300000 0x1
1166 interrupts = <GIC_SPI
1167 <GIC_SPI
1168 <GIC_SPI
1169 <GIC_SPI
1170 <GIC_SPI
1171 interrupt-names = "gp
1172 "gp
1173 "pp
1174 "pp
1175 "co
1176 clocks = <&prcmu_clk
1177 clock-names = "bus",
1178 mali-supply = <&db850
1179 power-domains = <&pm_
1180 };
1181
1182 mcde@a0350000 {
1183 compatible = "ste,mcd
1184 reg = <0xa0350000 0x1
1185 interrupts = <GIC_SPI
1186 epod-supply = <&db850
1187 clocks = <&prcmu_clk
1188 <&prcmu_clk
1189 <&prcmu_clk
1190 clock-names = "mcde",
1191 #address-cells = <1>;
1192 #size-cells = <1>;
1193 ranges;
1194 status = "disabled";
1195
1196 dsi0: dsi@a0351000 {
1197 compatible =
1198 reg = <0xa035
1199 clocks = <&pr
1200 clock-names =
1201 #address-cell
1202 #size-cells =
1203 };
1204 dsi1: dsi@a0352000 {
1205 compatible =
1206 reg = <0xa035
1207 clocks = <&pr
1208 clock-names =
1209 #address-cell
1210 #size-cells =
1211 };
1212 dsi2: dsi@a0353000 {
1213 compatible =
1214 reg = <0xa035
1215 /* This DSI p
1216 clocks = <&pr
1217 clock-names =
1218 #address-cell
1219 #size-cells =
1220 };
1221 };
1222
1223 cryp@a03cb000 {
1224 compatible = "sterics
1225 reg = <0xa03cb000 0x1
1226 interrupts = <GIC_SPI
1227 clocks = <&prcc_pclk
1228 power-domains = <&pm_
1229 };
1230
1231 hash@a03c2000 {
1232 compatible = "sterics
1233 reg = <0xa03c2000 0x1
1234 clocks = <&prcc_pclk
1235 power-domains = <&pm_
1236 };
1237 };
1238 };
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