1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014 STMicroelectronics R&D L
4 */
5 #include <dt-bindings/clock/stih407-clks.h>
6 / {
7 /*
8 * Fixed 30MHz oscillator inputs to So
9 */
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 };
15
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
20 };
21
22 clocks {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 /*
28 * A9 PLL.
29 */
30 clockgen-a9@92b0000 {
31 compatible = "st,clkge
32 reg = <0x92b0000 0x100
33
34 clockgen_a9_pll: clock
35 #clock-cells =
36 compatible = "
37
38 clocks = <&clk
39 };
40
41 clk_m_a9: clk-m-a9 {
42 #clock-cells =
43 compatible = "
44
45 clocks = <&clo
46 <&clo
47 <&clk
48 <&clk
49
50 /*
51 * ARM Periphe
52 */
53 arm_periph_clk
54 #clock
55 compat
56
57 clocks
58 clock-
59 clock-
60 };
61 };
62 };
63
64 clockgen-a@90ff000 {
65 compatible = "st,clkge
66 reg = <0x90ff000 0x100
67
68 clk_s_a0_pll: clk-s-a0
69 #clock-cells =
70 compatible = "
71
72 clocks = <&clk
73 };
74
75 clk_s_a0_flexgen: clk-
76 compatible = "
77
78 #clock-cells =
79
80 clocks = <&clk
81 <&clk
82 };
83 };
84
85 clk_s_c0: clockgen-c@9103000 {
86 compatible = "st,clkge
87 reg = <0x9103000 0x100
88
89 clk_s_c0_pll0: clk-s-c
90 #clock-cells =
91 compatible = "
92
93 clocks = <&clk
94 };
95
96 clk_s_c0_pll1: clk-s-c
97 #clock-cells =
98 compatible = "
99
100 clocks = <&clk
101 };
102
103 clk_s_c0_quadfs: clk-s
104 #clock-cells =
105 compatible = "
106
107 clocks = <&clk
108 };
109
110 clk_s_c0_flexgen: clk-
111 #clock-cells =
112 compatible = "
113
114 clocks = <&clk
115 <&clk
116 <&clk
117 <&clk
118 <&clk
119 <&clk
120 <&clk
121
122 /*
123 * ARM Periphe
124 */
125 clk_m_a9_ext2f
126 #clock
127 compat
128
129 clocks
130
131 clock-
132
133 clock-
134 clock-
135 };
136 };
137 };
138
139 clockgen-d0@9104000 {
140 compatible = "st,clkge
141 reg = <0x9104000 0x100
142
143 clk_s_d0_quadfs: clk-s
144 #clock-cells =
145 compatible = "
146
147 clocks = <&clk
148 };
149
150 clk_s_d0_flexgen: clk-
151 #clock-cells =
152 compatible = "
153
154 clocks = <&clk
155 <&clk
156 <&clk
157 <&clk
158 <&clk
159 };
160 };
161
162 clockgen-d2@9106000 {
163 compatible = "st,clkge
164 reg = <0x9106000 0x100
165
166 clk_s_d2_quadfs: clk-s
167 #clock-cells =
168 compatible = "
169
170 clocks = <&clk
171 };
172
173 clk_s_d2_flexgen: clk-
174 #clock-cells =
175 compatible = "
176
177 clocks = <&clk
178 <&clk
179 <&clk
180 <&clk
181 <&clk
182 <&clk
183 <&clk
184 };
185 };
186
187 clockgen-d3@9107000 {
188 compatible = "st,clkge
189 reg = <0x9107000 0x100
190
191 clk_s_d3_quadfs: clk-s
192 #clock-cells =
193 compatible = "
194
195 clocks = <&clk
196 };
197
198 clk_s_d3_flexgen: clk-
199 #clock-cells =
200 compatible = "
201
202 clocks = <&clk
203 <&clk
204 <&clk
205 <&clk
206 <&clk
207 };
208 };
209 };
210 };
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