1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014 STMicroelectronics Limit
4 * Author: Giuseppe Cavallaro <peppe.cavallaro@
5 */
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm
8 / {
9
10 aliases {
11 /* 0-5: PIO_SBC */
12 gpio0 = &pio0;
13 gpio1 = &pio1;
14 gpio2 = &pio2;
15 gpio3 = &pio3;
16 gpio4 = &pio4;
17 gpio5 = &pio5;
18 /* 10-19: PIO_FRONT0 */
19 gpio6 = &pio10;
20 gpio7 = &pio11;
21 gpio8 = &pio12;
22 gpio9 = &pio13;
23 gpio10 = &pio14;
24 gpio11 = &pio15;
25 gpio12 = &pio16;
26 gpio13 = &pio17;
27 gpio14 = &pio18;
28 gpio15 = &pio19;
29 /* 20: PIO_FRONT1 */
30 gpio16 = &pio20;
31 /* 30-35: PIO_REAR */
32 gpio17 = &pio30;
33 gpio18 = &pio31;
34 gpio19 = &pio32;
35 gpio20 = &pio33;
36 gpio21 = &pio34;
37 gpio22 = &pio35;
38 /* 40-42: PIO_FLASH */
39 gpio23 = &pio40;
40 gpio24 = &pio41;
41 gpio25 = &pio42;
42 };
43
44 soc {
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "st,stih4
49 st,syscfg = <&syscfg_s
50 reg = <0x0961f080 0x4>
51 reg-names = "irqmux";
52 interrupts = <GIC_SPI
53 interrupt-names = "irq
54 ranges = <0 0x09610000
55
56 pio0: gpio@9610000 {
57 gpio-controlle
58 #gpio-cells =
59 interrupt-cont
60 #interrupt-cel
61 reg = <0x0 0x1
62 st,bank-name =
63 };
64 pio1: gpio@9611000 {
65 gpio-controlle
66 #gpio-cells =
67 interrupt-cont
68 #interrupt-cel
69 reg = <0x1000
70 st,bank-name =
71 };
72 pio2: gpio@9612000 {
73 gpio-controlle
74 #gpio-cells =
75 interrupt-cont
76 #interrupt-cel
77 reg = <0x2000
78 st,bank-name =
79 };
80 pio3: gpio@9613000 {
81 gpio-controlle
82 #gpio-cells =
83 interrupt-cont
84 #interrupt-cel
85 reg = <0x3000
86 st,bank-name =
87 };
88 pio4: gpio@9614000 {
89 gpio-controlle
90 #gpio-cells =
91 interrupt-cont
92 #interrupt-cel
93 reg = <0x4000
94 st,bank-name =
95 };
96
97 pio5: gpio@9615000 {
98 gpio-controlle
99 #gpio-cells =
100 interrupt-cont
101 #interrupt-cel
102 reg = <0x5000
103 st,bank-name =
104 st,retime-pin-
105 };
106
107 cec0 {
108 pinctrl_cec0_d
109 st,pin
110
111 };
112 };
113 };
114
115 rc {
116 pinctrl_ir: ir
117 st,pin
118
119 };
120 };
121
122 pinctrl_uhf: u
123 st,pin
124
125 };
126 };
127
128 pinctrl_tx: tx
129 st,pin
130
131 };
132 };
133
134 pinctrl_tx_od:
135 st,pin
136
137 };
138 };
139 };
140
141 /* SBC_ASC0 - UART10 *
142 sbc_serial0 {
143 pinctrl_sbc_se
144 st,pin
145
146
147 };
148 };
149 };
150 /* SBC_ASC1 - UART11 *
151 sbc_serial1 {
152 pinctrl_sbc_se
153 st,pin
154
155
156 };
157 };
158 };
159
160 i2c10 {
161 pinctrl_i2c10_
162 st,pin
163
164
165 };
166 };
167 };
168
169 i2c11 {
170 pinctrl_i2c11_
171 st,pin
172
173
174 };
175 };
176 };
177
178 keyscan {
179 pinctrl_keysca
180 st,pin
181
182
183
184
185
186
187
188
189
190 };
191 };
192 };
193
194 gmac1 {
195 /*
196 * Almost all
197 * switch wher
198 * iface via I
199 * by using de
200 * standard PH
201 */
202 pinctrl_rgmii1
203 st,pin
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219 };
220 };
221
222 pinctrl_rgmii1
223 st,pin
224
225
226
227 };
228 };
229
230 pinctrl_rgmii1
231 st,pin
232
233
234 };
235 };
236
237 pinctrl_mii1:
238 st,pin
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261 };
262 };
263
264 pinctrl_rmii1:
265 st,pin
266
267
268
269
270
271
272
273
274
275
276 };
277 };
278
279 pinctrl_rmii1_
280 st,pin
281
282 };
283 };
284
285 pinctrl_rmii1_
286 st,pin
287
288 };
289 };
290 };
291
292 pwm1 {
293 pinctrl_pwm1_c
294 st,pin
295
296
297 };
298 };
299 pinctrl_pwm1_c
300 st,pin
301
302
303 };
304 };
305 pinctrl_pwm1_c
306 st,pin
307
308 };
309 };
310 pinctrl_pwm1_c
311 st,pin
312
313 };
314 };
315 };
316
317 spi10 {
318 pinctrl_spi10_
319 st,pin
320
321
322
323 };
324 };
325
326 pinctrl_spi10_
327 st,pin
328
329
330 };
331 };
332 };
333
334 spi11 {
335 pinctrl_spi11_
336 st,pin
337
338
339
340 };
341 };
342
343 pinctrl_spi11_
344 st,pin
345
346
347 };
348 };
349 };
350
351 spi12 {
352 pinctrl_spi12_
353 st,pin
354
355
356
357 };
358 };
359
360 pinctrl_spi12_
361 st,pin
362
363
364 };
365 };
366 };
367 };
368
369 pin-controller-front0@920f080
370 #address-cells = <1>;
371 #size-cells = <1>;
372 compatible = "st,stih4
373 st,syscfg = <&syscfg_f
374 reg = <0x0920f080 0x4>
375 reg-names = "irqmux";
376 interrupts = <GIC_SPI
377 interrupt-names = "irq
378 ranges = <0 0x09200000
379
380 pio10: pio@9200000 {
381 gpio-controlle
382 #gpio-cells =
383 interrupt-cont
384 #interrupt-cel
385 reg = <0x0 0x1
386 st,bank-name =
387 };
388 pio11: pio@9201000 {
389 gpio-controlle
390 #gpio-cells =
391 interrupt-cont
392 #interrupt-cel
393 reg = <0x1000
394 st,bank-name =
395 };
396 pio12: pio@9202000 {
397 gpio-controlle
398 #gpio-cells =
399 interrupt-cont
400 #interrupt-cel
401 reg = <0x2000
402 st,bank-name =
403 };
404 pio13: pio@9203000 {
405 gpio-controlle
406 #gpio-cells =
407 interrupt-cont
408 #interrupt-cel
409 reg = <0x3000
410 st,bank-name =
411 };
412 pio14: pio@9204000 {
413 gpio-controlle
414 #gpio-cells =
415 interrupt-cont
416 #interrupt-cel
417 reg = <0x4000
418 st,bank-name =
419 };
420 pio15: pio@9205000 {
421 gpio-controlle
422 #gpio-cells =
423 interrupt-cont
424 #interrupt-cel
425 reg = <0x5000
426 st,bank-name =
427 };
428 pio16: pio@9206000 {
429 gpio-controlle
430 #gpio-cells =
431 interrupt-cont
432 #interrupt-cel
433 reg = <0x6000
434 st,bank-name =
435 };
436 pio17: pio@9207000 {
437 gpio-controlle
438 #gpio-cells =
439 interrupt-cont
440 #interrupt-cel
441 reg = <0x7000
442 st,bank-name =
443 };
444 pio18: pio@9208000 {
445 gpio-controlle
446 #gpio-cells =
447 interrupt-cont
448 #interrupt-cel
449 reg = <0x8000
450 st,bank-name =
451 };
452 pio19: pio@9209000 {
453 gpio-controlle
454 #gpio-cells =
455 interrupt-cont
456 #interrupt-cel
457 reg = <0x9000
458 st,bank-name =
459 };
460
461 /* Comms */
462 serial0 {
463 pinctrl_serial
464 st,pin
465
466
467 };
468 };
469 pinctrl_serial
470 st,pin
471
472
473
474
475 };
476 };
477 };
478
479 serial1 {
480 pinctrl_serial
481 st,pin
482
483
484 };
485 };
486 };
487
488 serial2 {
489 pinctrl_serial
490 st,pin
491
492
493 };
494 };
495 };
496
497 mmc1 {
498 pinctrl_sd1: s
499 st,pin
500
501
502
503
504
505
506
507
508
509
510 };
511 };
512 };
513
514
515 i2c0 {
516 pinctrl_i2c0_d
517 st,pin
518
519
520 };
521 };
522 };
523
524 i2c1 {
525 pinctrl_i2c1_d
526 st,pin
527
528
529 };
530 };
531 };
532
533 i2c2 {
534 pinctrl_i2c2_d
535 st,pin
536
537
538 };
539 };
540
541 pinctrl_i2c2_a
542 st,pin
543
544
545 };
546 };
547 };
548
549 i2c3 {
550 pinctrl_i2c3_d
551 st,pin
552
553
554 };
555 };
556 pinctrl_i2c3_a
557 st,pin
558
559
560 };
561 };
562 pinctrl_i2c3_a
563 st,pin
564
565
566 };
567 };
568 };
569
570 spi0 {
571 pinctrl_spi0_d
572 st,pin
573
574
575
576 };
577 };
578
579 pinctrl_spi0_3
580 st,pin
581
582
583 };
584 };
585
586 pinctrl_spi0_4
587 st,pin
588
589
590
591 };
592 };
593
594 pinctrl_spi0_3
595 st,pin
596
597
598 };
599 };
600 };
601
602 spi1 {
603 pinctrl_spi1_d
604 st,pin
605
606
607
608 };
609 };
610
611 pinctrl_spi1_3
612 st,pin
613
614
615 };
616 };
617
618 pinctrl_spi1_4
619 st,pin
620
621
622
623 };
624 };
625
626 pinctrl_spi1_3
627 st,pin
628
629
630 };
631 };
632 };
633
634 spi2 {
635 pinctrl_spi2_d
636 st,pin
637
638
639
640 };
641 };
642
643 pinctrl_spi2_3
644 st,pin
645
646
647 };
648 };
649
650 pinctrl_spi2_4
651 st,pin
652
653
654
655 };
656 };
657
658 pinctrl_spi2_3
659 st,pin
660
661
662 };
663 };
664
665 pinctrl_spi2_4
666 st,pin
667
668
669
670 };
671 };
672
673 pinctrl_spi2_3
674 st,pin
675
676
677 };
678 };
679 };
680
681 spi3 {
682 pinctrl_spi3_d
683 st,pin
684
685
686
687 };
688 };
689
690 pinctrl_spi3_3
691 st,pin
692
693
694 };
695 };
696
697 pinctrl_spi3_4
698 st,pin
699
700
701
702 };
703 };
704
705 pinctrl_spi3_3
706 st,pin
707
708
709 };
710 };
711
712 pinctrl_spi3_4
713 st,pin
714
715
716
717 };
718 };
719
720 pinctrl_spi3_3
721 st,pin
722
723
724 };
725 };
726 };
727
728 tsin0 {
729 pinctrl_tsin0_
730 st,pin
731
732
733
734
735
736
737
738
739
740
741
742
743 };
744 };
745 pinctrl_tsin0_
746 st,pin
747
748
749
750
751
752 };
753 };
754 };
755
756 tsin1 {
757 pinctrl_tsin1_
758 st,pin
759
760
761
762
763
764
765
766
767
768
769
770
771 };
772 };
773 pinctrl_tsin1_
774 st,pin
775
776
777
778
779
780 };
781 };
782 };
783
784 tsin2 {
785 pinctrl_tsin2_
786 st,pin
787
788
789
790
791
792
793
794
795
796
797
798
799 };
800 };
801 pinctrl_tsin2_
802 st,pin
803
804
805
806
807
808 };
809 };
810 };
811
812 tsin3 {
813 pinctrl_tsin3_
814 st,pin
815
816
817
818
819
820 };
821 };
822 };
823
824 tsin4 {
825 pinctrl_tsin4_
826 st,pin
827
828
829
830
831
832 };
833 };
834 };
835
836 tsin5 {
837 pinctrl_tsin5_
838 st,pin
839
840
841
842
843
844 };
845 };
846 pinctrl_tsin5_
847 st,pin
848
849
850
851
852
853 };
854 };
855 };
856
857 tsout0 {
858 pinctrl_tsout0
859 st,pin
860
861
862
863
864
865
866
867
868
869
870
871
872 };
873 };
874 pinctrl_tsout0
875 st,pin
876
877
878
879
880
881 };
882 };
883 };
884
885 tsout1 {
886 pinctrl_tsout1
887 st,pin
888
889
890
891
892
893 };
894 };
895 };
896
897 mtsin0 {
898 pinctrl_mtsin0
899 st,pin
900
901
902
903
904
905
906
907
908
909
910
911
912 };
913 };
914 };
915
916 systrace {
917 pinctrl_systra
918 st,pin
919
920
921
922
923
924 };
925 };
926 };
927 };
928
929 pin-controller-front1@921f080
930 #address-cells = <1>;
931 #size-cells = <1>;
932 compatible = "st,stih4
933 st,syscfg = <&syscfg_f
934 reg = <0x0921f080 0x4>
935 reg-names = "irqmux";
936 interrupts = <GIC_SPI
937 interrupt-names = "irq
938 ranges = <0 0x09210000
939
940 pio20: pio@9210000 {
941 gpio-controlle
942 #gpio-cells =
943 interrupt-cont
944 #interrupt-cel
945 reg = <0x0 0x1
946 st,bank-name =
947 };
948
949 tsin4 {
950 pinctrl_tsin4_
951 st,pin
952
953
954
955
956
957 };
958 };
959 };
960 };
961
962 pin-controller-rear@922f080 {
963 #address-cells = <1>;
964 #size-cells = <1>;
965 compatible = "st,stih4
966 st,syscfg = <&syscfg_r
967 reg = <0x0922f080 0x4>
968 reg-names = "irqmux";
969 interrupts = <GIC_SPI
970 interrupt-names = "irq
971 ranges = <0 0x09220000
972
973 pio30: gpio@9220000 {
974 gpio-controlle
975 #gpio-cells =
976 interrupt-cont
977 #interrupt-cel
978 reg = <0x0 0x1
979 st,bank-name =
980 };
981 pio31: gpio@9221000 {
982 gpio-controlle
983 #gpio-cells =
984 interrupt-cont
985 #interrupt-cel
986 reg = <0x1000
987 st,bank-name =
988 };
989 pio32: gpio@9222000 {
990 gpio-controlle
991 #gpio-cells =
992 interrupt-cont
993 #interrupt-cel
994 reg = <0x2000
995 st,bank-name =
996 };
997 pio33: gpio@9223000 {
998 gpio-controlle
999 #gpio-cells =
1000 interrupt-con
1001 #interrupt-ce
1002 reg = <0x3000
1003 st,bank-name
1004 };
1005 pio34: gpio@9224000 {
1006 gpio-controll
1007 #gpio-cells =
1008 interrupt-con
1009 #interrupt-ce
1010 reg = <0x4000
1011 st,bank-name
1012 };
1013 pio35: gpio@9225000 {
1014 gpio-controll
1015 #gpio-cells =
1016 interrupt-con
1017 #interrupt-ce
1018 reg = <0x5000
1019 st,bank-name
1020 st,retime-pin
1021 };
1022
1023 i2c4 {
1024 pinctrl_i2c4_
1025 st,pi
1026
1027
1028 };
1029 };
1030 };
1031
1032 i2c5 {
1033 pinctrl_i2c5_
1034 st,pi
1035
1036
1037 };
1038 };
1039 };
1040
1041 usb3 {
1042 pinctrl_usb3:
1043 st,pi
1044
1045
1046
1047 };
1048 };
1049 };
1050
1051 pwm0 {
1052 pinctrl_pwm0_
1053 st,pi
1054
1055
1056 };
1057 };
1058 };
1059
1060 spi4 {
1061 pinctrl_spi4_
1062 st,pi
1063
1064
1065
1066 };
1067 };
1068
1069 pinctrl_spi4_
1070 st,pi
1071
1072
1073 };
1074 };
1075
1076 pinctrl_spi4_
1077 st,pi
1078
1079
1080
1081 };
1082 };
1083
1084 pinctrl_spi4_
1085 st,pi
1086
1087
1088 };
1089 };
1090 };
1091
1092 i2s_out {
1093 pinctrl_i2s_8
1094 st,pi
1095
1096
1097
1098
1099
1100
1101
1102 };
1103 };
1104
1105 pinctrl_i2s_2
1106 st,pi
1107
1108
1109
1110
1111 };
1112 };
1113 };
1114
1115 i2s_in {
1116 pinctrl_i2s_8
1117 st,pi
1118
1119
1120
1121
1122
1123
1124
1125
1126 };
1127 };
1128
1129 pinctrl_i2s_2
1130 st,pi
1131
1132
1133
1134
1135 };
1136 };
1137 };
1138
1139 spdif_out {
1140 pinctrl_spdif
1141 st,pi
1142
1143 };
1144 };
1145 };
1146
1147 serial3 {
1148 pinctrl_seria
1149 st,pi
1150
1151
1152 };
1153 };
1154 };
1155 };
1156
1157 pin-controller-flash@923f080
1158 #address-cells = <1>;
1159 #size-cells = <1>;
1160 compatible = "st,stih
1161 st,syscfg = <&syscfg_
1162 reg = <0x0923f080 0x4
1163 reg-names = "irqmux";
1164 interrupts = <GIC_SPI
1165 interrupt-names = "ir
1166 ranges = <0 0x0923000
1167
1168 pio40: gpio@9230000 {
1169 gpio-controll
1170 #gpio-cells =
1171 interrupt-con
1172 #interrupt-ce
1173 reg = <0 0x10
1174 st,bank-name
1175 };
1176 pio41: gpio@9231000 {
1177 gpio-controll
1178 #gpio-cells =
1179 interrupt-con
1180 #interrupt-ce
1181 reg = <0x1000
1182 st,bank-name
1183 };
1184 pio42: gpio@9232000 {
1185 gpio-controll
1186 #gpio-cells =
1187 interrupt-con
1188 #interrupt-ce
1189 reg = <0x2000
1190 st,bank-name
1191 };
1192
1193 mmc0 {
1194 pinctrl_mmc0:
1195 st,pi
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206 };
1207 };
1208 pinctrl_sd0:
1209 st,pi
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221 };
1222 };
1223 };
1224
1225 fsm {
1226 pinctrl_fsm:
1227 st,pi
1228
1229
1230
1231
1232
1233
1234 };
1235 };
1236 };
1237
1238 nand {
1239 pinctrl_nand:
1240 st,pi
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257 };
1258 };
1259 };
1260 };
1261 };
1262 };
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