1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3
2 /*
3 * Copyright (C) STMicroelectronics 2017 - All
4 * Author: Alexandre Torgue <alexandre.torgue@
5 */
6
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rcc.h>
9
10 / {
11 soc {
12 pinctrl: pinctrl@40020000 {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges = <0 0x40020000
16 interrupt-parent = <&e
17 st,syscfg = <&syscfg 0
18
19 gpioa: gpio@40020000 {
20 gpio-controlle
21 #gpio-cells =
22 interrupt-cont
23 #interrupt-cel
24 reg = <0x0 0x4
25 clocks = <&rcc
26 st,bank-name =
27 };
28
29 gpiob: gpio@40020400 {
30 gpio-controlle
31 #gpio-cells =
32 interrupt-cont
33 #interrupt-cel
34 reg = <0x400 0
35 clocks = <&rcc
36 st,bank-name =
37 };
38
39 gpioc: gpio@40020800 {
40 gpio-controlle
41 #gpio-cells =
42 interrupt-cont
43 #interrupt-cel
44 reg = <0x800 0
45 clocks = <&rcc
46 st,bank-name =
47 };
48
49 gpiod: gpio@40020c00 {
50 gpio-controlle
51 #gpio-cells =
52 interrupt-cont
53 #interrupt-cel
54 reg = <0xc00 0
55 clocks = <&rcc
56 st,bank-name =
57 };
58
59 gpioe: gpio@40021000 {
60 gpio-controlle
61 #gpio-cells =
62 interrupt-cont
63 #interrupt-cel
64 reg = <0x1000
65 clocks = <&rcc
66 st,bank-name =
67 };
68
69 gpiof: gpio@40021400 {
70 gpio-controlle
71 #gpio-cells =
72 interrupt-cont
73 #interrupt-cel
74 reg = <0x1400
75 clocks = <&rcc
76 st,bank-name =
77 };
78
79 gpiog: gpio@40021800 {
80 gpio-controlle
81 #gpio-cells =
82 interrupt-cont
83 #interrupt-cel
84 reg = <0x1800
85 clocks = <&rcc
86 st,bank-name =
87 };
88
89 gpioh: gpio@40021c00 {
90 gpio-controlle
91 #gpio-cells =
92 interrupt-cont
93 #interrupt-cel
94 reg = <0x1c00
95 clocks = <&rcc
96 st,bank-name =
97 };
98
99 gpioi: gpio@40022000 {
100 gpio-controlle
101 #gpio-cells =
102 interrupt-cont
103 #interrupt-cel
104 reg = <0x2000
105 clocks = <&rcc
106 st,bank-name =
107 };
108
109 gpioj: gpio@40022400 {
110 gpio-controlle
111 #gpio-cells =
112 interrupt-cont
113 #interrupt-cel
114 reg = <0x2400
115 clocks = <&rcc
116 st,bank-name =
117 };
118
119 gpiok: gpio@40022800 {
120 gpio-controlle
121 #gpio-cells =
122 interrupt-cont
123 #interrupt-cel
124 reg = <0x2800
125 clocks = <&rcc
126 st,bank-name =
127 };
128
129 cec_pins_a: cec-0 {
130 pins {
131 pinmux
132 slew-r
133 drive-
134 bias-d
135 };
136 };
137
138 usart1_pins_a: usart1-
139 pins1 {
140 pinmux
141 bias-d
142 drive-
143 slew-r
144 };
145 pins2 {
146 pinmux
147 bias-d
148 };
149 };
150
151 usart1_pins_b: usart1-
152 pins1 {
153 pinmux
154 bias-d
155 drive-
156 slew-r
157 };
158 pins2 {
159 pinmux
160 bias-d
161 };
162 };
163
164 i2c1_pins_b: i2c1-0 {
165 pins {
166 pinmux
167
168 bias-d
169 drive-
170 slew-r
171 };
172 };
173
174 i2c3_pins_a: i2c3-0 {
175 pins {
176 pinmux
177
178 bias-d
179 drive-
180 slew-r
181 };
182 };
183
184 usbotg_hs_pins_a: usbo
185 pins {
186 pinmux
187
188
189
190
191
192
193
194
195
196
197
198 bias-d
199 drive-
200 slew-r
201 };
202 };
203
204 usbotg_hs_pins_b: usbo
205 pins {
206 pinmux
207
208
209
210
211
212
213
214
215
216
217
218 bias-d
219 drive-
220 slew-r
221 };
222 };
223
224 usbotg_fs_pins_a: usbo
225 pins {
226 pinmux
227
228
229 bias-d
230 drive-
231 slew-r
232 };
233 };
234
235 sdio_pins_a: sdio-pins
236 pins {
237 pinmux
238
239
240
241
242
243 drive-
244 slew-r
245 };
246 };
247
248 sdio_pins_od_a: sdio-p
249 pins1 {
250 pinmux
251
252
253
254
255 drive-
256 slew-r
257 };
258
259 pins2 {
260 pinmux
261 drive-
262 slew-r
263 };
264 };
265
266 sdio_pins_sleep_a: sdi
267 pins {
268 pinmux
269
270
271
272
273
274 };
275 };
276
277 sdio_pins_b: sdio-pins
278 pins {
279 pinmux
280
281
282
283
284
285 drive-
286 slew-r
287 };
288 };
289
290 sdio_pins_od_b: sdio-p
291 pins1 {
292 pinmux
293
294
295
296
297 drive-
298 slew-r
299 };
300
301 pins2 {
302 pinmux
303 drive-
304 slew-r
305 };
306 };
307
308 sdio_pins_sleep_b: sdi
309 pins {
310 pinmux
311
312
313
314
315
316 };
317 };
318
319 can1_pins_a: can1-0 {
320 pins1 {
321 pinmux
322 };
323 pins2 {
324 pinmux
325 bias-p
326 };
327 };
328
329 can1_pins_b: can1-1 {
330 pins1 {
331 pinmux
332 };
333 pins2 {
334 pinmux
335 bias-p
336 };
337 };
338
339 can1_pins_c: can1-2 {
340 pins1 {
341 pinmux
342 };
343 pins2 {
344 pinmux
345 bias-p
346
347 };
348 };
349
350 can1_pins_d: can1-3 {
351 pins1 {
352 pinmux
353 };
354 pins2 {
355 pinmux
356 bias-p
357
358 };
359 };
360
361 can2_pins_a: can2-0 {
362 pins1 {
363 pinmux
364 };
365 pins2 {
366 pinmux
367 bias-p
368 };
369 };
370
371 can2_pins_b: can2-1 {
372 pins1 {
373 pinmux
374 };
375 pins2 {
376 pinmux
377 bias-p
378 };
379 };
380
381 can3_pins_a: can3-0 {
382 pins1 {
383 pinmux
384 };
385 pins2 {
386 pinmux
387 bias-p
388 };
389 };
390
391 can3_pins_b: can3-1 {
392 pins1 {
393 pinmux
394 };
395 pins2 {
396 pinmux
397 bias-p
398 };
399 };
400
401 ltdc_pins_a: ltdc-0 {
402 pins {
403 pinmux
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431 slew-r
432 };
433 };
434 };
435 };
436 };
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