1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3
2 /*
3 * Copyright (C) STMicroelectronics 2017 - All
4 * Author: Ludovic Barre <ludovic.barre@st.com>
5 */
6 #include <dt-bindings/interrupt-controller/arm
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
9
10 / {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cort
20 clock-frequency = <650
21 device_type = "cpu";
22 reg = <0>;
23 };
24 };
25
26 arm-pmu {
27 compatible = "arm,cortex-a7-pm
28 interrupts = <GIC_SPI 200 IRQ_
29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>;
31 };
32
33 psci {
34 compatible = "arm,psci-1.0";
35 method = "smc";
36 };
37
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gi
40 #interrupt-cells = <3>;
41 interrupt-controller;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
44 };
45
46 timer {
47 compatible = "arm,armv7-timer"
48 interrupts = <GIC_PPI 13 (GIC_
49 <GIC_PPI 14 (GIC_
50 <GIC_PPI 11 (GIC_
51 <GIC_PPI 10 (GIC_
52 interrupt-parent = <&intc>;
53 arm,no-tick-in-suspend;
54 };
55
56 clocks {
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-cl
60 clock-frequency = <240
61 };
62
63 clk_hsi: clk-hsi {
64 #clock-cells = <0>;
65 compatible = "fixed-cl
66 clock-frequency = <640
67 };
68
69 clk_lse: clk-lse {
70 #clock-cells = <0>;
71 compatible = "fixed-cl
72 clock-frequency = <327
73 };
74
75 clk_lsi: clk-lsi {
76 #clock-cells = <0>;
77 compatible = "fixed-cl
78 clock-frequency = <320
79 };
80
81 clk_csi: clk-csi {
82 #clock-cells = <0>;
83 compatible = "fixed-cl
84 clock-frequency = <400
85 };
86 };
87
88 thermal-zones {
89 cpu_thermal: cpu-thermal {
90 polling-delay-passive
91 polling-delay = <0>;
92 thermal-sensors = <&dt
93
94 trips {
95 cpu_alert1: cp
96 temper
97 hyster
98 type =
99 };
100
101 cpu-crit {
102 temper
103 hyster
104 type =
105 };
106 };
107
108 cooling-maps {
109 };
110 };
111 };
112
113 booster: regulator-booster {
114 compatible = "st,stm32mp1-boos
115 st,syscfg = <&syscfg>;
116 status = "disabled";
117 };
118
119 soc {
120 compatible = "simple-bus";
121 #address-cells = <1>;
122 #size-cells = <1>;
123 interrupt-parent = <&intc>;
124 ranges;
125
126 ipcc: mailbox@4c001000 {
127 compatible = "st,stm32
128 #mbox-cells = <1>;
129 reg = <0x4c001000 0x40
130 st,proc-id = <0>;
131 interrupts-extended =
132 <&exti 61 1>,
133 <&intc GIC_SPI
134 interrupt-names = "rx"
135 clocks = <&rcc IPCC>;
136 wakeup-source;
137 status = "disabled";
138 };
139
140 rcc: rcc@50000000 {
141 compatible = "st,stm32
142 reg = <0x50000000 0x10
143 #clock-cells = <1>;
144 #reset-cells = <1>;
145 };
146
147 pwr_regulators: pwr@50001000 {
148 compatible = "st,stm32
149 reg = <0x50001000 0x10
150
151 reg11: reg11 {
152 regulator-name
153 regulator-min-
154 regulator-max-
155 };
156
157 reg18: reg18 {
158 regulator-name
159 regulator-min-
160 regulator-max-
161 };
162
163 usb33: usb33 {
164 regulator-name
165 regulator-min-
166 regulator-max-
167 };
168 };
169
170 pwr_mcu: pwr_mcu@50001014 {
171 compatible = "st,stm32
172 reg = <0x50001014 0x4>
173 };
174
175 exti: interrupt-controller@500
176 compatible = "st,stm32
177 interrupt-controller;
178 #interrupt-cells = <2>
179 reg = <0x5000d000 0x40
180 interrupts-extended =
181 <&intc GIC_SPI
182 <&intc GIC_SPI
183 <&intc GIC_SPI
184 <&intc GIC_SPI
185 <&intc GIC_SPI
186 <&intc GIC_SPI
187 <&intc GIC_SPI
188 <&intc GIC_SPI
189 <&intc GIC_SPI
190 <&intc GIC_SPI
191 <&intc GIC_SPI
192 <&intc GIC_SPI
193 <&intc GIC_SPI
194 <&intc GIC_SPI
195 <&intc GIC_SPI
196 <&intc GIC_SPI
197 <&intc GIC_SPI
198 <0>,
199 <0>,
200 <&intc GIC_SPI
201 <0>,
202 <&intc GIC_SPI
203 <&intc GIC_SPI
204 <&intc GIC_SPI
205 <&intc GIC_SPI
206 <&intc GIC_SPI
207 <&intc GIC_SPI
208 <&intc GIC_SPI
209 <&intc GIC_SPI
210 <&intc GIC_SPI
211 <&intc GIC_SPI
212 <&intc GIC_SPI
213 <&intc GIC_SPI
214 <&intc GIC_SPI
215 <0>,
216 <0>,
217 <0>,
218 <0>,
219 <0>,
220 <0>,
221 <0>,
222 <0>,
223 <0>,
224 <0>,
225 <0>,
226 <0>,
227 <&intc GIC_SPI
228 <&intc GIC_SPI
229 <&intc GIC_SPI
230 <0>,
231 <&intc GIC_SPI
232 <0>,
233 <&intc GIC_SPI
234 <&intc GIC_SPI
235 <&intc GIC_SPI
236 <0>,
237 <0>,
238 <0>,
239 <0>,
240 <0>,
241 <0>,
242 <&intc GIC_SPI
243 <0>,
244 <0>,
245 <0>,
246 <&intc GIC_SPI
247 <0>,
248 <0>,
249 <&intc GIC_SPI
250 <0>,
251 <&intc GIC_SPI
252 <0>,
253 <0>,
254 <&intc GIC_SPI
255 };
256
257 syscfg: syscon@50020000 {
258 compatible = "st,stm32
259 reg = <0x50020000 0x40
260 clocks = <&rcc SYSCFG>
261 };
262
263 dts: thermal@50028000 {
264 compatible = "st,stm32
265 reg = <0x50028000 0x10
266 interrupts = <GIC_SPI
267 clocks = <&rcc TMPSENS
268 clock-names = "pclk";
269 #thermal-sensor-cells
270 status = "disabled";
271 };
272
273 mdma1: dma-controller@58000000
274 compatible = "st,stm32
275 reg = <0x58000000 0x10
276 interrupts = <GIC_SPI
277 clocks = <&rcc MDMA>;
278 resets = <&rcc MDMA_R>
279 #dma-cells = <5>;
280 dma-channels = <32>;
281 dma-requests = <48>;
282 };
283
284 sdmmc1: mmc@58005000 {
285 compatible = "st,stm32
286 arm,primecell-periphid
287 reg = <0x58005000 0x10
288 interrupts = <GIC_SPI
289 clocks = <&rcc SDMMC1_
290 clock-names = "apb_pcl
291 resets = <&rcc SDMMC1_
292 cap-sd-highspeed;
293 cap-mmc-highspeed;
294 max-frequency = <12000
295 status = "disabled";
296 };
297
298 sdmmc2: mmc@58007000 {
299 compatible = "st,stm32
300 arm,primecell-periphid
301 reg = <0x58007000 0x10
302 interrupts = <GIC_SPI
303 clocks = <&rcc SDMMC2_
304 clock-names = "apb_pcl
305 resets = <&rcc SDMMC2_
306 cap-sd-highspeed;
307 cap-mmc-highspeed;
308 max-frequency = <12000
309 status = "disabled";
310 };
311
312 crc1: crc@58009000 {
313 compatible = "st,stm32
314 reg = <0x58009000 0x40
315 clocks = <&rcc CRC1>;
316 status = "disabled";
317 };
318
319 usbh_ohci: usb@5800c000 {
320 compatible = "generic-
321 reg = <0x5800c000 0x10
322 clocks = <&usbphyc>, <
323 resets = <&rcc USBH_R>
324 interrupts = <GIC_SPI
325 phys = <&usbphyc_port0
326 phy-names = "usb";
327 status = "disabled";
328 };
329
330 usbh_ehci: usb@5800d000 {
331 compatible = "generic-
332 reg = <0x5800d000 0x10
333 clocks = <&usbphyc>, <
334 resets = <&rcc USBH_R>
335 interrupts = <GIC_SPI
336 companion = <&usbh_ohc
337 phys = <&usbphyc_port0
338 phy-names = "usb";
339 status = "disabled";
340 };
341
342 ltdc: display-controller@5a001
343 compatible = "st,stm32
344 reg = <0x5a001000 0x40
345 interrupts = <GIC_SPI
346 <GIC_SPI
347 clocks = <&rcc LTDC_PX
348 clock-names = "lcd";
349 resets = <&rcc LTDC_R>
350 status = "disabled";
351 };
352
353 iwdg2: watchdog@5a002000 {
354 compatible = "st,stm32
355 reg = <0x5a002000 0x40
356 clocks = <&rcc IWDG2>,
357 clock-names = "pclk",
358 status = "disabled";
359 };
360
361 usbphyc: usbphyc@5a006000 {
362 #address-cells = <1>;
363 #size-cells = <0>;
364 #clock-cells = <0>;
365 compatible = "st,stm32
366 reg = <0x5a006000 0x10
367 clocks = <&rcc USBPHY_
368 resets = <&rcc USBPHY_
369 vdda1v1-supply = <®
370 vdda1v8-supply = <®
371 status = "disabled";
372
373 usbphyc_port0: usb-phy
374 #phy-cells = <
375 reg = <0>;
376 };
377
378 usbphyc_port1: usb-phy
379 #phy-cells = <
380 reg = <1>;
381 };
382 };
383
384 rtc: rtc@5c004000 {
385 compatible = "st,stm32
386 reg = <0x5c004000 0x40
387 clocks = <&rcc RTCAPB>
388 clock-names = "pclk",
389 interrupts-extended =
390 status = "disabled";
391 };
392
393 bsec: efuse@5c005000 {
394 compatible = "st,stm32
395 reg = <0x5c005000 0x40
396 #address-cells = <1>;
397 #size-cells = <1>;
398 part_number_otp: part-
399 reg = <0x4 0x1
400 };
401 vrefint: vrefin-cal@52
402 reg = <0x52 0x
403 };
404 ts_cal1: calib@5c {
405 reg = <0x5c 0x
406 };
407 ts_cal2: calib@5e {
408 reg = <0x5e 0x
409 };
410 };
411
412 etzpc: bus@5c007000 {
413 compatible = "st,stm32
414 reg = <0x5c007000 0x40
415 #address-cells = <1>;
416 #size-cells = <1>;
417 #access-controller-cel
418 ranges;
419
420 timers2: timer@4000000
421 #address-cells
422 #size-cells =
423 compatible = "
424 reg = <0x40000
425 interrupts = <
426 interrupt-name
427 clocks = <&rcc
428 clock-names =
429 dmas = <&dmamu
430 <&dmamu
431 <&dmamu
432 <&dmamu
433 <&dmamu
434 dma-names = "c
435 access-control
436 status = "disa
437
438 pwm {
439 compat
440 #pwm-c
441 status
442 };
443
444 timer@1 {
445 compat
446 reg =
447 status
448 };
449
450 counter {
451 compat
452 status
453 };
454 };
455
456 timers3: timer@4000100
457 #address-cells
458 #size-cells =
459 compatible = "
460 reg = <0x40001
461 interrupts = <
462 interrupt-name
463 clocks = <&rcc
464 clock-names =
465 dmas = <&dmamu
466 <&dmamu
467 <&dmamu
468 <&dmamu
469 <&dmamu
470 <&dmamu
471 dma-names = "c
472 access-control
473 status = "disa
474
475 pwm {
476 compat
477 #pwm-c
478 status
479 };
480
481 timer@2 {
482 compat
483 reg =
484 status
485 };
486
487 counter {
488 compat
489 status
490 };
491 };
492
493 timers4: timer@4000200
494 #address-cells
495 #size-cells =
496 compatible = "
497 reg = <0x40002
498 interrupts = <
499 interrupt-name
500 clocks = <&rcc
501 clock-names =
502 dmas = <&dmamu
503 <&dmamu
504 <&dmamu
505 <&dmamu
506 dma-names = "c
507 access-control
508 status = "disa
509
510 pwm {
511 compat
512 #pwm-c
513 status
514 };
515
516 timer@3 {
517 compat
518 reg =
519 status
520 };
521
522 counter {
523 compat
524 status
525 };
526 };
527
528 timers5: timer@4000300
529 #address-cells
530 #size-cells =
531 compatible = "
532 reg = <0x40003
533 interrupts = <
534 interrupt-name
535 clocks = <&rcc
536 clock-names =
537 dmas = <&dmamu
538 <&dmamu
539 <&dmamu
540 <&dmamu
541 <&dmamu
542 <&dmamu
543 dma-names = "c
544 access-control
545 status = "disa
546
547 pwm {
548 compat
549 #pwm-c
550 status
551 };
552
553 timer@4 {
554 compat
555 reg =
556 status
557 };
558
559 counter {
560 compat
561 status
562 };
563 };
564
565 timers6: timer@4000400
566 #address-cells
567 #size-cells =
568 compatible = "
569 reg = <0x40004
570 interrupts = <
571 interrupt-name
572 clocks = <&rcc
573 clock-names =
574 dmas = <&dmamu
575 dma-names = "u
576 access-control
577 status = "disa
578
579 timer@5 {
580 compat
581 reg =
582 status
583 };
584 };
585
586 timers7: timer@4000500
587 #address-cells
588 #size-cells =
589 compatible = "
590 reg = <0x40005
591 interrupts = <
592 interrupt-name
593 clocks = <&rcc
594 clock-names =
595 dmas = <&dmamu
596 dma-names = "u
597 access-control
598 status = "disa
599
600 timer@6 {
601 compat
602 reg =
603 status
604 };
605 };
606
607 timers12: timer@400060
608 #address-cells
609 #size-cells =
610 compatible = "
611 reg = <0x40006
612 interrupts = <
613 interrupt-name
614 clocks = <&rcc
615 clock-names =
616 access-control
617 status = "disa
618
619 pwm {
620 compat
621 #pwm-c
622 status
623 };
624
625 timer@11 {
626 compat
627 reg =
628 status
629 };
630 };
631
632 timers13: timer@400070
633 #address-cells
634 #size-cells =
635 compatible = "
636 reg = <0x40007
637 interrupts = <
638 interrupt-name
639 clocks = <&rcc
640 clock-names =
641 access-control
642 status = "disa
643
644 pwm {
645 compat
646 #pwm-c
647 status
648 };
649
650 timer@12 {
651 compat
652 reg =
653 status
654 };
655 };
656
657 timers14: timer@400080
658 #address-cells
659 #size-cells =
660 compatible = "
661 reg = <0x40008
662 interrupts = <
663 interrupt-name
664 clocks = <&rcc
665 clock-names =
666 access-control
667 status = "disa
668
669 pwm {
670 compat
671 #pwm-c
672 status
673 };
674
675 timer@13 {
676 compat
677 reg =
678 status
679 };
680 };
681
682 lptimer1: timer@400090
683 #address-cells
684 #size-cells =
685 compatible = "
686 reg = <0x40009
687 interrupts-ext
688 clocks = <&rcc
689 clock-names =
690 wakeup-source;
691 access-control
692 status = "disa
693
694 pwm {
695 compat
696 #pwm-c
697 status
698 };
699
700 trigger@0 {
701 compat
702 reg =
703 status
704 };
705
706 counter {
707 compat
708 status
709 };
710 };
711
712 i2s2: audio-controller
713 compatible = "
714 #sound-dai-cel
715 reg = <0x4000b
716 interrupts = <
717 dmas = <&dmamu
718 <&dmamu
719 dma-names = "r
720 access-control
721 status = "disa
722 };
723
724 spi2: spi@4000b000 {
725 #address-cells
726 #size-cells =
727 compatible = "
728 reg = <0x4000b
729 interrupts = <
730 clocks = <&rcc
731 resets = <&rcc
732 dmas = <&dmamu
733 <&dmamu
734 dma-names = "r
735 access-control
736 status = "disa
737 };
738
739 i2s3: audio-controller
740 compatible = "
741 #sound-dai-cel
742 reg = <0x4000c
743 interrupts = <
744 dmas = <&dmamu
745 <&dmamu
746 dma-names = "r
747 access-control
748 status = "disa
749 };
750
751 spi3: spi@4000c000 {
752 #address-cells
753 #size-cells =
754 compatible = "
755 reg = <0x4000c
756 interrupts = <
757 clocks = <&rcc
758 resets = <&rcc
759 dmas = <&dmamu
760 <&dmamu
761 dma-names = "r
762 access-control
763 status = "disa
764 };
765
766 spdifrx: audio-control
767 compatible = "
768 #sound-dai-cel
769 reg = <0x4000d
770 clocks = <&rcc
771 clock-names =
772 interrupts = <
773 dmas = <&dmamu
774 <&dmamu
775 dma-names = "r
776 access-control
777 status = "disa
778 };
779
780 usart2: serial@4000e00
781 compatible = "
782 reg = <0x4000e
783 interrupts-ext
784 clocks = <&rcc
785 wakeup-source;
786 dmas = <&dmamu
787 <&dmamu
788 dma-names = "r
789 access-control
790 status = "disa
791 };
792
793 usart3: serial@4000f00
794 compatible = "
795 reg = <0x4000f
796 interrupts-ext
797 clocks = <&rcc
798 wakeup-source;
799 dmas = <&dmamu
800 <&dmamu
801 dma-names = "r
802 access-control
803 status = "disa
804 };
805
806 uart4: serial@40010000
807 compatible = "
808 reg = <0x40010
809 interrupts-ext
810 clocks = <&rcc
811 wakeup-source;
812 dmas = <&dmamu
813 <&dmamu
814 dma-names = "r
815 access-control
816 status = "disa
817 };
818
819 uart5: serial@40011000
820 compatible = "
821 reg = <0x40011
822 interrupts-ext
823 clocks = <&rcc
824 wakeup-source;
825 dmas = <&dmamu
826 <&dmamu
827 dma-names = "r
828 access-control
829 status = "disa
830 };
831
832 i2c1: i2c@40012000 {
833 compatible = "
834 reg = <0x40012
835 interrupt-name
836 interrupts = <
837 <
838 clocks = <&rcc
839 resets = <&rcc
840 #address-cells
841 #size-cells =
842 st,syscfg-fmp
843 wakeup-source;
844 i2c-analog-fil
845 access-control
846 status = "disa
847 };
848
849 i2c2: i2c@40013000 {
850 compatible = "
851 reg = <0x40013
852 interrupt-name
853 interrupts = <
854 <
855 clocks = <&rcc
856 resets = <&rcc
857 #address-cells
858 #size-cells =
859 st,syscfg-fmp
860 wakeup-source;
861 i2c-analog-fil
862 access-control
863 status = "disa
864 };
865
866 i2c3: i2c@40014000 {
867 compatible = "
868 reg = <0x40014
869 interrupt-name
870 interrupts = <
871 <
872 clocks = <&rcc
873 resets = <&rcc
874 #address-cells
875 #size-cells =
876 st,syscfg-fmp
877 wakeup-source;
878 i2c-analog-fil
879 access-control
880 status = "disa
881 };
882
883 i2c5: i2c@40015000 {
884 compatible = "
885 reg = <0x40015
886 interrupt-name
887 interrupts = <
888 <
889 clocks = <&rcc
890 resets = <&rcc
891 #address-cells
892 #size-cells =
893 st,syscfg-fmp
894 wakeup-source;
895 i2c-analog-fil
896 access-control
897 status = "disa
898 };
899
900 cec: cec@40016000 {
901 compatible = "
902 reg = <0x40016
903 interrupts = <
904 clocks = <&rcc
905 clock-names =
906 access-control
907 status = "disa
908 };
909
910 dac: dac@40017000 {
911 compatible = "
912 reg = <0x40017
913 clocks = <&rcc
914 clock-names =
915 #address-cells
916 #size-cells =
917 access-control
918 status = "disa
919
920 dac1: dac@1 {
921 compat
922 #io-ch
923 reg =
924 status
925 };
926
927 dac2: dac@2 {
928 compat
929 #io-ch
930 reg =
931 status
932 };
933 };
934
935 uart7: serial@40018000
936 compatible = "
937 reg = <0x40018
938 interrupts-ext
939 clocks = <&rcc
940 wakeup-source;
941 dmas = <&dmamu
942 <&dmamu
943 dma-names = "r
944 access-control
945 status = "disa
946 };
947
948 uart8: serial@40019000
949 compatible = "
950 reg = <0x40019
951 interrupts-ext
952 clocks = <&rcc
953 wakeup-source;
954 dmas = <&dmamu
955 <&dmamu
956 dma-names = "r
957 access-control
958 status = "disa
959 };
960
961 timers1: timer@4400000
962 #address-cells
963 #size-cells =
964 compatible = "
965 reg = <0x44000
966 interrupts = <
967 <
968 <
969 <
970 interrupt-name
971 clocks = <&rcc
972 clock-names =
973 dmas = <&dmamu
974 <&dmamu
975 <&dmamu
976 <&dmamu
977 <&dmamu
978 <&dmamu
979 <&dmamu
980 dma-names = "c
981 "u
982 access-control
983 status = "disa
984
985 pwm {
986 compat
987 #pwm-c
988 status
989 };
990
991 timer@0 {
992 compat
993 reg =
994 status
995 };
996
997 counter {
998 compat
999 status
1000 };
1001 };
1002
1003 timers8: timer@440010
1004 #address-cell
1005 #size-cells =
1006 compatible =
1007 reg = <0x4400
1008 interrupts =
1009
1010
1011
1012 interrupt-nam
1013 clocks = <&rc
1014 clock-names =
1015 dmas = <&dmam
1016 <&dmam
1017 <&dmam
1018 <&dmam
1019 <&dmam
1020 <&dmam
1021 <&dmam
1022 dma-names = "
1023 "
1024 access-contro
1025 status = "dis
1026
1027 pwm {
1028 compa
1029 #pwm-
1030 statu
1031 };
1032
1033 timer@7 {
1034 compa
1035 reg =
1036 statu
1037 };
1038
1039 counter {
1040 compa
1041 statu
1042 };
1043 };
1044
1045 usart6: serial@440030
1046 compatible =
1047 reg = <0x4400
1048 interrupts-ex
1049 clocks = <&rc
1050 wakeup-source
1051 dmas = <&dmam
1052 <&dmamux1 72
1053 dma-names = "
1054 access-contro
1055 status = "dis
1056 };
1057
1058 i2s1: audio-controlle
1059 compatible =
1060 #sound-dai-ce
1061 reg = <0x4400
1062 interrupts =
1063 dmas = <&dmam
1064 <&dmamux1 38
1065 dma-names = "
1066 access-contro
1067 status = "dis
1068 };
1069
1070 spi1: spi@44004000 {
1071 #address-cell
1072 #size-cells =
1073 compatible =
1074 reg = <0x4400
1075 interrupts =
1076 clocks = <&rc
1077 resets = <&rc
1078 dmas = <&dmam
1079 <&dmamux1 38
1080 dma-names = "
1081 access-contro
1082 status = "dis
1083 };
1084
1085 spi4: spi@44005000 {
1086 #address-cell
1087 #size-cells =
1088 compatible =
1089 reg = <0x4400
1090 interrupts =
1091 clocks = <&rc
1092 resets = <&rc
1093 dmas = <&dmam
1094 <&dmamux1 84
1095 dma-names = "
1096 access-contro
1097 status = "dis
1098 };
1099
1100 timers15: timer@44006
1101 #address-cell
1102 #size-cells =
1103 compatible =
1104 reg = <0x4400
1105 interrupts =
1106 interrupt-nam
1107 clocks = <&rc
1108 clock-names =
1109 dmas = <&dmam
1110 <&dmam
1111 <&dmam
1112 <&dmam
1113 dma-names = "
1114 access-contro
1115 status = "dis
1116
1117 pwm {
1118 compa
1119 #pwm-
1120 statu
1121 };
1122
1123 timer@14 {
1124 compa
1125 reg =
1126 statu
1127 };
1128 };
1129
1130 timers16: timer@44007
1131 #address-cell
1132 #size-cells =
1133 compatible =
1134 reg = <0x4400
1135 interrupts =
1136 interrupt-nam
1137 clocks = <&rc
1138 clock-names =
1139 dmas = <&dmam
1140 <&dmamux1 110
1141 dma-names = "
1142 access-contro
1143 status = "dis
1144
1145 pwm {
1146 compa
1147 #pwm-
1148 statu
1149 };
1150 timer@15 {
1151 compa
1152 reg =
1153 statu
1154 };
1155 };
1156
1157 timers17: timer@44008
1158 #address-cell
1159 #size-cells =
1160 compatible =
1161 reg = <0x4400
1162 interrupts =
1163 interrupt-nam
1164 clocks = <&rc
1165 clock-names =
1166 dmas = <&dmam
1167 <&dmamux1 112
1168 dma-names = "
1169 access-contro
1170 status = "dis
1171
1172 pwm {
1173 compa
1174 #pwm-
1175 statu
1176 };
1177
1178 timer@16 {
1179 compa
1180 reg =
1181 statu
1182 };
1183 };
1184
1185 spi5: spi@44009000 {
1186 #address-cell
1187 #size-cells =
1188 compatible =
1189 reg = <0x4400
1190 interrupts =
1191 clocks = <&rc
1192 resets = <&rc
1193 dmas = <&dmam
1194 <&dmamux1 86
1195 dma-names = "
1196 access-contro
1197 status = "dis
1198 };
1199
1200 sai1: sai@4400a000 {
1201 compatible =
1202 #address-cell
1203 #size-cells =
1204 ranges = <0 0
1205 reg = <0x4400
1206 interrupts =
1207 resets = <&rc
1208 access-contro
1209 status = "dis
1210
1211 sai1a: audio-
1212 #soun
1213
1214 compa
1215 reg =
1216 clock
1217 clock
1218 dmas
1219 statu
1220 };
1221
1222 sai1b: audio-
1223 #soun
1224 compa
1225 reg =
1226 clock
1227 clock
1228 dmas
1229 statu
1230 };
1231 };
1232
1233 sai2: sai@4400b000 {
1234 compatible =
1235 #address-cell
1236 #size-cells =
1237 ranges = <0 0
1238 reg = <0x4400
1239 interrupts =
1240 resets = <&rc
1241 access-contro
1242 status = "dis
1243
1244 sai2a: audio-
1245 #soun
1246 compa
1247 reg =
1248 clock
1249 clock
1250 dmas
1251 statu
1252 };
1253
1254 sai2b: audio-
1255 #soun
1256 compa
1257 reg =
1258 clock
1259 clock
1260 dmas
1261 statu
1262 };
1263 };
1264
1265 sai3: sai@4400c000 {
1266 compatible =
1267 #address-cell
1268 #size-cells =
1269 ranges = <0 0
1270 reg = <0x4400
1271 interrupts =
1272 resets = <&rc
1273 access-contro
1274 status = "dis
1275
1276 sai3a: audio-
1277 #soun
1278 compa
1279 reg =
1280 clock
1281 clock
1282 dmas
1283 statu
1284 };
1285
1286 sai3b: audio-
1287 #soun
1288 compa
1289 reg =
1290 clock
1291 clock
1292 dmas
1293 statu
1294 };
1295 };
1296
1297 dfsdm: dfsdm@4400d000
1298 compatible =
1299 reg = <0x4400
1300 clocks = <&rc
1301 clock-names =
1302 #address-cell
1303 #size-cells =
1304 access-contro
1305 status = "dis
1306
1307 dfsdm0: filte
1308 compa
1309 #io-c
1310 reg =
1311 inter
1312 dmas
1313 dma-n
1314 statu
1315 };
1316
1317 dfsdm1: filte
1318 compa
1319 #io-c
1320 reg =
1321 inter
1322 dmas
1323 dma-n
1324 statu
1325 };
1326
1327 dfsdm2: filte
1328 compa
1329 #io-c
1330 reg =
1331 inter
1332 dmas
1333 dma-n
1334 statu
1335 };
1336
1337 dfsdm3: filte
1338 compa
1339 #io-c
1340 reg =
1341 inter
1342 dmas
1343 dma-n
1344 statu
1345 };
1346
1347 dfsdm4: filte
1348 compa
1349 #io-c
1350 reg =
1351 inter
1352 dmas
1353 dma-n
1354 statu
1355 };
1356
1357 dfsdm5: filte
1358 compa
1359 #io-c
1360 reg =
1361 inter
1362 dmas
1363 dma-n
1364 statu
1365 };
1366 };
1367
1368 dma1: dma-controller@
1369 compatible =
1370 reg = <0x4800
1371 interrupts =
1372
1373
1374
1375
1376
1377
1378
1379 clocks = <&rc
1380 resets = <&rc
1381 #dma-cells =
1382 st,mem2mem;
1383 dma-requests
1384 access-contro
1385 };
1386
1387 dma2: dma-controller@
1388 compatible =
1389 reg = <0x4800
1390 interrupts =
1391
1392
1393
1394
1395
1396
1397
1398 clocks = <&rc
1399 resets = <&rc
1400 #dma-cells =
1401 st,mem2mem;
1402 dma-requests
1403 access-contro
1404 };
1405
1406 dmamux1: dma-router@4
1407 compatible =
1408 reg = <0x4800
1409 #dma-cells =
1410 dma-requests
1411 dma-masters =
1412 dma-channels
1413 clocks = <&rc
1414 resets = <&rc
1415 access-contro
1416 };
1417
1418 adc: adc@48003000 {
1419 compatible =
1420 reg = <0x4800
1421 interrupts =
1422
1423 clocks = <&rc
1424 clock-names =
1425 interrupt-con
1426 st,syscfg = <
1427 #interrupt-ce
1428 #address-cell
1429 #size-cells =
1430 access-contro
1431 status = "dis
1432
1433 adc1: adc@0 {
1434 compa
1435 #io-c
1436 #addr
1437 #size
1438 reg =
1439 inter
1440 inter
1441 dmas
1442 dma-n
1443 statu
1444 };
1445
1446 adc2: adc@100
1447 compa
1448 #io-c
1449 #addr
1450 #size
1451 reg =
1452 inter
1453 inter
1454 dmas
1455 dma-n
1456 nvmem
1457 nvmem
1458 statu
1459 chann
1460
1461
1462 };
1463 chann
1464
1465
1466 };
1467 };
1468 };
1469
1470 sdmmc3: mmc@48004000
1471 compatible =
1472 arm,primecell
1473 reg = <0x4800
1474 interrupts =
1475 clocks = <&rc
1476 clock-names =
1477 resets = <&rc
1478 cap-sd-highsp
1479 cap-mmc-highs
1480 max-frequency
1481 access-contro
1482 status = "dis
1483 };
1484
1485 usbotg_hs: usb-otg@49
1486 compatible =
1487 reg = <0x4900
1488 clocks = <&rc
1489 clock-names =
1490 resets = <&rc
1491 reset-names =
1492 interrupts =
1493 g-rx-fifo-siz
1494 g-np-tx-fifo-
1495 g-tx-fifo-siz
1496 dr_mode = "ot
1497 otg-rev = <0x
1498 usb33d-supply
1499 access-contro
1500 status = "dis
1501 };
1502
1503 dcmi: dcmi@4c006000 {
1504 compatible =
1505 reg = <0x4c00
1506 interrupts =
1507 resets = <&rc
1508 clocks = <&rc
1509 clock-names =
1510 dmas = <&dmam
1511 dma-names = "
1512 access-contro
1513 status = "dis
1514 };
1515
1516 lptimer2: timer@50021
1517 #address-cell
1518 #size-cells =
1519 compatible =
1520 reg = <0x5002
1521 interrupts-ex
1522 clocks = <&rc
1523 clock-names =
1524 wakeup-source
1525 access-contro
1526 status = "dis
1527
1528 pwm {
1529 compa
1530 #pwm-
1531 statu
1532 };
1533
1534 trigger@1 {
1535 compa
1536 reg =
1537 statu
1538 };
1539
1540 counter {
1541 compa
1542 statu
1543 };
1544 };
1545
1546 lptimer3: timer@50022
1547 #address-cell
1548 #size-cells =
1549 compatible =
1550 reg = <0x5002
1551 interrupts-ex
1552 clocks = <&rc
1553 clock-names =
1554 wakeup-source
1555 access-contro
1556 status = "dis
1557
1558 pwm {
1559 compa
1560 #pwm-
1561 statu
1562 };
1563
1564 trigger@2 {
1565 compa
1566 reg =
1567 statu
1568 };
1569 };
1570
1571 lptimer4: timer@50023
1572 compatible =
1573 reg = <0x5002
1574 interrupts-ex
1575 clocks = <&rc
1576 clock-names =
1577 wakeup-source
1578 access-contro
1579 status = "dis
1580
1581 pwm {
1582 compa
1583 #pwm-
1584 statu
1585 };
1586 };
1587
1588 lptimer5: timer@50024
1589 compatible =
1590 reg = <0x5002
1591 interrupts-ex
1592 clocks = <&rc
1593 clock-names =
1594 wakeup-source
1595 access-contro
1596 status = "dis
1597
1598 pwm {
1599 compa
1600 #pwm-
1601 statu
1602 };
1603 };
1604
1605 vrefbuf: vrefbuf@5002
1606 compatible =
1607 reg = <0x5002
1608 regulator-min
1609 regulator-max
1610 clocks = <&rc
1611 access-contro
1612 status = "dis
1613 };
1614
1615 sai4: sai@50027000 {
1616 compatible =
1617 #address-cell
1618 #size-cells =
1619 ranges = <0 0
1620 reg = <0x5002
1621 interrupts =
1622 resets = <&rc
1623 access-contro
1624 status = "dis
1625
1626 sai4a: audio-
1627 #soun
1628 compa
1629 reg =
1630 clock
1631 clock
1632 dmas
1633 statu
1634 };
1635
1636 sai4b: audio-
1637 #soun
1638 compa
1639 reg =
1640 clock
1641 clock
1642 dmas
1643 statu
1644 };
1645 };
1646
1647 hash1: hash@54002000
1648 compatible =
1649 reg = <0x5400
1650 interrupts =
1651 clocks = <&rc
1652 resets = <&rc
1653 dmas = <&mdma
1654 dma-names = "
1655 dma-maxburst
1656 access-contro
1657 status = "dis
1658 };
1659
1660 rng1: rng@54003000 {
1661 compatible =
1662 reg = <0x5400
1663 clocks = <&rc
1664 resets = <&rc
1665 access-contro
1666 status = "dis
1667 };
1668
1669 fmc: memory-controlle
1670 #address-cell
1671 #size-cells =
1672 compatible =
1673 reg = <0x5800
1674 clocks = <&rc
1675 resets = <&rc
1676 access-contro
1677 status = "dis
1678
1679 ranges = <0 0
1680 <1 0
1681 <2 0
1682 <3 0
1683 <4 0
1684
1685 nand-controll
1686 #addr
1687 #size
1688 compa
1689 reg =
1690
1691
1692
1693
1694
1695 inter
1696 dmas
1697
1698
1699 dma-n
1700 statu
1701 };
1702 };
1703
1704 qspi: spi@58003000 {
1705 compatible =
1706 reg = <0x5800
1707 reg-names = "
1708 interrupts =
1709 dmas = <&mdma
1710 <&mdma
1711 dma-names = "
1712 clocks = <&rc
1713 resets = <&rc
1714 #address-cell
1715 #size-cells =
1716 access-contro
1717 status = "dis
1718 };
1719
1720 ethernet0: ethernet@5
1721 compatible =
1722 reg = <0x5800
1723 reg-names = "
1724 interrupts-ex
1725 interrupt-nam
1726 clock-names =
1727
1728
1729
1730
1731
1732 clocks = <&rc
1733 <&rc
1734 <&rc
1735 <&rc
1736 <&rc
1737 <&rc
1738 st,syscon = <
1739 snps,mixed-bu
1740 snps,pbl = <2
1741 snps,en-tx-lp
1742 snps,axi-conf
1743 snps,tso;
1744 access-contro
1745 status = "dis
1746
1747 stmmac_axi_co
1748 snps,
1749 snps,
1750 snps,
1751 };
1752 };
1753
1754 usart1: serial@5c0000
1755 compatible =
1756 reg = <0x5c00
1757 interrupts-ex
1758 clocks = <&rc
1759 wakeup-source
1760 access-contro
1761 status = "dis
1762 };
1763
1764 spi6: spi@5c001000 {
1765 #address-cell
1766 #size-cells =
1767 compatible =
1768 reg = <0x5c00
1769 interrupts =
1770 clocks = <&rc
1771 resets = <&rc
1772 dmas = <&mdma
1773 <&mdma
1774 access-contro
1775 dma-names = "
1776 status = "dis
1777 };
1778
1779 i2c4: i2c@5c002000 {
1780 compatible =
1781 reg = <0x5c00
1782 interrupt-nam
1783 interrupts =
1784
1785 clocks = <&rc
1786 resets = <&rc
1787 #address-cell
1788 #size-cells =
1789 st,syscfg-fmp
1790 wakeup-source
1791 i2c-analog-fi
1792 access-contro
1793 status = "dis
1794 };
1795
1796 i2c6: i2c@5c009000 {
1797 compatible =
1798 reg = <0x5c00
1799 interrupt-nam
1800 interrupts =
1801
1802 clocks = <&rc
1803 resets = <&rc
1804 #address-cell
1805 #size-cells =
1806 st,syscfg-fmp
1807 wakeup-source
1808 i2c-analog-fi
1809 access-contro
1810 status = "dis
1811 };
1812 };
1813
1814 tamp: tamp@5c00a000 {
1815 compatible = "st,stm3
1816 reg = <0x5c00a000 0x4
1817 };
1818
1819 /*
1820 * Break node order to solve
1821 * pinctrl and exti.
1822 */
1823 pinctrl: pinctrl@50002000 {
1824 #address-cells = <1>;
1825 #size-cells = <1>;
1826 compatible = "st,stm3
1827 ranges = <0 0x5000200
1828 interrupt-parent = <&
1829 st,syscfg = <&exti 0x
1830
1831 gpioa: gpio@50002000
1832 gpio-controll
1833 #gpio-cells =
1834 interrupt-con
1835 #interrupt-ce
1836 reg = <0x0 0x
1837 clocks = <&rc
1838 st,bank-name
1839 status = "dis
1840 };
1841
1842 gpiob: gpio@50003000
1843 gpio-controll
1844 #gpio-cells =
1845 interrupt-con
1846 #interrupt-ce
1847 reg = <0x1000
1848 clocks = <&rc
1849 st,bank-name
1850 status = "dis
1851 };
1852
1853 gpioc: gpio@50004000
1854 gpio-controll
1855 #gpio-cells =
1856 interrupt-con
1857 #interrupt-ce
1858 reg = <0x2000
1859 clocks = <&rc
1860 st,bank-name
1861 status = "dis
1862 };
1863
1864 gpiod: gpio@50005000
1865 gpio-controll
1866 #gpio-cells =
1867 interrupt-con
1868 #interrupt-ce
1869 reg = <0x3000
1870 clocks = <&rc
1871 st,bank-name
1872 status = "dis
1873 };
1874
1875 gpioe: gpio@50006000
1876 gpio-controll
1877 #gpio-cells =
1878 interrupt-con
1879 #interrupt-ce
1880 reg = <0x4000
1881 clocks = <&rc
1882 st,bank-name
1883 status = "dis
1884 };
1885
1886 gpiof: gpio@50007000
1887 gpio-controll
1888 #gpio-cells =
1889 interrupt-con
1890 #interrupt-ce
1891 reg = <0x5000
1892 clocks = <&rc
1893 st,bank-name
1894 status = "dis
1895 };
1896
1897 gpiog: gpio@50008000
1898 gpio-controll
1899 #gpio-cells =
1900 interrupt-con
1901 #interrupt-ce
1902 reg = <0x6000
1903 clocks = <&rc
1904 st,bank-name
1905 status = "dis
1906 };
1907
1908 gpioh: gpio@50009000
1909 gpio-controll
1910 #gpio-cells =
1911 interrupt-con
1912 #interrupt-ce
1913 reg = <0x7000
1914 clocks = <&rc
1915 st,bank-name
1916 status = "dis
1917 };
1918
1919 gpioi: gpio@5000a000
1920 gpio-controll
1921 #gpio-cells =
1922 interrupt-con
1923 #interrupt-ce
1924 reg = <0x8000
1925 clocks = <&rc
1926 st,bank-name
1927 status = "dis
1928 };
1929
1930 gpioj: gpio@5000b000
1931 gpio-controll
1932 #gpio-cells =
1933 interrupt-con
1934 #interrupt-ce
1935 reg = <0x9000
1936 clocks = <&rc
1937 st,bank-name
1938 status = "dis
1939 };
1940
1941 gpiok: gpio@5000c000
1942 gpio-controll
1943 #gpio-cells =
1944 interrupt-con
1945 #interrupt-ce
1946 reg = <0xa000
1947 clocks = <&rc
1948 st,bank-name
1949 status = "dis
1950 };
1951 };
1952
1953 pinctrl_z: pinctrl@54004000 {
1954 #address-cells = <1>;
1955 #size-cells = <1>;
1956 compatible = "st,stm3
1957 ranges = <0 0x5400400
1958 interrupt-parent = <&
1959 st,syscfg = <&exti 0x
1960
1961 gpioz: gpio@54004000
1962 gpio-controll
1963 #gpio-cells =
1964 interrupt-con
1965 #interrupt-ce
1966 reg = <0 0x40
1967 clocks = <&rc
1968 st,bank-name
1969 st,bank-iopor
1970 status = "dis
1971 };
1972 };
1973 };
1974
1975 mlahb: ahb {
1976 compatible = "st,mlahb", "sim
1977 #address-cells = <1>;
1978 #size-cells = <1>;
1979 ranges;
1980 dma-ranges = <0x00000000 0x38
1981 <0x10000000 0x10
1982 <0x30000000 0x30
1983
1984 m4_rproc: m4@10000000 {
1985 compatible = "st,stm3
1986 reg = <0x10000000 0x4
1987 <0x30000000 0x4
1988 <0x38000000 0x1
1989 resets = <&rcc MCU_R>
1990 reset-names = "mcu_rs
1991 st,syscfg-holdboot =
1992 st,syscfg-pdds = <&pw
1993 st,syscfg-rsc-tbl = <
1994 st,syscfg-m4-state =
1995 status = "disabled";
1996 };
1997 };
1998 };
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