1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada
4 *
5 * Sebastian Hesselbarth <sebastian.hesselbarth
6 *
7 * based on GPL'ed 2.6 kernel sources
8 * (c) Marvell International Ltd.
9 */
10
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm
13
14 / {
15 model = "Marvell Armada 1500-mini (BG2
16 compatible = "marvell,berlin2cd", "mar
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu: cpu@0 {
30 compatible = "arm,cort
31 device_type = "cpu";
32 next-level-cache = <&l
33 reg = <0>;
34
35 clocks = <&chip_clk CL
36 clock-latency = <10000
37 operating-points = <
38 /* kHz uV *
39 800000 120000
40 600000 120000
41 >;
42 };
43 };
44
45 pmu {
46 compatible = "arm,cortex-a9-pm
47 interrupt-parent = <&gic>;
48 interrupts = <GIC_SPI 30 IRQ_T
49 };
50
51 refclk: oscillator {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <25000000>;
55 };
56
57 soc@f7000000 {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 interrupt-parent = <&gic>;
62
63 ranges = <0 0xf7000000 0x10000
64
65 sdhci0: mmc@ab0000 {
66 compatible = "mrvl,pxa
67 reg = <0xab0000 0x200>
68 clocks = <&chip_clk CL
69 clock-names = "io", "c
70 interrupts = <GIC_SPI
71 status = "disabled";
72 };
73
74 l2: cache-controller@ac0000 {
75 compatible = "arm,pl31
76 reg = <0xac0000 0x1000
77 cache-unified;
78 cache-level = <2>;
79 };
80
81 snoop-control-unit@ad0000 {
82 compatible = "arm,cort
83 reg = <0xad0000 0x100>
84 };
85
86 gic: interrupt-controller@ad10
87 compatible = "arm,cort
88 reg = <0xad1000 0x1000
89 interrupt-controller;
90 #interrupt-cells = <3>
91 };
92
93 global-timer@ad0200 {
94 compatible = "arm,cort
95 reg = <0xad0200 0x20>;
96 interrupts = <GIC_PPI
97 clocks = <&chip_clk CL
98 };
99
100 local-timer@ad0600 {
101 compatible = "arm,cort
102 reg = <0xad0600 0x20>;
103 interrupts = <GIC_PPI
104 clocks = <&chip_clk CL
105 };
106
107 local-wdt@ad0620 {
108 compatible = "arm,cort
109 reg = <0xad0620 0x20>;
110 interrupts = <GIC_PPI
111 clocks = <&chip_clk CL
112 };
113
114 usb_phy0: usb-phy@b74000 {
115 compatible = "marvell,
116 reg = <0xb74000 0x128>
117 #phy-cells = <0>;
118 resets = <&chip_rst 0x
119 status = "disabled";
120 };
121
122 usb_phy1: usb-phy@b78000 {
123 compatible = "marvell,
124 reg = <0xb78000 0x128>
125 #phy-cells = <0>;
126 resets = <&chip_rst 0x
127 status = "disabled";
128 };
129
130 eth1: ethernet@b90000 {
131 compatible = "marvell,
132 reg = <0xb90000 0x1000
133 clocks = <&chip_clk CL
134 interrupts = <GIC_SPI
135 /* set by bootloader *
136 local-mac-address = [0
137 #address-cells = <1>;
138 #size-cells = <0>;
139 phy-connection-type =
140 phy-handle = <ðphy1
141 status = "disabled";
142
143 ethphy1: ethernet-phy@
144 reg = <0>;
145 };
146 };
147
148 eth0: ethernet@e50000 {
149 compatible = "marvell,
150 reg = <0xe50000 0x1000
151 clocks = <&chip_clk CL
152 interrupts = <GIC_SPI
153 /* set by bootloader *
154 local-mac-address = [0
155 #address-cells = <1>;
156 #size-cells = <0>;
157 phy-connection-type =
158 phy-handle = <ðphy0
159 status = "disabled";
160
161 ethphy0: ethernet-phy@
162 reg = <0>;
163 };
164 };
165
166 apb@e80000 {
167 compatible = "simple-b
168 #address-cells = <1>;
169 #size-cells = <1>;
170
171 ranges = <0 0xe80000 0
172 interrupt-parent = <&a
173
174 gpio0: gpio@400 {
175 compatible = "
176 reg = <0x0400
177 #address-cells
178 #size-cells =
179
180 porta: gpio-po
181 compat
182 gpio-c
183 #gpio-
184 ngpios
185 reg =
186 interr
187 #inter
188 interr
189 };
190 };
191
192 gpio1: gpio@800 {
193 compatible = "
194 reg = <0x0800
195 #address-cells
196 #size-cells =
197
198 portb: gpio-po
199 compat
200 gpio-c
201 #gpio-
202 ngpios
203 reg =
204 interr
205 #inter
206 interr
207 };
208 };
209
210 gpio2: gpio@c00 {
211 compatible = "
212 reg = <0x0c00
213 #address-cells
214 #size-cells =
215
216 portc: gpio-po
217 compat
218 gpio-c
219 #gpio-
220 ngpios
221 reg =
222 interr
223 #inter
224 interr
225 };
226 };
227
228 gpio3: gpio@1000 {
229 compatible = "
230 reg = <0x1000
231 #address-cells
232 #size-cells =
233
234 portd: gpio-po
235 compat
236 gpio-c
237 #gpio-
238 ngpios
239 reg =
240 interr
241 #inter
242 interr
243 };
244 };
245
246 i2c0: i2c@1400 {
247 compatible = "
248 #address-cells
249 #size-cells =
250 reg = <0x1400
251 interrupts = <
252 clocks = <&chi
253 status = "disa
254 };
255
256 i2c1: i2c@1800 {
257 compatible = "
258 #address-cells
259 #size-cells =
260 reg = <0x1800
261 interrupts = <
262 clocks = <&chi
263 status = "disa
264 };
265
266 spi0: spi@1c00 {
267 compatible = "
268 #address-cells
269 #size-cells =
270 reg = <0x1c00
271 interrupts = <
272 clocks = <&chi
273 status = "disa
274 };
275
276 wdt4: watchdog@2000 {
277 compatible = "
278 reg = <0x2000
279 clocks = <&chi
280 interrupts = <
281 status = "disa
282 };
283
284 wdt5: watchdog@2400 {
285 compatible = "
286 reg = <0x2400
287 clocks = <&chi
288 interrupts = <
289 status = "disa
290 };
291
292 wdt6: watchdog@2800 {
293 compatible = "
294 reg = <0x2800
295 clocks = <&chi
296 interrupts = <
297 status = "disa
298 };
299
300 timer0: timer@2c00 {
301 compatible = "
302 reg = <0x2c00
303 interrupts = <
304 clocks = <&chi
305 clock-names =
306 status = "okay
307 };
308
309 timer1: timer@2c14 {
310 compatible = "
311 reg = <0x2c14
312 interrupts = <
313 clocks = <&chi
314 clock-names =
315 status = "okay
316 };
317
318 timer2: timer@2c28 {
319 compatible = "
320 reg = <0x2c28
321 interrupts = <
322 clocks = <&chi
323 clock-names =
324 status = "disa
325 };
326
327 timer3: timer@2c3c {
328 compatible = "
329 reg = <0x2c3c
330 interrupts = <
331 clocks = <&chi
332 clock-names =
333 status = "disa
334 };
335
336 timer4: timer@2c50 {
337 compatible = "
338 reg = <0x2c50
339 interrupts = <
340 clocks = <&chi
341 clock-names =
342 status = "disa
343 };
344
345 timer5: timer@2c64 {
346 compatible = "
347 reg = <0x2c64
348 interrupts = <
349 clocks = <&chi
350 clock-names =
351 status = "disa
352 };
353
354 timer6: timer@2c78 {
355 compatible = "
356 reg = <0x2c78
357 interrupts = <
358 clocks = <&chi
359 clock-names =
360 status = "disa
361 };
362
363 timer7: timer@2c8c {
364 compatible = "
365 reg = <0x2c8c
366 interrupts = <
367 clocks = <&chi
368 clock-names =
369 status = "disa
370 };
371
372 aic: interrupt-control
373 compatible = "
374 reg = <0x3000
375 interrupt-cont
376 #interrupt-cel
377 interrupt-pare
378 interrupts = <
379 };
380 };
381
382 chip: chip-control@ea0000 {
383 compatible = "simple-m
384 reg = <0xea0000 0x400>
385
386 chip_clk: clock {
387 compatible = "
388 #clock-cells =
389 clocks = <&ref
390 clock-names =
391 };
392
393 soc_pinctrl: pin-contr
394 compatible = "
395
396 uart0_pmux: ua
397 groups
398 functi
399 };
400 };
401
402 chip_rst: reset {
403 compatible = "
404 #reset-cells =
405 };
406 };
407
408 usb0: usb@ed0000 {
409 compatible = "chipidea
410 reg = <0xed0000 0x200>
411 interrupts = <GIC_SPI
412 clocks = <&chip_clk CL
413 phys = <&usb_phy0>;
414 phy-names = "usb-phy";
415 status = "disabled";
416 };
417
418 usb1: usb@ee0000 {
419 compatible = "chipidea
420 reg = <0xee0000 0x200>
421 interrupts = <GIC_SPI
422 clocks = <&chip_clk CL
423 phys = <&usb_phy1>;
424 phy-names = "usb-phy";
425 status = "disabled";
426 };
427
428 pwm: pwm@f20000 {
429 compatible = "marvell,
430 reg = <0xf20000 0x40>;
431 clocks = <&chip_clk CL
432 #pwm-cells = <3>;
433 };
434
435 apb@fc0000 {
436 compatible = "simple-b
437 #address-cells = <1>;
438 #size-cells = <1>;
439
440 ranges = <0 0xfc0000 0
441 interrupt-parent = <&s
442
443 wdt0: watchdog@1000 {
444 compatible = "
445 reg = <0x1000
446 clocks = <&ref
447 interrupts = <
448 };
449
450 wdt1: watchdog@2000 {
451 compatible = "
452 reg = <0x2000
453 clocks = <&ref
454 interrupts = <
455 status = "disa
456 };
457
458 wdt2: watchdog@3000 {
459 compatible = "
460 reg = <0x3000
461 clocks = <&ref
462 interrupts = <
463 status = "disa
464 };
465
466 sm_gpio1: gpio@5000 {
467 compatible = "
468 reg = <0x5000
469 #address-cells
470 #size-cells =
471
472 portf: gpio-po
473 compat
474 gpio-c
475 #gpio-
476 ngpios
477 reg =
478 };
479 };
480
481 spi1: spi@6000 {
482 compatible = "
483 #address-cells
484 #size-cells =
485 reg = <0x6000
486 clocks = <&ref
487 interrupts = <
488 status = "disa
489 };
490
491 i2c2: i2c@7000 {
492 compatible = "
493 #address-cells
494 #size-cells =
495 reg = <0x7000
496 interrupts = <
497 clocks = <&ref
498 status = "disa
499 };
500
501 i2c3: i2c@8000 {
502 compatible = "
503 #address-cells
504 #size-cells =
505 reg = <0x8000
506 interrupts = <
507 clocks = <&ref
508 status = "disa
509 };
510
511 sm_gpio0: gpio@c000 {
512 compatible = "
513 reg = <0xc000
514 #address-cells
515 #size-cells =
516
517 porte: gpio-po
518 compat
519 gpio-c
520 #gpio-
521 ngpios
522 reg =
523 };
524 };
525
526 uart0: serial@9000 {
527 compatible = "
528 reg = <0x9000
529 reg-shift = <2
530 reg-io-width =
531 interrupts = <
532 clocks = <&ref
533 pinctrl-0 = <&
534 pinctrl-names
535 status = "disa
536 };
537
538 uart1: serial@a000 {
539 compatible = "
540 reg = <0xa000
541 reg-shift = <2
542 reg-io-width =
543 interrupts = <
544 clocks = <&ref
545 status = "disa
546 };
547
548 uart2: serial@b000 {
549 compatible = "
550 reg = <0xb000
551 reg-shift = <2
552 reg-io-width =
553 interrupts = <
554 clocks = <&ref
555 status = "disa
556 };
557
558 sysctrl: system-contro
559 compatible = "
560 reg = <0xd000
561
562 sys_pinctrl: p
563 compat
564 };
565
566 adc: adc {
567 compat
568 interr
569 interr
570 };
571 };
572
573 sic: interrupt-control
574 compatible = "
575 reg = <0xe000
576 interrupt-cont
577 #interrupt-cel
578 interrupt-pare
579 interrupts = <
580 };
581 };
582 };
583 };
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