1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2014 Antoine Ténart <antoine.
4 */
5
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm
8
9 / {
10 model = "Marvell Armada 1500 pro (BG2-
11 compatible = "marvell,berlin2q", "marv
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 aliases {
16 serial0 = &uart0;
17 serial1 = &uart1;
18 };
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berli
24
25 cpu0: cpu@0 {
26 compatible = "arm,cort
27 device_type = "cpu";
28 next-level-cache = <&l
29 reg = <0>;
30
31 clocks = <&chip_clk CL
32 clock-latency = <10000
33 /* Can be modified by
34 operating-points = <
35 /* kHz uV *
36 1200000 120000
37 1000000 120000
38 800000 120000
39 600000 120000
40 >;
41 };
42
43 cpu1: cpu@1 {
44 compatible = "arm,cort
45 device_type = "cpu";
46 next-level-cache = <&l
47 reg = <1>;
48
49 clocks = <&chip_clk CL
50 clock-latency = <10000
51 /* Can be modified by
52 operating-points = <
53 /* kHz uV *
54 1200000 120000
55 1000000 120000
56 800000 120000
57 600000 120000
58 >;
59 };
60
61 cpu2: cpu@2 {
62 compatible = "arm,cort
63 device_type = "cpu";
64 next-level-cache = <&l
65 reg = <2>;
66
67 clocks = <&chip_clk CL
68 clock-latency = <10000
69 /* Can be modified by
70 operating-points = <
71 /* kHz uV *
72 1200000 120000
73 1000000 120000
74 800000 120000
75 600000 120000
76 >;
77 };
78
79 cpu3: cpu@3 {
80 compatible = "arm,cort
81 device_type = "cpu";
82 next-level-cache = <&l
83 reg = <3>;
84
85 clocks = <&chip_clk CL
86 clock-latency = <10000
87 /* Can be modified by
88 operating-points = <
89 /* kHz uV *
90 1200000 120000
91 1000000 120000
92 800000 120000
93 600000 120000
94 >;
95 };
96 };
97
98 pmu {
99 compatible = "arm,cortex-a9-pm
100 interrupt-parent = <&gic>;
101 interrupts = <GIC_SPI 30 IRQ_T
102 <GIC_SPI 31 IRQ_T
103 <GIC_SPI 40 IRQ_T
104 <GIC_SPI 41 IRQ_T
105 interrupt-affinity = <&cpu0>,
106 <&cpu1>,
107 <&cpu2>,
108 <&cpu3>;
109 };
110
111 refclk: oscillator {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <25000000>;
115 };
116
117 soc@f7000000 {
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
121
122 ranges = <0 0xf7000000 0x10000
123 interrupt-parent = <&gic>;
124
125 sdhci0: mmc@ab0000 {
126 compatible = "mrvl,pxa
127 reg = <0xab0000 0x200>
128 clocks = <&chip_clk CL
129 clock-names = "io", "c
130 interrupts = <GIC_SPI
131 status = "disabled";
132 };
133
134 sdhci1: mmc@ab0800 {
135 compatible = "mrvl,pxa
136 reg = <0xab0800 0x200>
137 clocks = <&chip_clk CL
138 clock-names = "io", "c
139 interrupts = <GIC_SPI
140 status = "disabled";
141 };
142
143 sdhci2: mmc@ab1000 {
144 compatible = "mrvl,pxa
145 reg = <0xab1000 0x200>
146 interrupts = <GIC_SPI
147 clocks = <&chip_clk CL
148 clock-names = "io", "c
149 status = "disabled";
150 };
151
152 l2: cache-controller@ac0000 {
153 compatible = "arm,pl31
154 reg = <0xac0000 0x1000
155 cache-unified;
156 cache-level = <2>;
157 arm,data-latency = <2
158 arm,tag-latency = <2 2
159 };
160
161 scu: snoop-control-unit@ad0000
162 compatible = "arm,cort
163 reg = <0xad0000 0x58>;
164 };
165
166 local-timer@ad0600 {
167 compatible = "arm,cort
168 reg = <0xad0600 0x20>;
169 clocks = <&chip_clk CL
170 interrupts = <GIC_PPI
171 };
172
173 gic: interrupt-controller@ad10
174 compatible = "arm,cort
175 reg = <0xad1000 0x1000
176 interrupt-controller;
177 #interrupt-cells = <3>
178 };
179
180 usb_phy2: phy@a2f400 {
181 compatible = "marvell,
182 reg = <0xa2f400 0x128>
183 #phy-cells = <0>;
184 resets = <&chip_rst 0x
185 status = "disabled";
186 };
187
188 usb2: usb@a30000 {
189 compatible = "chipidea
190 reg = <0xa30000 0x1000
191 interrupts = <GIC_SPI
192 clocks = <&chip_clk CL
193 phys = <&usb_phy2>;
194 phy-names = "usb-phy";
195 status = "disabled";
196 };
197
198 usb_phy0: phy@b74000 {
199 compatible = "marvell,
200 reg = <0xb74000 0x128>
201 #phy-cells = <0>;
202 resets = <&chip_rst 0x
203 status = "disabled";
204 };
205
206 usb_phy1: phy@b78000 {
207 compatible = "marvell,
208 reg = <0xb78000 0x128>
209 #phy-cells = <0>;
210 resets = <&chip_rst 0x
211 status = "disabled";
212 };
213
214 eth0: ethernet@b90000 {
215 compatible = "marvell,
216 reg = <0xb90000 0x1000
217 clocks = <&chip_clk CL
218 interrupts = <GIC_SPI
219 /* set by bootloader *
220 local-mac-address = [0
221 #address-cells = <1>;
222 #size-cells = <0>;
223 phy-connection-type =
224 phy-handle = <ðphy0
225 status = "disabled";
226
227 ethphy0: ethernet-phy@
228 reg = <0>;
229 };
230 };
231
232 cpu-ctrl@dd0000 {
233 compatible = "marvell,
234 reg = <0xdd0000 0x1000
235 };
236
237 apb@e80000 {
238 compatible = "simple-b
239 #address-cells = <1>;
240 #size-cells = <1>;
241
242 ranges = <0 0xe80000 0
243 interrupt-parent = <&a
244
245 gpio0: gpio@400 {
246 compatible = "
247 reg = <0x0400
248 #address-cells
249 #size-cells =
250
251 porta: gpio-po
252 compat
253 gpio-c
254 #gpio-
255 ngpios
256 reg =
257 interr
258 #inter
259 interr
260 };
261 };
262
263 gpio1: gpio@800 {
264 compatible = "
265 reg = <0x0800
266 #address-cells
267 #size-cells =
268
269 portb: gpio-po
270 compat
271 gpio-c
272 #gpio-
273 ngpios
274 reg =
275 interr
276 #inter
277 interr
278 };
279 };
280
281 gpio2: gpio@c00 {
282 compatible = "
283 reg = <0x0c00
284 #address-cells
285 #size-cells =
286
287 portc: gpio-po
288 compat
289 gpio-c
290 #gpio-
291 ngpios
292 reg =
293 interr
294 #inter
295 interr
296 };
297 };
298
299 gpio3: gpio@1000 {
300 compatible = "
301 reg = <0x1000
302 #address-cells
303 #size-cells =
304
305 portd: gpio-po
306 compat
307 gpio-c
308 #gpio-
309 ngpios
310 reg =
311 interr
312 #inter
313 interr
314 };
315 };
316
317 i2c0: i2c@1400 {
318 compatible = "
319 #address-cells
320 #size-cells =
321 reg = <0x1400
322 interrupts = <
323 clocks = <&chi
324 pinctrl-0 = <&
325 pinctrl-names
326 status = "disa
327 };
328
329 i2c1: i2c@1800 {
330 compatible = "
331 #address-cells
332 #size-cells =
333 reg = <0x1800
334 interrupts = <
335 clocks = <&chi
336 pinctrl-0 = <&
337 pinctrl-names
338 status = "disa
339 };
340
341 timer0: timer@2c00 {
342 compatible = "
343 reg = <0x2c00
344 clocks = <&chi
345 clock-names =
346 interrupts = <
347 };
348
349 timer1: timer@2c14 {
350 compatible = "
351 reg = <0x2c14
352 clocks = <&chi
353 clock-names =
354 };
355
356 timer2: timer@2c28 {
357 compatible = "
358 reg = <0x2c28
359 clocks = <&chi
360 clock-names =
361 status = "disa
362 };
363
364 timer3: timer@2c3c {
365 compatible = "
366 reg = <0x2c3c
367 clocks = <&chi
368 clock-names =
369 status = "disa
370 };
371
372 timer4: timer@2c50 {
373 compatible = "
374 reg = <0x2c50
375 clocks = <&chi
376 clock-names =
377 status = "disa
378 };
379
380 timer5: timer@2c64 {
381 compatible = "
382 reg = <0x2c64
383 clocks = <&chi
384 clock-names =
385 status = "disa
386 };
387
388 timer6: timer@2c78 {
389 compatible = "
390 reg = <0x2c78
391 clocks = <&chi
392 clock-names =
393 status = "disa
394 };
395
396 timer7: timer@2c8c {
397 compatible = "
398 reg = <0x2c8c
399 clocks = <&chi
400 clock-names =
401 status = "disa
402 };
403
404 aic: interrupt-control
405 compatible = "
406 reg = <0x3800
407 interrupt-cont
408 #interrupt-cel
409 interrupt-pare
410 interrupts = <
411 };
412 };
413
414 chip: chip-control@ea0000 {
415 compatible = "simple-m
416 reg = <0xea0000 0x400>
417
418 chip_clk: clock {
419 compatible = "
420 #clock-cells =
421 clocks = <&ref
422 clock-names =
423 };
424
425 soc_pinctrl: pin-contr
426 compatible = "
427
428 sd1_pmux: sd1-
429 groups
430 functi
431 };
432
433 twsi0_pmux: tw
434 groups
435 functi
436 };
437
438 twsi1_pmux: tw
439 groups
440 functi
441 };
442 };
443
444 chip_rst: reset {
445 compatible = "
446 #reset-cells =
447 };
448 };
449
450 ahci: sata@e90000 {
451 compatible = "marvell,
452 reg = <0xe90000 0x1000
453 interrupts = <GIC_SPI
454 clocks = <&chip_clk CL
455 #address-cells = <1>;
456 #size-cells = <0>;
457
458 sata0: sata-port@0 {
459 reg = <0>;
460 phys = <&sata_
461 status = "disa
462 };
463
464 sata1: sata-port@1 {
465 reg = <1>;
466 phys = <&sata_
467 status = "disa
468 };
469 };
470
471 sata_phy: phy@e900a0 {
472 compatible = "marvell,
473 reg = <0xe900a0 0x200>
474 clocks = <&chip_clk CL
475 #address-cells = <1>;
476 #size-cells = <0>;
477 #phy-cells = <1>;
478 status = "disabled";
479
480 sata-phy@0 {
481 reg = <0>;
482 };
483
484 sata-phy@1 {
485 reg = <1>;
486 };
487 };
488
489 usb0: usb@ed0000 {
490 compatible = "chipidea
491 reg = <0xed0000 0x1000
492 interrupts = <GIC_SPI
493 clocks = <&chip_clk CL
494 phys = <&usb_phy0>;
495 phy-names = "usb-phy";
496 status = "disabled";
497 };
498
499 usb1: usb@ee0000 {
500 compatible = "chipidea
501 reg = <0xee0000 0x1000
502 interrupts = <GIC_SPI
503 clocks = <&chip_clk CL
504 phys = <&usb_phy1>;
505 phy-names = "usb-phy";
506 status = "disabled";
507 };
508
509 pwm: pwm@f20000 {
510 compatible = "marvell,
511 reg = <0xf20000 0x40>;
512 clocks = <&chip_clk CL
513 #pwm-cells = <3>;
514 };
515
516 apb@fc0000 {
517 compatible = "simple-b
518 #address-cells = <1>;
519 #size-cells = <1>;
520
521 ranges = <0 0xfc0000 0
522 interrupt-parent = <&s
523
524 wdt0: watchdog@1000 {
525 compatible = "
526 reg = <0x1000
527 clocks = <&ref
528 interrupts = <
529 };
530
531 wdt1: watchdog@2000 {
532 compatible = "
533 reg = <0x2000
534 clocks = <&ref
535 interrupts = <
536 };
537
538 wdt2: watchdog@3000 {
539 compatible = "
540 reg = <0x3000
541 clocks = <&ref
542 interrupts = <
543 };
544
545 sm_gpio1: gpio@5000 {
546 compatible = "
547 reg = <0x5000
548 #address-cells
549 #size-cells =
550
551 portf: gpio-po
552 compat
553 gpio-c
554 #gpio-
555 ngpios
556 reg =
557 };
558 };
559
560 i2c2: i2c@7000 {
561 compatible = "
562 #address-cells
563 #size-cells =
564 reg = <0x7000
565 interrupts = <
566 clocks = <&ref
567 pinctrl-0 = <&
568 pinctrl-names
569 status = "disa
570 };
571
572 i2c3: i2c@8000 {
573 compatible = "
574 #address-cells
575 #size-cells =
576 reg = <0x8000
577 interrupts = <
578 clocks = <&ref
579 pinctrl-0 = <&
580 pinctrl-names
581 status = "disa
582 };
583
584 uart0: serial@9000 {
585 compatible = "
586 reg = <0x9000
587 interrupts = <
588 clocks = <&ref
589 reg-shift = <2
590 pinctrl-0 = <&
591 pinctrl-names
592 status = "disa
593 };
594
595 uart1: serial@a000 {
596 compatible = "
597 reg = <0xa000
598 interrupts = <
599 clocks = <&ref
600 reg-shift = <2
601 pinctrl-0 = <&
602 pinctrl-names
603 status = "disa
604 };
605
606 sm_gpio0: gpio@c000 {
607 compatible = "
608 reg = <0xc000
609 #address-cells
610 #size-cells =
611
612 porte: gpio-po
613 compat
614 gpio-c
615 #gpio-
616 ngpios
617 reg =
618 };
619 };
620
621 sysctrl: pin-controlle
622 compatible = "
623 reg = <0xd000
624
625 sys_pinctrl: p
626 compat
627
628 uart0_
629
630
631 };
632
633 uart1_
634
635
636 };
637
638 twsi2_
639
640
641 };
642
643 twsi3_
644
645
646 };
647 };
648
649 adc: adc {
650 compat
651 interr
652 interr
653 };
654 };
655
656 sic: interrupt-control
657 compatible = "
658 reg = <0xe000
659 interrupt-cont
660 #interrupt-cel
661 interrupt-pare
662 interrupts = <
663 };
664 };
665 };
666 };
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