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TOMOYO Linux Cross Reference
Linux/arch/arm/crypto/sha1-armv4-large.S

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Diff markup

Differences between /arch/arm/crypto/sha1-armv4-large.S (Version linux-6.12-rc7) and /arch/sparc64/crypto/sha1-armv4-large.S (Version linux-6.1.116)


  1 #define __ARM_ARCH__ __LINUX_ARM_ARCH__           
  2 @ SPDX-License-Identifier: GPL-2.0                
  3                                                   
  4 @ This code is taken from the OpenSSL project     
  5 @ has relicensed it under the GPLv2. Therefore    
  6 @ you can redistribute it and/or modify it und    
  7 @ Public License version 2 as published by the    
  8 @                                                 
  9 @ The original headers, including the original    
 10 @ included below for completeness.                
 11                                                   
 12 @ ============================================    
 13 @ Written by Andy Polyakov <appro@fy.chalmers.s    
 14 @ project. The module is, however, dual licens    
 15 @ CRYPTOGAMS licenses depending on where you o    
 16 @ details see https://www.openssl.org/~appro/c    
 17 @ ============================================    
 18                                                   
 19 @ sha1_block procedure for ARMv4.                 
 20 @                                                 
 21 @ January 2007.                                   
 22                                                   
 23 @ Size/performance trade-off                      
 24 @ ============================================    
 25 @ impl          size in bytes   comp cycles[*]    
 26 @ ============================================    
 27 @ thumb         304             3212              
 28 @ armv4-small   392/+29%        1958/+64%         
 29 @ armv4-compact 740/+89%        1552/+26%         
 30 @ armv4-large   1420/+92%       1307/+19%         
 31 @ full unroll   ~5100/+260%     ~1260/+4%         
 32 @ ============================================    
 33 @ thumb         = same as 'small' but in Thumb    
 34 @                 with recurring code in two p    
 35 @ small         = detached Xload/update, loops    
 36 @ compact       = detached Xload/update, 5x un    
 37 @ large         = interleaved Xload/update, 5x    
 38 @ full unroll   = interleaved Xload/update, fu    
 39 @                                                 
 40 @ [*]   Manually counted instructions in "gran    
 41 @       performance is affected by prologue an    
 42 @       i-cache availability, branch penalties    
 43 @ [**]  While each Thumb instruction is twice     
 44 @       diverse as ARM ones: e.g., there are o    
 45 @       instructions with 3 arguments, no [fix    
 46 @       modes are limited. As result it takes     
 47 @       the same job in Thumb, therefore the c    
 48 @       small and always slower.                  
 49 @ [***] which is also ~35% better than compile    
 50 @       issue Cortex A8 core was measured to p    
 51 @       ~990 cycles.                              
 52                                                   
 53 @ August 2010.                                    
 54 @                                                 
 55 @ Rescheduling for dual-issue pipeline resulte    
 56 @ Cortex A8 core and in absolute terms ~870 cy    
 57 @ [or 13.6 cycles per byte].                      
 58                                                   
 59 @ February 2011.                                  
 60 @                                                 
 61 @ Profiler-assisted and platform-specific opti    
 62 @ improvement on Cortex A8 core and 12.2 cycle    
 63                                                   
 64 #include <linux/linkage.h>                        
 65                                                   
 66 .text                                             
 67                                                   
 68 .align  2                                         
 69 ENTRY(sha1_block_data_order)                      
 70         stmdb   sp!,{r4-r12,lr}                   
 71         add     r2,r1,r2,lsl#6  @ r2 to point     
 72         ldmia   r0,{r3,r4,r5,r6,r7}               
 73 .Lloop:                                           
 74         ldr     r8,.LK_00_19                      
 75         mov     r14,sp                            
 76         sub     sp,sp,#15*4                       
 77         mov     r5,r5,ror#30                      
 78         mov     r6,r6,ror#30                      
 79         mov     r7,r7,ror#30            @ [6]     
 80 .L_00_15:                                         
 81 #if __ARM_ARCH__<7                                
 82         ldrb    r10,[r1,#2]                       
 83         ldrb    r9,[r1,#3]                        
 84         ldrb    r11,[r1,#1]                       
 85         add     r7,r8,r7,ror#2                    
 86         ldrb    r12,[r1],#4                       
 87         orr     r9,r9,r10,lsl#8                   
 88         eor     r10,r5,r6                         
 89         orr     r9,r9,r11,lsl#16                  
 90         add     r7,r7,r3,ror#27                   
 91         orr     r9,r9,r12,lsl#24                  
 92 #else                                             
 93         ldr     r9,[r1],#4                        
 94         add     r7,r8,r7,ror#2                    
 95         eor     r10,r5,r6                         
 96         add     r7,r7,r3,ror#27                   
 97 #ifdef __ARMEL__                                  
 98         rev     r9,r9                             
 99 #endif                                            
100 #endif                                            
101         and     r10,r4,r10,ror#2                  
102         add     r7,r7,r9                          
103         eor     r10,r10,r6,ror#2                  
104         str     r9,[r14,#-4]!                     
105         add     r7,r7,r10                         
106 #if __ARM_ARCH__<7                                
107         ldrb    r10,[r1,#2]                       
108         ldrb    r9,[r1,#3]                        
109         ldrb    r11,[r1,#1]                       
110         add     r6,r8,r6,ror#2                    
111         ldrb    r12,[r1],#4                       
112         orr     r9,r9,r10,lsl#8                   
113         eor     r10,r4,r5                         
114         orr     r9,r9,r11,lsl#16                  
115         add     r6,r6,r7,ror#27                   
116         orr     r9,r9,r12,lsl#24                  
117 #else                                             
118         ldr     r9,[r1],#4                        
119         add     r6,r8,r6,ror#2                    
120         eor     r10,r4,r5                         
121         add     r6,r6,r7,ror#27                   
122 #ifdef __ARMEL__                                  
123         rev     r9,r9                             
124 #endif                                            
125 #endif                                            
126         and     r10,r3,r10,ror#2                  
127         add     r6,r6,r9                          
128         eor     r10,r10,r5,ror#2                  
129         str     r9,[r14,#-4]!                     
130         add     r6,r6,r10                         
131 #if __ARM_ARCH__<7                                
132         ldrb    r10,[r1,#2]                       
133         ldrb    r9,[r1,#3]                        
134         ldrb    r11,[r1,#1]                       
135         add     r5,r8,r5,ror#2                    
136         ldrb    r12,[r1],#4                       
137         orr     r9,r9,r10,lsl#8                   
138         eor     r10,r3,r4                         
139         orr     r9,r9,r11,lsl#16                  
140         add     r5,r5,r6,ror#27                   
141         orr     r9,r9,r12,lsl#24                  
142 #else                                             
143         ldr     r9,[r1],#4                        
144         add     r5,r8,r5,ror#2                    
145         eor     r10,r3,r4                         
146         add     r5,r5,r6,ror#27                   
147 #ifdef __ARMEL__                                  
148         rev     r9,r9                             
149 #endif                                            
150 #endif                                            
151         and     r10,r7,r10,ror#2                  
152         add     r5,r5,r9                          
153         eor     r10,r10,r4,ror#2                  
154         str     r9,[r14,#-4]!                     
155         add     r5,r5,r10                         
156 #if __ARM_ARCH__<7                                
157         ldrb    r10,[r1,#2]                       
158         ldrb    r9,[r1,#3]                        
159         ldrb    r11,[r1,#1]                       
160         add     r4,r8,r4,ror#2                    
161         ldrb    r12,[r1],#4                       
162         orr     r9,r9,r10,lsl#8                   
163         eor     r10,r7,r3                         
164         orr     r9,r9,r11,lsl#16                  
165         add     r4,r4,r5,ror#27                   
166         orr     r9,r9,r12,lsl#24                  
167 #else                                             
168         ldr     r9,[r1],#4                        
169         add     r4,r8,r4,ror#2                    
170         eor     r10,r7,r3                         
171         add     r4,r4,r5,ror#27                   
172 #ifdef __ARMEL__                                  
173         rev     r9,r9                             
174 #endif                                            
175 #endif                                            
176         and     r10,r6,r10,ror#2                  
177         add     r4,r4,r9                          
178         eor     r10,r10,r3,ror#2                  
179         str     r9,[r14,#-4]!                     
180         add     r4,r4,r10                         
181 #if __ARM_ARCH__<7                                
182         ldrb    r10,[r1,#2]                       
183         ldrb    r9,[r1,#3]                        
184         ldrb    r11,[r1,#1]                       
185         add     r3,r8,r3,ror#2                    
186         ldrb    r12,[r1],#4                       
187         orr     r9,r9,r10,lsl#8                   
188         eor     r10,r6,r7                         
189         orr     r9,r9,r11,lsl#16                  
190         add     r3,r3,r4,ror#27                   
191         orr     r9,r9,r12,lsl#24                  
192 #else                                             
193         ldr     r9,[r1],#4                        
194         add     r3,r8,r3,ror#2                    
195         eor     r10,r6,r7                         
196         add     r3,r3,r4,ror#27                   
197 #ifdef __ARMEL__                                  
198         rev     r9,r9                             
199 #endif                                            
200 #endif                                            
201         and     r10,r5,r10,ror#2                  
202         add     r3,r3,r9                          
203         eor     r10,r10,r7,ror#2                  
204         str     r9,[r14,#-4]!                     
205         add     r3,r3,r10                         
206         cmp     r14,sp                            
207         bne     .L_00_15                @ [((1    
208         sub     sp,sp,#25*4                       
209 #if __ARM_ARCH__<7                                
210         ldrb    r10,[r1,#2]                       
211         ldrb    r9,[r1,#3]                        
212         ldrb    r11,[r1,#1]                       
213         add     r7,r8,r7,ror#2                    
214         ldrb    r12,[r1],#4                       
215         orr     r9,r9,r10,lsl#8                   
216         eor     r10,r5,r6                         
217         orr     r9,r9,r11,lsl#16                  
218         add     r7,r7,r3,ror#27                   
219         orr     r9,r9,r12,lsl#24                  
220 #else                                             
221         ldr     r9,[r1],#4                        
222         add     r7,r8,r7,ror#2                    
223         eor     r10,r5,r6                         
224         add     r7,r7,r3,ror#27                   
225 #ifdef __ARMEL__                                  
226         rev     r9,r9                             
227 #endif                                            
228 #endif                                            
229         and     r10,r4,r10,ror#2                  
230         add     r7,r7,r9                          
231         eor     r10,r10,r6,ror#2                  
232         str     r9,[r14,#-4]!                     
233         add     r7,r7,r10                         
234         ldr     r9,[r14,#15*4]                    
235         ldr     r10,[r14,#13*4]                   
236         ldr     r11,[r14,#7*4]                    
237         add     r6,r8,r6,ror#2                    
238         ldr     r12,[r14,#2*4]                    
239         eor     r9,r9,r10                         
240         eor     r11,r11,r12                       
241         eor     r10,r4,r5                         
242         mov     r9,r9,ror#31                      
243         add     r6,r6,r7,ror#27                   
244         eor     r9,r9,r11,ror#31                  
245         str     r9,[r14,#-4]!                     
246         and r10,r3,r10,ror#2                      
247                                                   
248         add     r6,r6,r9                          
249         eor     r10,r10,r5,ror#2                  
250         add     r6,r6,r10                         
251         ldr     r9,[r14,#15*4]                    
252         ldr     r10,[r14,#13*4]                   
253         ldr     r11,[r14,#7*4]                    
254         add     r5,r8,r5,ror#2                    
255         ldr     r12,[r14,#2*4]                    
256         eor     r9,r9,r10                         
257         eor     r11,r11,r12                       
258         eor     r10,r3,r4                         
259         mov     r9,r9,ror#31                      
260         add     r5,r5,r6,ror#27                   
261         eor     r9,r9,r11,ror#31                  
262         str     r9,[r14,#-4]!                     
263         and r10,r7,r10,ror#2                      
264                                                   
265         add     r5,r5,r9                          
266         eor     r10,r10,r4,ror#2                  
267         add     r5,r5,r10                         
268         ldr     r9,[r14,#15*4]                    
269         ldr     r10,[r14,#13*4]                   
270         ldr     r11,[r14,#7*4]                    
271         add     r4,r8,r4,ror#2                    
272         ldr     r12,[r14,#2*4]                    
273         eor     r9,r9,r10                         
274         eor     r11,r11,r12                       
275         eor     r10,r7,r3                         
276         mov     r9,r9,ror#31                      
277         add     r4,r4,r5,ror#27                   
278         eor     r9,r9,r11,ror#31                  
279         str     r9,[r14,#-4]!                     
280         and r10,r6,r10,ror#2                      
281                                                   
282         add     r4,r4,r9                          
283         eor     r10,r10,r3,ror#2                  
284         add     r4,r4,r10                         
285         ldr     r9,[r14,#15*4]                    
286         ldr     r10,[r14,#13*4]                   
287         ldr     r11,[r14,#7*4]                    
288         add     r3,r8,r3,ror#2                    
289         ldr     r12,[r14,#2*4]                    
290         eor     r9,r9,r10                         
291         eor     r11,r11,r12                       
292         eor     r10,r6,r7                         
293         mov     r9,r9,ror#31                      
294         add     r3,r3,r4,ror#27                   
295         eor     r9,r9,r11,ror#31                  
296         str     r9,[r14,#-4]!                     
297         and r10,r5,r10,ror#2                      
298                                                   
299         add     r3,r3,r9                          
300         eor     r10,r10,r7,ror#2                  
301         add     r3,r3,r10                         
302                                                   
303         ldr     r8,.LK_20_39            @ [+15    
304         cmn     sp,#0                   @ [+3]    
305 .L_20_39_or_60_79:                                
306         ldr     r9,[r14,#15*4]                    
307         ldr     r10,[r14,#13*4]                   
308         ldr     r11,[r14,#7*4]                    
309         add     r7,r8,r7,ror#2                    
310         ldr     r12,[r14,#2*4]                    
311         eor     r9,r9,r10                         
312         eor     r11,r11,r12                       
313         eor     r10,r5,r6                         
314         mov     r9,r9,ror#31                      
315         add     r7,r7,r3,ror#27                   
316         eor     r9,r9,r11,ror#31                  
317         str     r9,[r14,#-4]!                     
318         eor r10,r4,r10,ror#2                      
319                                                   
320         add     r7,r7,r9                          
321         add     r7,r7,r10                         
322         ldr     r9,[r14,#15*4]                    
323         ldr     r10,[r14,#13*4]                   
324         ldr     r11,[r14,#7*4]                    
325         add     r6,r8,r6,ror#2                    
326         ldr     r12,[r14,#2*4]                    
327         eor     r9,r9,r10                         
328         eor     r11,r11,r12                       
329         eor     r10,r4,r5                         
330         mov     r9,r9,ror#31                      
331         add     r6,r6,r7,ror#27                   
332         eor     r9,r9,r11,ror#31                  
333         str     r9,[r14,#-4]!                     
334         eor r10,r3,r10,ror#2                      
335                                                   
336         add     r6,r6,r9                          
337         add     r6,r6,r10                         
338         ldr     r9,[r14,#15*4]                    
339         ldr     r10,[r14,#13*4]                   
340         ldr     r11,[r14,#7*4]                    
341         add     r5,r8,r5,ror#2                    
342         ldr     r12,[r14,#2*4]                    
343         eor     r9,r9,r10                         
344         eor     r11,r11,r12                       
345         eor     r10,r3,r4                         
346         mov     r9,r9,ror#31                      
347         add     r5,r5,r6,ror#27                   
348         eor     r9,r9,r11,ror#31                  
349         str     r9,[r14,#-4]!                     
350         eor r10,r7,r10,ror#2                      
351                                                   
352         add     r5,r5,r9                          
353         add     r5,r5,r10                         
354         ldr     r9,[r14,#15*4]                    
355         ldr     r10,[r14,#13*4]                   
356         ldr     r11,[r14,#7*4]                    
357         add     r4,r8,r4,ror#2                    
358         ldr     r12,[r14,#2*4]                    
359         eor     r9,r9,r10                         
360         eor     r11,r11,r12                       
361         eor     r10,r7,r3                         
362         mov     r9,r9,ror#31                      
363         add     r4,r4,r5,ror#27                   
364         eor     r9,r9,r11,ror#31                  
365         str     r9,[r14,#-4]!                     
366         eor r10,r6,r10,ror#2                      
367                                                   
368         add     r4,r4,r9                          
369         add     r4,r4,r10                         
370         ldr     r9,[r14,#15*4]                    
371         ldr     r10,[r14,#13*4]                   
372         ldr     r11,[r14,#7*4]                    
373         add     r3,r8,r3,ror#2                    
374         ldr     r12,[r14,#2*4]                    
375         eor     r9,r9,r10                         
376         eor     r11,r11,r12                       
377         eor     r10,r6,r7                         
378         mov     r9,r9,ror#31                      
379         add     r3,r3,r4,ror#27                   
380         eor     r9,r9,r11,ror#31                  
381         str     r9,[r14,#-4]!                     
382         eor r10,r5,r10,ror#2                      
383                                                   
384         add     r3,r3,r9                          
385         add     r3,r3,r10                         
386  ARM(   teq     r14,sp          )       @ pres    
387  THUMB( mov     r11,sp          )                 
388  THUMB( teq     r14,r11         )       @ pres    
389         bne     .L_20_39_or_60_79       @ [+((    
390         bcs     .L_done                 @ [+((    
391                                                   
392         ldr     r8,.LK_40_59                      
393         sub     sp,sp,#20*4             @ [+2]    
394 .L_40_59:                                         
395         ldr     r9,[r14,#15*4]                    
396         ldr     r10,[r14,#13*4]                   
397         ldr     r11,[r14,#7*4]                    
398         add     r7,r8,r7,ror#2                    
399         ldr     r12,[r14,#2*4]                    
400         eor     r9,r9,r10                         
401         eor     r11,r11,r12                       
402         eor     r10,r5,r6                         
403         mov     r9,r9,ror#31                      
404         add     r7,r7,r3,ror#27                   
405         eor     r9,r9,r11,ror#31                  
406         str     r9,[r14,#-4]!                     
407         and r10,r4,r10,ror#2                      
408         and r11,r5,r6                             
409         add     r7,r7,r9                          
410         add     r7,r7,r10                         
411         add     r7,r7,r11,ror#2                   
412         ldr     r9,[r14,#15*4]                    
413         ldr     r10,[r14,#13*4]                   
414         ldr     r11,[r14,#7*4]                    
415         add     r6,r8,r6,ror#2                    
416         ldr     r12,[r14,#2*4]                    
417         eor     r9,r9,r10                         
418         eor     r11,r11,r12                       
419         eor     r10,r4,r5                         
420         mov     r9,r9,ror#31                      
421         add     r6,r6,r7,ror#27                   
422         eor     r9,r9,r11,ror#31                  
423         str     r9,[r14,#-4]!                     
424         and r10,r3,r10,ror#2                      
425         and r11,r4,r5                             
426         add     r6,r6,r9                          
427         add     r6,r6,r10                         
428         add     r6,r6,r11,ror#2                   
429         ldr     r9,[r14,#15*4]                    
430         ldr     r10,[r14,#13*4]                   
431         ldr     r11,[r14,#7*4]                    
432         add     r5,r8,r5,ror#2                    
433         ldr     r12,[r14,#2*4]                    
434         eor     r9,r9,r10                         
435         eor     r11,r11,r12                       
436         eor     r10,r3,r4                         
437         mov     r9,r9,ror#31                      
438         add     r5,r5,r6,ror#27                   
439         eor     r9,r9,r11,ror#31                  
440         str     r9,[r14,#-4]!                     
441         and r10,r7,r10,ror#2                      
442         and r11,r3,r4                             
443         add     r5,r5,r9                          
444         add     r5,r5,r10                         
445         add     r5,r5,r11,ror#2                   
446         ldr     r9,[r14,#15*4]                    
447         ldr     r10,[r14,#13*4]                   
448         ldr     r11,[r14,#7*4]                    
449         add     r4,r8,r4,ror#2                    
450         ldr     r12,[r14,#2*4]                    
451         eor     r9,r9,r10                         
452         eor     r11,r11,r12                       
453         eor     r10,r7,r3                         
454         mov     r9,r9,ror#31                      
455         add     r4,r4,r5,ror#27                   
456         eor     r9,r9,r11,ror#31                  
457         str     r9,[r14,#-4]!                     
458         and r10,r6,r10,ror#2                      
459         and r11,r7,r3                             
460         add     r4,r4,r9                          
461         add     r4,r4,r10                         
462         add     r4,r4,r11,ror#2                   
463         ldr     r9,[r14,#15*4]                    
464         ldr     r10,[r14,#13*4]                   
465         ldr     r11,[r14,#7*4]                    
466         add     r3,r8,r3,ror#2                    
467         ldr     r12,[r14,#2*4]                    
468         eor     r9,r9,r10                         
469         eor     r11,r11,r12                       
470         eor     r10,r6,r7                         
471         mov     r9,r9,ror#31                      
472         add     r3,r3,r4,ror#27                   
473         eor     r9,r9,r11,ror#31                  
474         str     r9,[r14,#-4]!                     
475         and r10,r5,r10,ror#2                      
476         and r11,r6,r7                             
477         add     r3,r3,r9                          
478         add     r3,r3,r10                         
479         add     r3,r3,r11,ror#2                   
480         cmp     r14,sp                            
481         bne     .L_40_59                @ [+((    
482                                                   
483         ldr     r8,.LK_60_79                      
484         sub     sp,sp,#20*4                       
485         cmp     sp,#0                   @ set     
486         b       .L_20_39_or_60_79       @ [+4]    
487 .L_done:                                          
488         add     sp,sp,#80*4             @ "dea    
489         ldmia   r0,{r8,r9,r10,r11,r12}            
490         add     r3,r8,r3                          
491         add     r4,r9,r4                          
492         add     r5,r10,r5,ror#2                   
493         add     r6,r11,r6,ror#2                   
494         add     r7,r12,r7,ror#2                   
495         stmia   r0,{r3,r4,r5,r6,r7}               
496         teq     r1,r2                             
497         bne     .Lloop                  @ [+18    
498                                                   
499         ldmia   sp!,{r4-r12,pc}                   
500 .align  2                                         
501 .LK_00_19:      .word   0x5a827999                
502 .LK_20_39:      .word   0x6ed9eba1                
503 .LK_40_59:      .word   0x8f1bbcdc                
504 .LK_60_79:      .word   0xca62c1d6                
505 ENDPROC(sha1_block_data_order)                    
506 .asciz  "SHA1 block transform for ARMv4, CRYPT<    
507 .align  2                                         
                                                      

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