1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * arch/arm/include/asm/pgtable-2level.h
4 *
5 * Copyright (C) 1995-2002 Russell King
6 */
7 #ifndef _ASM_PGTABLE_2LEVEL_H
8 #define _ASM_PGTABLE_2LEVEL_H
9
10 #define __PAGETABLE_PMD_FOLDED 1
11
12 /*
13 * Hardware-wise, we have a two level page tab
14 * level has 4096 entries, and the second leve
15 * is one 32-bit word. Most of the bits in th
16 * by hardware, and there aren't any "accessed
17 *
18 * Linux on the other hand has a three level p
19 * be wrapped to fit a two level page table st
20 * and PTE only. However, Linux also expects
21 * at least a "dirty" bit.
22 *
23 * Therefore, we tweak the implementation slig
24 * have 2048 entries in the first level, each
25 * hardware pointers to the second level.) Th
26 * hardware PTE tables arranged contiguously,
27 * which contain the state information Linux n
28 * with 512 entries in the "PTE" level.
29 *
30 * This leads to the page tables having the fo
31 *
32 * pgd pte
33 * | |
34 * +--------+
35 * | | +------------+ +0
36 * +- - - - + | Linux pt 0 |
37 * | | +------------+ +1024
38 * +--------+ +0 | Linux pt 1 |
39 * | |-----> +------------+ +2048
40 * +- - - - + +4 | h/w pt 0 |
41 * | |-----> +------------+ +3072
42 * +--------+ +8 | h/w pt 1 |
43 * | | +------------+ +4096
44 *
45 * See L_PTE_xxx below for definitions of bits
46 * PTE_xxx for definitions of bits appearing i
47 *
48 * PMD_xxx definitions refer to bits in the fi
49 *
50 * The "dirty" bit is emulated by only grantin
51 * iff the page is marked "writable" and "dirt
52 * means that a write to a clean page will cau
53 * the Linux MM layer will mark the page dirty
54 * For the hardware to notice the permission c
55 * be flushed, and ptep_set_access_flags() doe
56 *
57 * The "accessed" or "young" bit is emulated b
58 * allow accesses to the page if the "young" b
59 * page will cause a fault, and handle_pte_fau
60 * for us as long as the page is marked presen
61 * PTE entry. Again, ptep_set_access_flags()
62 * up to date.
63 *
64 * However, when the "young" bit is cleared, w
65 * by clearing the hardware PTE. Currently Li
66 * for us in this case, which means the TLB wi
67 * until either the TLB entry is evicted under
68 * switch which changes the user space mapping
69 */
70 #define PTRS_PER_PTE 512
71 #define PTRS_PER_PMD 1
72 #define PTRS_PER_PGD 2048
73
74 #define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
75 #define PTE_HWTABLE_OFF (PTE_HWTABLE_P
76 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE
77
78 #define MAX_POSSIBLE_PHYSMEM_BITS 32
79
80 /*
81 * PMD_SHIFT determines the size of the area a
82 * PGDIR_SHIFT determines what a third-level p
83 */
84 #define PMD_SHIFT 21
85 #define PGDIR_SHIFT 21
86
87 #define PMD_SIZE (1UL << PMD_SH
88 #define PMD_MASK (~(PMD_SIZE-1)
89 #define PGDIR_SIZE (1UL << PGDIR_
90 #define PGDIR_MASK (~(PGDIR_SIZE-
91
92 /*
93 * section address mask and size definitions.
94 */
95 #define SECTION_SHIFT 20
96 #define SECTION_SIZE (1UL << SECTIO
97 #define SECTION_MASK (~(SECTION_SIZ
98
99 /*
100 * ARMv6 supersection address mask and size de
101 */
102 #define SUPERSECTION_SHIFT 24
103 #define SUPERSECTION_SIZE (1UL << SUPERS
104 #define SUPERSECTION_MASK (~(SUPERSECTIO
105
106 #define USER_PTRS_PER_PGD (TASK_SIZE / P
107
108 /*
109 * "Linux" PTE definitions.
110 *
111 * We keep two sets of PTEs - the hardware and
112 * This allows greater flexibility in the way
113 * onto the hardware tables, and allows us to
114 * bits.
115 *
116 * The PTE table pointer refers to the hardwar
117 * entries are stored 1024 bytes below.
118 */
119 #define L_PTE_VALID (_AT(pteval_t,
120 #define L_PTE_PRESENT (_AT(pteval_t,
121 #define L_PTE_YOUNG (_AT(pteval_t,
122 #define L_PTE_DIRTY (_AT(pteval_t,
123 #define L_PTE_RDONLY (_AT(pteval_t,
124 #define L_PTE_USER (_AT(pteval_t,
125 #define L_PTE_XN (_AT(pteval_t,
126 #define L_PTE_SHARED (_AT(pteval_t,
127 #define L_PTE_NONE (_AT(pteval_t,
128
129 /* We borrow bit 7 to store the exclusive mark
130 #define L_PTE_SWP_EXCLUSIVE L_PTE_RDONLY
131
132 /*
133 * These are the memory types, defined to be c
134 * pre-ARMv6 CPUs cacheable and bufferable bit
135 * ARMv6+ without TEX remapping, they are a ta
136 * ARMv6+ with TEX remapping, they correspond
137 *
138 * MT type Pre-ARMv6 ARMv6+
139 * UNCACHED Uncached Strong
140 * BUFFERABLE Bufferable Normal
141 * WRITETHROUGH Writethrough Normal
142 * WRITEBACK Writeback Normal
143 * MINICACHE Minicache N/A
144 * WRITEALLOC Writeback Normal
145 * DEV_SHARED Uncached Device
146 * DEV_NONSHARED Uncached Device
147 * DEV_WC Bufferable Normal
148 * DEV_CACHED Writeback Normal
149 * VECTORS Variable Normal
150 *
151 * All normal memory mappings have the followi
152 * - reads can be repeated with no side effect
153 * - repeated reads return the last value writ
154 * - reads can fetch additional locations with
155 * - writes can be repeated (in certain cases)
156 * - writes can be merged before accessing the
157 * - unaligned accesses can be supported
158 *
159 * All device mappings have the following prop
160 * - no access speculation
161 * - no repetition (eg, on return from an exce
162 * - number, order and size of accesses are ma
163 * - unaligned accesses are "unpredictable"
164 */
165 #define L_PTE_MT_UNCACHED (_AT(pteval_t,
166 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t,
167 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t,
168 #define L_PTE_MT_WRITEBACK (_AT(pteval_t,
169 #define L_PTE_MT_MINICACHE (_AT(pteval_t,
170 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t,
171 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t,
172 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t,
173 #define L_PTE_MT_DEV_WC (_AT(pteval_t,
174 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t,
175 #define L_PTE_MT_VECTORS (_AT(pteval_t,
176 #define L_PTE_MT_MASK (_AT(pteval_t,
177
178 #ifndef __ASSEMBLY__
179
180 /*
181 * The "pud_xxx()" functions here are trivial
182 * the pud: the pud entry is never bad, always
183 * cleared.
184 */
185 static inline int pud_none(pud_t pud)
186 {
187 return 0;
188 }
189
190 static inline int pud_bad(pud_t pud)
191 {
192 return 0;
193 }
194
195 static inline int pud_present(pud_t pud)
196 {
197 return 1;
198 }
199
200 static inline void pud_clear(pud_t *pudp)
201 {
202 }
203
204 static inline void set_pud(pud_t *pudp, pud_t
205 {
206 }
207
208 static inline pmd_t *pmd_offset(pud_t *pud, un
209 {
210 return (pmd_t *)pud;
211 }
212 #define pmd_offset pmd_offset
213
214 #define pmd_pfn(pmd) (__phys_to_pfn
215
216 #define pmd_leaf(pmd) (pmd_val(pmd)
217 #define pmd_bad(pmd) pmd_leaf(pmd)
218 #define pmd_present(pmd) (pmd_val(pmd))
219
220 #define copy_pmd(pmdpd,pmdps) \
221 do { \
222 pmdpd[0] = pmdps[0]; \
223 pmdpd[1] = pmdps[1]; \
224 flush_pmd_entry(pmdpd); \
225 } while (0)
226
227 #define pmd_clear(pmdp) \
228 do { \
229 pmdp[0] = __pmd(0); \
230 pmdp[1] = __pmd(0); \
231 clean_pmd_entry(pmdp); \
232 } while (0)
233
234 /* we don't need complex calculations here as
235 #define pmd_addr_end(addr,end) (end)
236
237 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_
238
239 /*
240 * We don't have huge page support for short d
241 * define empty stubs for use by pin_page_for_
242 */
243 #define pmd_hugewillfault(pmd) (0)
244
245 #endif /* __ASSEMBLY__ */
246
247 #endif /* _ASM_PGTABLE_2LEVEL_H */
248
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