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Linux/arch/arm/include/debug/brcmstb.S

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Diff markup

Differences between /arch/arm/include/debug/brcmstb.S (Architecture sparc) and /arch/mips/include/debug/brcmstb.S (Architecture mips)


  1 /* SPDX-License-Identifier: GPL-2.0-only */       
  2 /* Copyright (C) 2016 Broadcom */                 
  3 #include <linux/serial_reg.h>                     
  4 #include <asm/cputype.h>                          
  5                                                   
  6 /* Physical register offset and virtual regist    
  7 #define REG_PHYS_BASE           0xf0000000        
  8 #define REG_PHYS_BASE_V7        0x08000000        
  9 #define REG_VIRT_BASE           0xfc000000        
 10 #define REG_PHYS_ADDR(x)        ((x) + REG_PHY    
 11 #define REG_PHYS_ADDR_V7(x)     ((x) + REG_PHY    
 12                                                   
 13 /* Product id can be read from here */            
 14 #define SUN_TOP_CTRL_BASE       REG_PHYS_ADDR(    
 15 #define SUN_TOP_CTRL_BASE_V7    REG_PHYS_ADDR_    
 16                                                   
 17 #define UARTA_3390              REG_PHYS_ADDR(    
 18 #define UARTA_72116             UARTA_7255        
 19 #define UARTA_7250              REG_PHYS_ADDR(    
 20 #define UARTA_7255              REG_PHYS_ADDR(    
 21 #define UARTA_7260              UARTA_7255        
 22 #define UARTA_7268              UARTA_7255        
 23 #define UARTA_7271              UARTA_7268        
 24 #define UARTA_7278              REG_PHYS_ADDR_    
 25 #define UARTA_7216              UARTA_7278        
 26 #define UARTA_72164             UARTA_7278        
 27 #define UARTA_72165             UARTA_7278        
 28 #define UARTA_7364              REG_PHYS_ADDR(    
 29 #define UARTA_7366              UARTA_7364        
 30 #define UARTA_74165             UARTA_7278        
 31 #define UARTA_74371             REG_PHYS_ADDR(    
 32 #define UARTA_7439              REG_PHYS_ADDR(    
 33 #define UARTA_7445              REG_PHYS_ADDR(    
 34                                                   
 35 #define UART_SHIFT              2                 
 36                                                   
 37 #define checkuart(rp, rv, family_id, family) \    
 38                 /* Load family id */ \            
 39                 ldr     rp, =family_id ; \        
 40                 /* Compare SUN_TOP_CTRL value     
 41                 cmp     rp, rv ; \                
 42                 /* Passed test, load address *    
 43                 ldreq   rp, =UARTA_##family ;     
 44                 /* Jump to save UART address *    
 45                 beq     91f                       
 46                                                   
 47                 .macro  addruart, rp, rv, tmp     
 48                 adr     \rp, 99f                  
 49                 ldr     \rv, [\rp]                
 50                 sub     \rv, \rv, \rp             
 51                 ldr     \rp, [\rp, #4]            
 52                 sub     \tmp, \rp, \rv            
 53                 ldr     \rp, [\tmp]               
 54                 cmp     \rp, #1                   
 55                 bne     100f                      
 56                 mov     \rv, #0                   
 57                 str     \rv, [\tmp]               
 58                                                   
 59                 /* Check for V7 memory map if     
 60                 mrc     p15, 0, \rv, c0, c0, 0    
 61                 ldr     \rp, =ARM_CPU_PART_MAS    
 62                 and     \rv, \rv, \rp             
 63                 ldr     \rp, =ARM_CPU_PART_BRA    
 64                 cmp     \rv, \rp                  
 65                 bne     10f                       
 66                                                   
 67                 /* if PERIPHBASE doesn't overl    
 68                 mrc     p15, 1, \rv, c15, c3,     
 69                 ands    \rv, \rv, #REG_PHYS_BA    
 70                 ldreq   \rp, =SUN_TOP_CTRL_BAS    
 71                                                   
 72                 /* Check SUN_TOP_CTRL base */     
 73 10:             ldrne   \rp, =SUN_TOP_CTRL_BAS    
 74                 ldr     \rv, [\rp, #0]            
 75 ARM_BE8(        rev     \rv, \rv )                
 76                 and     \rv, \rv, #0xffffff00     
 77                                                   
 78                 /* Chip specific detection sta    
 79 20:             checkuart(\rp, \rv, 0x33900000    
 80 21:             checkuart(\rp, \rv, 0x07211600    
 81 22:             checkuart(\rp, \rv, 0x72160000    
 82 23:             checkuart(\rp, \rv, 0x07216400    
 83 24:             checkuart(\rp, \rv, 0x07216500    
 84 25:             checkuart(\rp, \rv, 0x72500000    
 85 26:             checkuart(\rp, \rv, 0x72550000    
 86 27:             checkuart(\rp, \rv, 0x72600000    
 87 28:             checkuart(\rp, \rv, 0x72680000    
 88 29:             checkuart(\rp, \rv, 0x72710000    
 89 30:             checkuart(\rp, \rv, 0x72780000    
 90 31:             checkuart(\rp, \rv, 0x73640000    
 91 32:             checkuart(\rp, \rv, 0x73660000    
 92 33:             checkuart(\rp, \rv, 0x07416500    
 93 34:             checkuart(\rp, \rv, 0x07437100    
 94 35:             checkuart(\rp, \rv, 0x74390000    
 95 36:             checkuart(\rp, \rv, 0x74450000    
 96                                                   
 97                 /* No valid UART found */         
 98 90:             mov     \rp, #0                   
 99                 /* fall through */                
100                                                   
101                 /* Record whichever UART we ch    
102 91:             str     \rp, [\tmp, #4]           
103                 cmp     \rp, #0                   
104                 bne     92f                       
105                 str     \rp, [\tmp, #8]           
106                 b       100f                      
107 92:             and     \rv, \rp, #0xffffff       
108                 add     \rv, \rv, #REG_VIRT_BA    
109                 str     \rv, [\tmp, #8]           
110                 b       100f                      
111                                                   
112                 .align                            
113 99:             .word   .                         
114                 .word   brcmstb_uart_config       
115                 .ltorg                            
116                                                   
117                 /* Load previously selected UA    
118 100:            ldr     \rp, [\tmp, #4]           
119                 ldr     \rv, [\tmp, #8]           
120                 .endm                             
121                                                   
122                 .macro  store, rd, rx:vararg      
123 ARM_BE8(        rev     \rd, \rd )                
124                 str     \rd, \rx                  
125                 .endm                             
126                                                   
127                 .macro  load, rd, rx:vararg       
128                 ldr     \rd, \rx                  
129 ARM_BE8(        rev     \rd, \rd )                
130                 .endm                             
131                                                   
132                 .macro  senduart,rd,rx            
133                 store   \rd, [\rx, #UART_TX <<    
134                 .endm                             
135                                                   
136                 .macro  busyuart,rd,rx            
137 1002:           load    \rd, [\rx, #UART_LSR <    
138                 and     \rd, \rd, #UART_LSR_TE    
139                 teq     \rd, #UART_LSR_TEMT |     
140                 bne     1002b                     
141                 .endm                             
142                                                   
143                 .macro  waituarttxrdy,rd,rx       
144                 .endm                             
145                                                   
146                 .macro  waituartcts,rd,rx         
147                 .endm                             
148                                                   
149 /*                                                
150  * Storage for the state maintained by the mac    
151  *                                                
152  * In the kernel proper, this data is located     
153  * That's because this header is included from    
154  * want a single copy of the data. In particul    
155  * assumes it's running using physical address    
156  * is included from head.o, but not when inclu    
157  * to share the probe results between the two     
158  * to re-run the probing again later.             
159  *                                                
160  * In the decompressor, we put the symbol/stor    
161  * isn't included in the decompressor build. T    
162  * even though it's really data, since .data i    
163  * decompressor. Luckily, .text is writeable i    
164  * CONFIG_ZBOOT_ROM. That dependency is handle    
165  */                                               
166 #if defined(ZIMAGE)                               
167 brcmstb_uart_config:                              
168         /* Debug UART initialization required     
169         .word 1                                   
170         /* Debug UART physical address */         
171         .word 0                                   
172         /* Debug UART virtual address */          
173         .word 0                                   
174 #endif                                            
                                                      

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