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Linux/arch/arm/include/debug/sa1100.S

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Diff markup

Differences between /arch/arm/include/debug/sa1100.S (Architecture alpha) and /arch/sparc64/include/debug/sa1100.S (Architecture sparc64)


  1 /* SPDX-License-Identifier: GPL-2.0-only */       
  2 /* arch/arm/include/debug/sa1100.S                
  3  *                                                
  4  * Debugging macro include header                 
  5  *                                                
  6  *  Copyright (C) 1994-1999 Russell King          
  7  *  Moved from linux/arch/arm/kernel/debug.S b    
  8 */                                                
  9                                                   
 10 #define UTCR3           0x0c                      
 11 #define UTDR            0x14                      
 12 #define UTSR1           0x20                      
 13 #define UTCR3_TXE       0x00000002      /* Tra    
 14 #define UTSR1_TBY       0x00000001      /* Tra    
 15 #define UTSR1_TNF       0x00000004      /* Tra    
 16                                                   
 17                 .macro  addruart, rp, rv, tmp     
 18                 mrc     p15, 0, \rp, c1, c0       
 19                 tst     \rp, #1                   
 20                 moveq   \rp, #0x80000000          
 21                 movne   \rp, #0xf8000000          
 22                                                   
 23                 @ We probe for the active seri    
 24                 @ the comment in arch/arm/mach    
 25                 @ We assume r1 can be clobbere    
 26                                                   
 27                 @ see if Ser3 is active           
 28                 add     \rp, \rp, #0x00050000     
 29                 ldr     \rv, [\rp, #UTCR3]        
 30                 tst     \rv, #UTCR3_TXE           
 31                                                   
 32                 @ if Ser3 is inactive, then tr    
 33                 addeq   \rp, \rp, #(0x00010000    
 34                 ldreq   \rv, [\rp, #UTCR3]        
 35                 tsteq   \rv, #UTCR3_TXE           
 36                                                   
 37                 @ if Ser1 is inactive, then tr    
 38                 addeq   \rp, \rp, #(0x00030000    
 39                 ldreq   \rv, [\rp, #UTCR3]        
 40                 tsteq   \rv, #UTCR3_TXE           
 41                                                   
 42                 @ clear top bits, and generate    
 43                 lsl     \rp, \rp, #8              
 44                 lsr     \rp, \rp, #8              
 45                 orr     \rv, \rp, #0xf8000000     
 46                 orr     \rp, \rp, #0x80000000     
 47                                                   
 48                 .endm                             
 49                                                   
 50                 .macro  senduart,rd,rx            
 51                 str     \rd, [\rx, #UTDR]         
 52                 .endm                             
 53                                                   
 54                 .macro  waituartcts,rd,rx         
 55                 .endm                             
 56                                                   
 57                 .macro  waituarttxrdy,rd,rx       
 58 1001:           ldr     \rd, [\rx, #UTSR1]        
 59                 tst     \rd, #UTSR1_TNF           
 60                 beq     1001b                     
 61                 .endm                             
 62                                                   
 63                 .macro  busyuart,rd,rx            
 64 1001:           ldr     \rd, [\rx, #UTSR1]        
 65                 tst     \rd, #UTSR1_TBY           
 66                 bne     1001b                     
 67                 .endm                             
                                                      

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