1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/linkage.h>
3 #include <linux/threads.h>
4 #include <asm/asm-offsets.h>
5 #include <asm/assembler.h>
6 #include <asm/glue-cache.h>
7 #include <asm/glue-proc.h>
8 .text
9
10 /*
11 * Implementation of MPIDR hash algorithm thro
12 * and OR'ing.
13 *
14 * @dst: register containing hash result
15 * @rs0: register containing affinity level 0
16 * @rs1: register containing affinity level 1
17 * @rs2: register containing affinity level 2
18 * @mpidr: register containing MPIDR value
19 * @mask: register containing MPIDR mask
20 *
21 * Pseudo C-code:
22 *
23 *u32 dst;
24 *
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2
26 * u32 aff0, aff1, aff2;
27 * u32 mpidr_masked = mpidr & mask;
28 * aff0 = mpidr_masked & 0xff;
29 * aff1 = mpidr_masked & 0xff00;
30 * aff2 = mpidr_masked & 0xff0000;
31 * dst = (aff0 >> rs0 | aff1 >> rs1 | aff
32 *}
33 * Input registers: rs0, rs1, rs2, mpidr, mask
34 * Output register: dst
35 * Note: input and output registers must be di
36 (eg: a macro instance with mpidr = r1
37 */
38 .macro compute_mpidr_hash dst, rs0, rs
39 and \mpidr, \mpidr, \mask
40 and \dst, \mpidr, #0xff
41 ARM( mov \dst, \dst, lsr \rs0
42 THUMB( lsr \dst, \dst, \rs0
43 and \mask, \mpidr, #0xff00
44 ARM( orr \dst, \dst, \mask, lsr \rs1
45 THUMB( lsr \mask, \mask, \rs1
46 THUMB( orr \dst, \dst, \mask
47 and \mask, \mpidr, #0xff0000
48 ARM( orr \dst, \dst, \mask, lsr \rs2
49 THUMB( lsr \mask, \mask, \rs2
50 THUMB( orr \dst, \dst, \mask
51 .endm
52
53 /*
54 * Save CPU state for a suspend. This saves t
55 * registers, and allocates space on the kerne
56 * specific registers and some other data for
57 * r0 = suspend function arg0
58 * r1 = suspend function
59 * r2 = MPIDR value the resuming CPU will use
60 */
61 ENTRY(__cpu_suspend)
62 stmfd sp!, {r4 - r11, lr}
63 #ifdef MULTI_CPU
64 ldr r10, =processor
65 ldr r4, [r10, #CPU_SLEEP_SIZE] @ s
66 #else
67 ldr r4, =cpu_suspend_size
68 #endif
69 mov r5, sp @ curr
70 #ifdef CONFIG_VMAP_STACK
71 @ Run the suspend code from the overfl
72 @ on vmalloc-to-phys conversions anywh
73 @ The original SP value captured in R5
74 ldr_this_cpu sp, overflow_stack_ptr, r
75 #endif
76 add r4, r4, #12 @ Spac
77 sub sp, sp, r4 @ allo
78 ldr r3, =sleep_save_sp
79 stmfd sp!, {r0, r1} @ save
80 ldr r3, [r3, #SLEEP_SAVE_SP_VIRT]
81 ALT_SMP(W(nop)) @ don'
82 ALT_UP_B(1f)
83 adr_l r0, mpidr_hash
84 /* This ldmia relies on the memory lay
85 ldmia r0, {r1, r6-r8} @ r1 = mpidr m
86 compute_mpidr_hash r0, r6, r7, r8
87 add r3, r3, r0, lsl #2
88 1: mov r2, r5 @ virt
89 mov r1, r4 @ size
90 add r0, sp, #8 @ poin
91 bl __cpu_suspend_save
92 badr lr, cpu_suspend_abort
93 ldmfd sp!, {r0, pc} @ call
94 ENDPROC(__cpu_suspend)
95 .ltorg
96
97 cpu_suspend_abort:
98 ldmia sp!, {r1 - r3} @ pop
99 teq r0, #0
100 moveq r0, #1 @ forc
101 mov sp, r2
102 ldmfd sp!, {r4 - r11, pc}
103 ENDPROC(cpu_suspend_abort)
104
105 /*
106 * r0 = control register value
107 */
108 .align 5
109 .pushsection .idmap.text,"ax"
110 ENTRY(cpu_resume_mmu)
111 ldr r3, =cpu_resume_after_mmu
112 instr_sync
113 mcr p15, 0, r0, c1, c0, 0 @ turn
114 mrc p15, 0, r0, c0, c0, 0 @ read
115 instr_sync
116 mov r0, r0
117 mov r0, r0
118 ret r3 @ jump
119 ENDPROC(cpu_resume_mmu)
120 .popsection
121 cpu_resume_after_mmu:
122 #if defined(CONFIG_VMAP_STACK) && !defined(CON
123 @ Before using the vmap'ed stack, we h
124 @ as the ID map does not cover the vma
125 mrc p15, 0, ip, c2, c0, 1 @ read
126 mcr p15, 0, ip, c2, c0, 0 @ set
127 instr_sync
128 #endif
129 bl cpu_init @ rest
130 #if defined(CONFIG_KASAN) && defined(CONFIG_KA
131 mov r0, sp
132 bl kasan_unpoison_task_stack_belo
133 #endif
134 mov r0, #0 @ retu
135 ldmfd sp!, {r4 - r11, pc}
136 ENDPROC(cpu_resume_after_mmu)
137
138 .text
139 .align
140
141 #ifdef CONFIG_MCPM
142 .arm
143 THUMB( .thumb )
144 ENTRY(cpu_resume_no_hyp)
145 ARM_BE8(setend be) @ ensu
146 b no_hyp
147 #endif
148
149 #ifdef CONFIG_MMU
150 .arm
151 ENTRY(cpu_resume_arm)
152 THUMB( badr r9, 1f ) @ Kern
153 THUMB( bx r9 ) @ If t
154 THUMB( .thumb ) @ swit
155 THUMB(1: )
156 #endif
157
158 ENTRY(cpu_resume)
159 ARM_BE8(setend be) @ ensu
160 #ifdef CONFIG_ARM_VIRT_EXT
161 bl __hyp_stub_install_secondary
162 #endif
163 safe_svcmode_maskall r1
164 no_hyp:
165 mov r1, #0
166 ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
167 ALT_UP_B(1f)
168 adr_l r2, mpidr_hash @ r2 =
169
170 /*
171 * This ldmia relies on the memory lay
172 * struct mpidr_hash.
173 */
174 ldmia r2, { r3-r6 } @ r3 = mpidr m
175 compute_mpidr_hash r1, r4, r5, r6
176 1:
177 ldr_l r0, sleep_save_sp + SLEEP_SAVE
178 ldr r0, [r0, r1, lsl #2]
179
180 @ load phys pgd, stack, resume fn
181 ARM( ldmia r0!, {r1, sp, pc} )
182 THUMB( ldmia r0!, {r1, r2, r3} )
183 THUMB( mov sp, r2 )
184 THUMB( bx r3 )
185 ENDPROC(cpu_resume)
186
187 #ifdef CONFIG_MMU
188 ENDPROC(cpu_resume_arm)
189 #endif
190 #ifdef CONFIG_MCPM
191 ENDPROC(cpu_resume_no_hyp)
192 #endif
193
194 .data
195 .align 2
196 .type sleep_save_sp, #object
197 ENTRY(sleep_save_sp)
198 .space SLEEP_SAVE_SP_SZ
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