1 // SPDX-License-Identifier: GPL-2.0-or-later 1
2 /*
3 * DA8XX/OMAP L1XX platform device data
4 *
5 * Copyright (c) 2007-2009, MontaVista Softwar
6 * Derived from code that was:
7 * Copyright (C) 2006 Komal Shah <komal_s
8 */
9 #include <linux/ahci_platform.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk.h>
12 #include <linux/clkdev.h>
13 #include <linux/dma-map-ops.h>
14 #include <linux/dmaengine.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/platform_device.h>
18 #include <linux/reboot.h>
19 #include <linux/serial_8250.h>
20
21 #include "common.h"
22 #include "cputype.h"
23 #include "da8xx.h"
24 #include "cpuidle.h"
25 #include "irqs.h"
26 #include "sram.h"
27
28 #define DA8XX_TPCC_BASE 0x01c0
29 #define DA8XX_TPTC0_BASE 0x01c0
30 #define DA8XX_TPTC1_BASE 0x01c0
31 #define DA8XX_WDOG_BASE 0x01c2
32 #define DA8XX_I2C0_BASE 0x01c2
33 #define DA8XX_RTC_BASE 0x01c2
34 #define DA8XX_PRUSS_MEM_BASE 0x01c3
35 #define DA8XX_MMCSD0_BASE 0x01c4
36 #define DA8XX_SPI0_BASE 0x01c4
37 #define DA830_SPI1_BASE 0x01e1
38 #define DA8XX_LCD_CNTRL_BASE 0x01e1
39 #define DA850_SATA_BASE 0x01e1
40 #define DA850_MMCSD1_BASE 0x01e1
41 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e2
42 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e2
43 #define DA8XX_EMAC_CPGMAC_BASE 0x01e2
44 #define DA8XX_EMAC_MDIO_BASE 0x01e2
45 #define DA8XX_I2C1_BASE 0x01e2
46 #define DA850_TPCC1_BASE 0x01e3
47 #define DA850_TPTC2_BASE 0x01e3
48 #define DA850_SPI1_BASE 0x01f0
49 #define DA8XX_DDR2_CTL_BASE 0xb000
50
51 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
52 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
53 #define DA8XX_EMAC_RAM_OFFSET 0x0000
54 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
55
56 void __iomem *da8xx_syscfg0_base;
57 void __iomem *da8xx_syscfg1_base;
58
59 static void __iomem *da8xx_ddr2_ctlr_base;
60 void __iomem * __init da8xx_get_mem_ctlr(void)
61 {
62 if (da8xx_ddr2_ctlr_base)
63 return da8xx_ddr2_ctlr_base;
64
65 da8xx_ddr2_ctlr_base = ioremap(DA8XX_D
66 if (!da8xx_ddr2_ctlr_base)
67 pr_warn("%s: Unable to map DDR
68
69 return da8xx_ddr2_ctlr_base;
70 }
71
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