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Linux/arch/arm/mach-dove/bridge-regs.h

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Diff markup

Differences between /arch/arm/mach-dove/bridge-regs.h (Version linux-6.12-rc7) and /arch/ppc/mach-dove/bridge-regs.h (Version linux-6.6.60)


  1 /* SPDX-License-Identifier: GPL-2.0-only */         1 
  2 /* Mbus-L to Mbus Bridge Registers */             
  3                                                   
  4 #ifndef __ASM_ARCH_BRIDGE_REGS_H                  
  5 #define __ASM_ARCH_BRIDGE_REGS_H                  
  6                                                   
  7 #include "dove.h"                                 
  8                                                   
  9 #define CPU_CONFIG              (BRIDGE_VIRT_B    
 10                                                   
 11 #define CPU_CONTROL             (BRIDGE_VIRT_B    
 12 #define  CPU_CTRL_PCIE0_LINK    0x00000001        
 13 #define  CPU_RESET              0x00000002        
 14 #define  CPU_CTRL_PCIE1_LINK    0x00000008        
 15                                                   
 16 #define RSTOUTn_MASK            (BRIDGE_VIRT_B    
 17 #define RSTOUTn_MASK_PHYS       (BRIDGE_PHYS_B    
 18 #define  SOFT_RESET_OUT_EN      0x00000004        
 19                                                   
 20 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_B    
 21 #define  SOFT_RESET             0x00000001        
 22                                                   
 23 #define BRIDGE_CAUSE            (BRIDGE_VIRT_B    
 24 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)         
 25                                                   
 26 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_B    
 27 #define IRQ_CAUSE_LOW_OFF       0x0000            
 28 #define IRQ_MASK_LOW_OFF        0x0004            
 29 #define FIQ_MASK_LOW_OFF        0x0008            
 30 #define ENDPOINT_MASK_LOW_OFF   0x000c            
 31 #define IRQ_CAUSE_HIGH_OFF      0x0010            
 32 #define IRQ_MASK_HIGH_OFF       0x0014            
 33 #define FIQ_MASK_HIGH_OFF       0x0018            
 34 #define ENDPOINT_MASK_HIGH_OFF  0x001c            
 35 #define PCIE_INTERRUPT_MASK_OFF 0x0020            
 36                                                   
 37 #define IRQ_MASK_LOW            (IRQ_VIRT_BASE    
 38 #define FIQ_MASK_LOW            (IRQ_VIRT_BASE    
 39 #define ENDPOINT_MASK_LOW       (IRQ_VIRT_BASE    
 40 #define IRQ_MASK_HIGH           (IRQ_VIRT_BASE    
 41 #define FIQ_MASK_HIGH           (IRQ_VIRT_BASE    
 42 #define ENDPOINT_MASK_HIGH      (IRQ_VIRT_BASE    
 43 #define PCIE_INTERRUPT_MASK     (IRQ_VIRT_BASE    
 44                                                   
 45 #define POWER_MANAGEMENT        (BRIDGE_VIRT_B    
 46                                                   
 47 #define TIMER_VIRT_BASE         (BRIDGE_VIRT_B    
 48 #define TIMER_PHYS_BASE         (BRIDGE_PHYS_B    
 49                                                   
 50 #endif                                            
 51                                                   

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