1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 2 /* 3 * arch/arm/mach-lpc32xx/include/mach/platform 4 * 5 * Author: Kevin Wells <kevin.wells@nxp.com> 6 * 7 * Copyright (C) 2010 NXP Semiconductors 8 */ 9 10 #ifndef __ARM_LPC32XX_H 11 #define __ARM_LPC32XX_H 12 13 #define _SBF(f, v) 14 #define _BIT(n) 15 16 /* 17 * AHB 0 physical base addresses 18 */ 19 #define LPC32XX_SLC_BASE 20 #define LPC32XX_SSP0_BASE 21 #define LPC32XX_SPI1_BASE 22 #define LPC32XX_SSP1_BASE 23 #define LPC32XX_SPI2_BASE 24 #define LPC32XX_I2S0_BASE 25 #define LPC32XX_SD_BASE 26 #define LPC32XX_I2S1_BASE 27 #define LPC32XX_MLC_BASE 28 #define LPC32XX_AHB0_START 29 #define LPC32XX_AHB0_SIZE 30 31 /* 32 * AHB 1 physical base addresses 33 */ 34 #define LPC32XX_DMA_BASE 35 #define LPC32XX_USB_BASE 36 #define LPC32XX_USBH_BASE 37 #define LPC32XX_USB_OTG_BASE 38 #define LPC32XX_OTG_I2C_BASE 39 #define LPC32XX_LCD_BASE 40 #define LPC32XX_ETHERNET_BASE 41 #define LPC32XX_EMC_BASE 42 #define LPC32XX_ETB_CFG_BASE 43 #define LPC32XX_ETB_DATA_BASE 44 #define LPC32XX_AHB1_START 45 #define LPC32XX_AHB1_SIZE 46 47 /* 48 * FAB physical base addresses 49 */ 50 #define LPC32XX_CLK_PM_BASE 51 #define LPC32XX_MIC_BASE 52 #define LPC32XX_SIC1_BASE 53 #define LPC32XX_SIC2_BASE 54 #define LPC32XX_HS_UART1_BASE 55 #define LPC32XX_HS_UART2_BASE 56 #define LPC32XX_HS_UART7_BASE 57 #define LPC32XX_RTC_BASE 58 #define LPC32XX_RTC_RAM_BASE 59 #define LPC32XX_GPIO_BASE 60 #define LPC32XX_PWM3_BASE 61 #define LPC32XX_PWM4_BASE 62 #define LPC32XX_MSTIM_BASE 63 #define LPC32XX_HSTIM_BASE 64 #define LPC32XX_WDTIM_BASE 65 #define LPC32XX_DEBUG_CTRL_BASE 66 #define LPC32XX_TIMER0_BASE 67 #define LPC32XX_ADC_BASE 68 #define LPC32XX_TIMER1_BASE 69 #define LPC32XX_KSCAN_BASE 70 #define LPC32XX_UART_CTRL_BASE 71 #define LPC32XX_TIMER2_BASE 72 #define LPC32XX_PWM1_BASE 73 #define LPC32XX_PWM2_BASE 74 #define LPC32XX_TIMER3_BASE 75 76 /* 77 * APB physical base addresses 78 */ 79 #define LPC32XX_UART3_BASE 80 #define LPC32XX_UART4_BASE 81 #define LPC32XX_UART5_BASE 82 #define LPC32XX_UART6_BASE 83 #define LPC32XX_I2C1_BASE 84 #define LPC32XX_I2C2_BASE 85 86 /* 87 * FAB and APB base and sizing 88 */ 89 #define LPC32XX_FABAPB_START 90 #define LPC32XX_FABAPB_SIZE 91 92 /* 93 * Internal memory bases and sizes 94 */ 95 #define LPC32XX_IRAM_BASE 96 #define LPC32XX_IROM_BASE 97 98 /* 99 * External Static Memory Bank Address Space B 100 */ 101 #define LPC32XX_EMC_CS0_BASE 102 #define LPC32XX_EMC_CS1_BASE 103 #define LPC32XX_EMC_CS2_BASE 104 #define LPC32XX_EMC_CS3_BASE 105 106 /* 107 * External SDRAM Memory Bank Address Space Ba 108 */ 109 #define LPC32XX_EMC_DYCS0_BASE 110 #define LPC32XX_EMC_DYCS1_BASE 111 112 /* 113 * Clock and crystal information 114 */ 115 #define LPC32XX_MAIN_OSC_FREQ 116 #define LPC32XX_CLOCK_OSC_FREQ 117 118 /* 119 * Clock and Power control register offsets 120 */ 121 #define _PMREG(x) 122 123 #define LPC32XX_CLKPWR_DEBUG_CTRL 124 #define LPC32XX_CLKPWR_BOOTMAP 125 #define LPC32XX_CLKPWR_P01_ER 126 #define LPC32XX_CLKPWR_USBCLK_PDIV 127 #define LPC32XX_CLKPWR_INT_ER 128 #define LPC32XX_CLKPWR_INT_RS 129 #define LPC32XX_CLKPWR_INT_SR 130 #define LPC32XX_CLKPWR_INT_AP 131 #define LPC32XX_CLKPWR_PIN_ER 132 #define LPC32XX_CLKPWR_PIN_RS 133 #define LPC32XX_CLKPWR_PIN_SR 134 #define LPC32XX_CLKPWR_PIN_AP 135 #define LPC32XX_CLKPWR_HCLK_DIV 136 #define LPC32XX_CLKPWR_PWR_CTRL 137 #define LPC32XX_CLKPWR_PLL397_CTRL 138 #define LPC32XX_CLKPWR_MAIN_OSC_CTRL 139 #define LPC32XX_CLKPWR_SYSCLK_CTRL 140 #define LPC32XX_CLKPWR_LCDCLK_CTRL 141 #define LPC32XX_CLKPWR_HCLKPLL_CTRL 142 #define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 143 #define LPC32XX_CLKPWR_USB_CTRL 144 #define LPC32XX_CLKPWR_SDRAMCLK_CTRL 145 #define LPC32XX_CLKPWR_DDR_LAP_NOM 146 #define LPC32XX_CLKPWR_DDR_LAP_COUNT 147 #define LPC32XX_CLKPWR_DDR_LAP_DELAY 148 #define LPC32XX_CLKPWR_SSP_CLK_CTRL 149 #define LPC32XX_CLKPWR_I2S_CLK_CTRL 150 #define LPC32XX_CLKPWR_MS_CTRL 151 #define LPC32XX_CLKPWR_MACCLK_CTRL 152 #define LPC32XX_CLKPWR_TEST_CLK_SEL 153 #define LPC32XX_CLKPWR_SFW_INT 154 #define LPC32XX_CLKPWR_I2C_CLK_CTRL 155 #define LPC32XX_CLKPWR_KEY_CLK_CTRL 156 #define LPC32XX_CLKPWR_ADC_CLK_CTRL 157 #define LPC32XX_CLKPWR_PWM_CLK_CTRL 158 #define LPC32XX_CLKPWR_TIMER_CLK_CTRL 159 #define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 160 #define LPC32XX_CLKPWR_SPI_CLK_CTRL 161 #define LPC32XX_CLKPWR_NAND_CLK_CTRL 162 #define LPC32XX_CLKPWR_UART3_CLK_CTRL 163 #define LPC32XX_CLKPWR_UART4_CLK_CTRL 164 #define LPC32XX_CLKPWR_UART5_CLK_CTRL 165 #define LPC32XX_CLKPWR_UART6_CLK_CTRL 166 #define LPC32XX_CLKPWR_IRDA_CLK_CTRL 167 #define LPC32XX_CLKPWR_UART_CLK_CTRL 168 #define LPC32XX_CLKPWR_DMA_CLK_CTRL 169 #define LPC32XX_CLKPWR_AUTOCLOCK 170 #define LPC32XX_CLKPWR_DEVID(x) 171 172 /* 173 * clkpwr_debug_ctrl register definitions 174 */ 175 #define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT 176 177 /* 178 * clkpwr_bootmap register definitions 179 */ 180 #define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT 181 182 /* 183 * clkpwr_start_gpio register bit definitions 184 */ 185 #define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT 186 #define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT 187 #define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT 188 #define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT 189 #define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT 190 #define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT 191 #define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT 192 #define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT 193 #define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT 194 #define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT 195 #define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT 196 #define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT 197 #define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT 198 #define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT 199 #define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT 200 #define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT 201 #define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT 202 #define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT 203 #define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT 204 #define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT 205 #define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT 206 #define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT 207 #define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT 208 #define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT 209 #define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT 210 #define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT 211 #define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT 212 #define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT 213 #define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT 214 #define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT 215 #define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT 216 #define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT 217 218 /* 219 * clkpwr_usbclk_pdiv register definitions 220 */ 221 #define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 222 223 /* 224 * clkpwr_start_int, clkpwr_start_raw_sts_int, 225 * clkpwr_start_pol_int, register bit definiti 226 */ 227 #define LPC32XX_CLKPWR_INTSRC_ADC_BIT 228 #define LPC32XX_CLKPWR_INTSRC_TS_P_BIT 229 #define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT 230 #define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT 231 #define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT 232 #define LPC32XX_CLKPWR_INTSRC_RTC_BIT 233 #define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT 234 #define LPC32XX_CLKPWR_INTSRC_USB_BIT 235 #define LPC32XX_CLKPWR_INTSRC_I2C_BIT 236 #define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT 237 #define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT 238 #define LPC32XX_CLKPWR_INTSRC_KEY_BIT 239 #define LPC32XX_CLKPWR_INTSRC_MAC_BIT 240 #define LPC32XX_CLKPWR_INTSRC_P0P1_BIT 241 #define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT 242 #define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT 243 #define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT 244 #define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT 245 #define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT 246 #define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT 247 248 /* 249 * clkpwr_start_pin, clkpwr_start_raw_sts_pin, 250 * clkpwr_start_pol_pin register bit definitio 251 */ 252 #define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT 253 #define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT 254 #define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT 255 #define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT 256 #define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT 257 #define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT 258 #define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT 259 #define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT 260 #define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT 261 #define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT 262 #define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT 263 #define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT 264 #define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT 265 #define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT 266 #define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT 267 #define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT 268 #define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT 269 #define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT 270 #define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT 271 #define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT 272 #define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT 273 #define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT 274 #define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT 275 #define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT 276 #define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT 277 278 /* 279 * clkpwr_hclk_div register definitions 280 */ 281 #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP 282 #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM 283 #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF 284 #define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) 285 #define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) 286 287 /* 288 * clkpwr_pwr_ctrl register definitions 289 */ 290 #define LPC32XX_CLKPWR_CTRL_FORCE_PCLK 291 #define LPC32XX_CLKPWR_SDRAM_SELF_RFSH 292 #define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH 293 #define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH 294 #define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT 295 #define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT 296 #define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN 297 #define LPC32XX_CLKPWR_SELECT_RUN_MODE 298 #define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN 299 #define LPC32XX_CLKPWR_STOP_MODE_CTRL 300 301 /* 302 * clkpwr_pll397_ctrl register definitions 303 */ 304 #define LPC32XX_CLKPWR_PLL397_MSLOCK_STS 305 #define LPC32XX_CLKPWR_PLL397_BYPASS 306 #define LPC32XX_CLKPWR_PLL397_BIAS_NORM 307 #define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 308 #define LPC32XX_CLKPWR_PLL397_BIAS_N25 309 #define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 310 #define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 311 #define LPC32XX_CLKPWR_PLL397_BIAS_P25 312 #define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 313 #define LPC32XX_CLKPWR_PLL397_BIAS_P50 314 #define LPC32XX_CLKPWR_PLL397_BIAS_MASK 315 #define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS 316 #define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS 317 318 /* 319 * clkpwr_main_osc_ctrl register definitions 320 */ 321 #define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) 322 #define LPC32XX_CLKPWR_MOSC_CAP_MASK 323 #define LPC32XX_CLKPWR_TEST_MODE 324 #define LPC32XX_CLKPWR_MOSC_DISABLE 325 326 /* 327 * clkpwr_sysclk_ctrl register definitions 328 */ 329 #define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) 330 #define LPC32XX_CLKPWR_SYSCTRL_BP_MASK 331 #define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 332 #define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX 333 334 /* 335 * clkpwr_lcdclk_ctrl register definitions 336 */ 337 #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 338 #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 339 #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 340 #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 341 #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 342 #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 343 #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 344 #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 345 #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 346 #define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 347 #define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) 348 #define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 349 350 /* 351 * clkpwr_hclkpll_ctrl register definitions 352 */ 353 #define LPC32XX_CLKPWR_HCLKPLL_POWER_UP 354 #define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS 355 #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS 356 #define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK 357 #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) 358 #define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) 359 #define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) 360 #define LPC32XX_CLKPWR_HCLKPLL_PLL_STS 361 362 /* 363 * clkpwr_adc_clk_ctrl_1 register definitions 364 */ 365 #define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) 366 #define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL 367 368 /* 369 * clkpwr_usb_ctrl register definitions 370 */ 371 #define LPC32XX_CLKPWR_USBCTRL_HCLK_EN 372 #define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN 373 #define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN 374 #define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN 375 #define LPC32XX_CLKPWR_USBCTRL_PU_ADD 376 #define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER 377 #define LPC32XX_CLKPWR_USBCTRL_PD_ADD 378 #define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 379 #define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 380 #define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP 381 #define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS 382 #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS 383 #define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK 384 #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) 385 #define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) 386 #define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) 387 #define LPC32XX_CLKPWR_USBCTRL_PLL_STS 388 389 /* 390 * clkpwr_sdramclk_ctrl register definitions 391 */ 392 #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK 393 #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW 394 #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT 395 #define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET 396 #define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) 397 #define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS 398 #define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) 399 #define LPC32XX_CLKPWR_SDRCLK_USE_CAL 400 #define LPC32XX_CLKPWR_SDRCLK_DO_CAL 401 #define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC 402 #define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) 403 #define LPC32XX_CLKPWR_SDRCLK_USE_DDR 404 #define LPC32XX_CLKPWR_SDRCLK_CLK_DIS 405 406 /* 407 * clkpwr_ssp_blk_ctrl register definitions 408 */ 409 #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX 410 #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX 411 #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX 412 #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX 413 #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN 414 #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN 415 416 /* 417 * clkpwr_i2s_clk_ctrl register definitions 418 */ 419 #define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX 420 #define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX 421 #define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA 422 #define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX 423 #define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX 424 #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN 425 #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN 426 427 /* 428 * clkpwr_ms_ctrl register definitions 429 */ 430 #define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS 431 #define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN 432 #define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS 433 #define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS 434 #define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS 435 #define LPC32XX_CLKPWR_MSCARD_SDCARD_EN 436 #define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) 437 438 /* 439 * clkpwr_macclk_ctrl register definitions 440 */ 441 #define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 442 #define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 443 #define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 444 #define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 445 #define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN 446 #define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN 447 #define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN 448 449 /* 450 * clkpwr_test_clk_sel register definitions 451 */ 452 #define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK 453 #define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC 454 #define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC 455 #define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK 456 #define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN 457 #define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK 458 #define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK 459 #define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK 460 #define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC 461 #define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 462 #define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK 463 #define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN 464 465 /* 466 * clkpwr_sw_int register definitions 467 */ 468 #define LPC32XX_CLKPWR_SW_INT(n) 469 #define LPC32XX_CLKPWR_SW_GET_ARG(n) 470 471 /* 472 * clkpwr_i2c_clk_ctrl register definitions 473 */ 474 #define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE 475 #define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE 476 #define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE 477 #define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN 478 #define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN 479 480 /* 481 * clkpwr_key_clk_ctrl register definitions 482 */ 483 #define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 484 485 /* 486 * clkpwr_adc_clk_ctrl register definitions 487 */ 488 #define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 489 490 /* 491 * clkpwr_pwm_clk_ctrl register definitions 492 */ 493 #define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) 494 #define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) 495 #define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 496 #define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 497 #define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 498 #define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 499 500 /* 501 * clkpwr_timer_clk_ctrl register definitions 502 */ 503 #define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 504 #define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 505 506 /* 507 * clkpwr_timers_pwms_clk_ctrl_1 register defi 508 */ 509 #define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 510 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 511 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 512 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 513 #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 514 #define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 515 #define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 516 517 /* 518 * clkpwr_spi_clk_ctrl register definitions 519 */ 520 #define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 521 #define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 522 #define LPC32XX_CLKPWR_SPICLK_USE_SPI2 523 #define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 524 #define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 525 #define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 526 #define LPC32XX_CLKPWR_SPICLK_USE_SPI1 527 #define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 528 529 /* 530 * clkpwr_nand_clk_ctrl register definitions 531 */ 532 #define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 533 #define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 534 #define LPC32XX_CLKPWR_NANDCLK_DMA_INT 535 #define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 536 #define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 537 #define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 538 539 /* 540 * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctr 541 * and clkpwr_uart6_clk_ctrl register definiti 542 */ 543 #define LPC32XX_CLKPWR_UART_Y_DIV(y) 544 #define LPC32XX_CLKPWR_UART_X_DIV(x) 545 #define LPC32XX_CLKPWR_UART_USE_HCLK 546 547 /* 548 * clkpwr_irda_clk_ctrl register definitions 549 */ 550 #define LPC32XX_CLKPWR_IRDA_Y_DIV(y) 551 #define LPC32XX_CLKPWR_IRDA_X_DIV(x) 552 553 /* 554 * clkpwr_uart_clk_ctrl register definitions 555 */ 556 #define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN 557 #define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN 558 #define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN 559 #define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN 560 561 /* 562 * clkpwr_dmaclk_ctrl register definitions 563 */ 564 #define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 565 566 /* 567 * clkpwr_autoclock register definitions 568 */ 569 #define LPC32XX_CLKPWR_AUTOCLK_USB_EN 570 #define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 571 #define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 572 573 /* 574 * Interrupt controller register offsets 575 */ 576 #define LPC32XX_INTC_MASK(x) 577 #define LPC32XX_INTC_RAW_STAT(x) 578 #define LPC32XX_INTC_STAT(x) 579 #define LPC32XX_INTC_POLAR(x) 580 #define LPC32XX_INTC_ACT_TYPE(x) 581 #define LPC32XX_INTC_TYPE(x) 582 583 /* 584 * Timer/counter register offsets 585 */ 586 #define LPC32XX_TIMER_IR(x) 587 #define LPC32XX_TIMER_TCR(x) 588 #define LPC32XX_TIMER_TC(x) 589 #define LPC32XX_TIMER_PR(x) 590 #define LPC32XX_TIMER_PC(x) 591 #define LPC32XX_TIMER_MCR(x) 592 #define LPC32XX_TIMER_MR0(x) 593 #define LPC32XX_TIMER_MR1(x) 594 #define LPC32XX_TIMER_MR2(x) 595 #define LPC32XX_TIMER_MR3(x) 596 #define LPC32XX_TIMER_CCR(x) 597 #define LPC32XX_TIMER_CR0(x) 598 #define LPC32XX_TIMER_CR1(x) 599 #define LPC32XX_TIMER_CR2(x) 600 #define LPC32XX_TIMER_CR3(x) 601 #define LPC32XX_TIMER_EMR(x) 602 #define LPC32XX_TIMER_CTCR(x) 603 604 /* 605 * ir register definitions 606 */ 607 #define LPC32XX_TIMER_CNTR_MTCH_BIT(n) 608 #define LPC32XX_TIMER_CNTR_CAPT_BIT(n) 609 610 /* 611 * tcr register definitions 612 */ 613 #define LPC32XX_TIMER_CNTR_TCR_EN 614 #define LPC32XX_TIMER_CNTR_TCR_RESET 615 616 /* 617 * mcr register definitions 618 */ 619 #define LPC32XX_TIMER_CNTR_MCR_MTCH(n) 620 #define LPC32XX_TIMER_CNTR_MCR_RESET(n) 621 #define LPC32XX_TIMER_CNTR_MCR_STOP(n) 622 623 /* 624 * Standard UART register offsets 625 */ 626 #define LPC32XX_UART_DLL_FIFO(x) 627 #define LPC32XX_UART_DLM_IER(x) 628 #define LPC32XX_UART_IIR_FCR(x) 629 #define LPC32XX_UART_LCR(x) 630 #define LPC32XX_UART_MODEM_CTRL(x) 631 #define LPC32XX_UART_LSR(x) 632 #define LPC32XX_UART_MODEM_STATUS(x) 633 #define LPC32XX_UART_RXLEV(x) 634 635 /* 636 * UART control structure offsets 637 */ 638 #define _UCREG(x) 639 640 #define LPC32XX_UARTCTL_CTRL 641 #define LPC32XX_UARTCTL_CLKMODE 642 #define LPC32XX_UARTCTL_CLOOP 643 644 /* 645 * ctrl register definitions 646 */ 647 #define LPC32XX_UART_U3_MD_CTRL_EN 648 #define LPC32XX_UART_IRRX6_INV_EN 649 #define LPC32XX_UART_HDPX_EN 650 #define LPC32XX_UART_UART6_IRDAMOD_BYPASS 651 #define LPC32XX_RT_IRTX6_INV_EN 652 #define LPC32XX_RT_IRTX6_INV_MIR_EN 653 #define LPC32XX_RT_RX_IRPULSE_3_16_115K 654 #define LPC32XX_RT_TX_IRPULSE_3_16_115K 655 #define LPC32XX_UART_U5_ROUTE_TO_USB 656 657 /* 658 * clkmode register definitions 659 */ 660 #define LPC32XX_UART_ENABLED_CLOCKS(n) 661 #define LPC32XX_UART_ENABLED_CLOCK(n, u) 662 #define LPC32XX_UART_ENABLED_CLKS_ANY 663 #define LPC32XX_UART_CLKMODE_OFF 664 #define LPC32XX_UART_CLKMODE_ON 665 #define LPC32XX_UART_CLKMODE_AUTO 666 #define LPC32XX_UART_CLKMODE_MASK(u) 667 #define LPC32XX_UART_CLKMODE_LOAD(m, u) 668 669 /* 670 * GPIO Module Register offsets 671 */ 672 #define _GPREG(x) 673 #define LPC32XX_GPIO_P_MUX_SET 674 #define LPC32XX_GPIO_P_MUX_CLR 675 #define LPC32XX_GPIO_P_MUX_STATE 676 #define LPC32XX_GPIO_P3_MUX_SET 677 #define LPC32XX_GPIO_P3_MUX_CLR 678 #define LPC32XX_GPIO_P3_MUX_STATE 679 #define LPC32XX_GPIO_P0_MUX_SET 680 #define LPC32XX_GPIO_P0_MUX_CLR 681 #define LPC32XX_GPIO_P0_MUX_STATE 682 #define LPC32XX_GPIO_P1_MUX_SET 683 #define LPC32XX_GPIO_P1_MUX_CLR 684 #define LPC32XX_GPIO_P1_MUX_STATE 685 #define LPC32XX_GPIO_P2_MUX_SET 686 #define LPC32XX_GPIO_P2_MUX_CLR 687 #define LPC32XX_GPIO_P2_MUX_STATE 688 689 /* 690 * USB Otg Registers 691 */ 692 #define _OTGREG(x) io_p2v 693 #define LPC32XX_USB_OTG_CLK_CTRL _OTGRE 694 #define LPC32XX_USB_OTG_CLK_STAT _OTGRE 695 696 /* USB OTG CLK CTRL bit defines */ 697 #define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4 698 #define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3 699 #define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2 700 #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1 701 #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0 702 703 /* 704 * Start of virtual addresses for IO devices 705 */ 706 #define IO_BASE 0xF0000000 707 708 /* 709 * This macro relies on fact that for all HW i 710 */ 711 #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000 712 IO_BASE) 713 714 #define io_p2v(x) ((void __iomem *) (uns 715 #define io_v2p(x) ((((x) & 0x0ff00000) < 716 717 #endif 718
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