1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_ 3 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_ 4 5 /* 6 * OMAP3430 Clock Management register bits 7 * 8 * Copyright (C) 2007-2008 Texas Instruments, 9 * Copyright (C) 2007-2008 Nokia Corporation 10 * 11 * Written by Paul Walmsley 12 */ 13 14 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK 15 #define OMAP3430_ST_IVA2_SHIFT 16 #define OMAP3430_CLKTRCTRL_IVA2_MASK 17 #define OMAP3430_CLKACTIVITY_IVA2_MASK 18 #define OMAP3430_CLKTRCTRL_MPU_MASK 19 #define OMAP3430_ST_AES2_SHIFT 20 #define OMAP3430_ST_SHA12_SHIFT 21 #define AM35XX_ST_UART4_SHIFT 22 #define OMAP3430_ST_HDQ_SHIFT 23 #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 24 #define OMAP3430_ST_MAILBOXES_SHIFT 25 #define OMAP3430_ST_SAD2D_SHIFT 26 #define OMAP3430_ST_SDMA_SHIFT 27 #define OMAP3430ES2_ST_USBTLL_SHIFT 28 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK 29 #define OMAP3430_CLKTRCTRL_L4_MASK 30 #define OMAP3430_CLKTRCTRL_L3_MASK 31 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK 32 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK 33 #define OMAP3430_ST_WDT2_SHIFT 34 #define OMAP3430_ST_32KSYNC_SHIFT 35 #define OMAP3430_AUTO_PERIPH_DPLL_MASK 36 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 37 #define OMAP3430_CLKTRCTRL_DSS_MASK 38 #define OMAP3430_CLKTRCTRL_CAM_MASK 39 #define OMAP3430_ST_MCBSP4_SHIFT 40 #define OMAP3430_ST_MCBSP3_SHIFT 41 #define OMAP3430_ST_MCBSP2_SHIFT 42 #define OMAP3430_CLKTRCTRL_PER_MASK 43 #define OMAP3430_CLKTRCTRL_EMU_MASK 44 #define OMAP3430_CLKTRCTRL_NEON_MASK 45 #define OMAP3430ES2_EN_USBHOST2_SHIFT 46 #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 47 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK 48 #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 49 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 50 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 51 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 52 #endif 53
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