1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * OMAP54xx Clock Management register bits 4 * 5 * Copyright (C) 2013 Texas Instruments Incorp 6 * 7 * Paul Walmsley (paul@pwsan.com) 8 * Rajendra Nayak (rnayak@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * 11 * This file is automatically generated from t 12 * We respectfully ask that any modifications 13 * with the public linux-omap@vger.kernel.org 14 * authors above to ensure that the autogenera 15 * up-to-date with the file contents. 16 */ 17 18 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_ 19 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_ 20 21 #define OMAP54XX_ABE_STATDEP_SHIFT 22 #define OMAP54XX_AUTO_DPLL_MODE_MASK 23 #define OMAP54XX_CLKSEL_SHIFT 24 #define OMAP54XX_CLKSEL_WIDTH 25 #define OMAP54XX_CLKSEL_0_0_SHIFT 26 #define OMAP54XX_CLKSEL_0_0_WIDTH 27 #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 28 #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 29 #define OMAP54XX_CLKSEL_DIV_SHIFT 30 #define OMAP54XX_CLKSEL_DIV_WIDTH 31 #define OMAP54XX_CLKSEL_FCLK_SHIFT 32 #define OMAP54XX_CLKSEL_FCLK_WIDTH 33 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 34 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 35 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 36 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 37 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 38 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 39 #define OMAP54XX_CLKSEL_OPP_SHIFT 40 #define OMAP54XX_CLKSEL_OPP_WIDTH 41 #define OMAP54XX_CLKSEL_SOURCE_SHIFT 42 #define OMAP54XX_CLKSEL_SOURCE_WIDTH 43 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHI 44 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WID 45 #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 46 #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 47 #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 48 #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 49 #define OMAP54XX_DIVHS_MASK 50 #define OMAP54XX_DIVHS_0_4_MASK 51 #define OMAP54XX_DIVHS_0_6_MASK 52 #define OMAP54XX_DPLL_DIV_MASK 53 #define OMAP54XX_DPLL_EN_MASK 54 #define OMAP54XX_DPLL_LPMODE_EN_MASK 55 #define OMAP54XX_DPLL_MULT_MASK 56 #define OMAP54XX_DPLL_REGM4XEN_MASK 57 #define OMAP54XX_DPLL_SD_DIV_MASK 58 #define OMAP54XX_DSP_STATDEP_SHIFT 59 #define OMAP54XX_DSS_STATDEP_SHIFT 60 #define OMAP54XX_EMIF_STATDEP_SHIFT 61 #define OMAP54XX_GPU_STATDEP_SHIFT 62 #define OMAP54XX_IPU_STATDEP_SHIFT 63 #define OMAP54XX_IVA_STATDEP_SHIFT 64 #define OMAP54XX_L3INIT_STATDEP_SHIFT 65 #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 66 #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 67 #define OMAP54XX_L4CFG_STATDEP_SHIFT 68 #define OMAP54XX_L4PER_STATDEP_SHIFT 69 #define OMAP54XX_L4SEC_STATDEP_SHIFT 70 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 71 #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 72 #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 73 #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 74 #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 75 #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 76 #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 77 #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHI 78 #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHI 79 #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHI 80 #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIF 81 #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIF 82 #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIF 83 #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 84 #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 85 #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 86 #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 87 #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 88 #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 89 #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 90 #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 91 #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 92 #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 93 #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 94 #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 95 #define OMAP54XX_PAD_CLKS_GATE_SHIFT 96 #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 97 #define OMAP54XX_ST_DPLL_CLK_MASK 98 #define OMAP54XX_SYS_CLKSEL_SHIFT 99 #define OMAP54XX_SYS_CLKSEL_WIDTH 100 #define OMAP54XX_WKUPAON_STATDEP_SHIFT 101 #endif 102
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