1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * DRA7xx CM1 instance offset macros 4 * 5 * Copyright (C) 2013 Texas Instruments Incorp 6 * 7 * Generated by code originally written by: 8 * Paul Walmsley (paul@pwsan.com) 9 * Rajendra Nayak (rnayak@ti.com) 10 * Benoit Cousson (b-cousson@ti.com) 11 * 12 * This file is automatically generated from t 13 * We respectfully ask that any modifications 14 * with the public linux-omap@vger.kernel.org 15 * authors above to ensure that the autogenera 16 * up-to-date with the file contents. 17 */ 18 19 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H 20 #define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H 21 22 /* CM1 base address */ 23 #define DRA7XX_CM_CORE_AON_BASE 0x4a00 24 25 #define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) 26 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON 27 28 /* CM_CORE_AON instances */ 29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 31 #define DRA7XX_CM_CORE_AON_MPU_INST 32 #define DRA7XX_CM_CORE_AON_DSP1_INST 33 #define DRA7XX_CM_CORE_AON_IPU_INST 34 #define DRA7XX_CM_CORE_AON_DSP2_INST 35 #define DRA7XX_CM_CORE_AON_EVE1_INST 36 #define DRA7XX_CM_CORE_AON_EVE2_INST 37 #define DRA7XX_CM_CORE_AON_EVE3_INST 38 #define DRA7XX_CM_CORE_AON_EVE4_INST 39 #define DRA7XX_CM_CORE_AON_RTC_INST 40 #define DRA7XX_CM_CORE_AON_VPE_INST 41 42 /* CM_CORE_AON clockdomain register offsets (f 43 #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 44 #define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 45 #define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 46 #define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 47 #define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 48 #define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 49 #define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 50 #define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 51 #define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 52 #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 53 #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 54 55 #endif 56
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