1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * OMAP3xxx CM module functions
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Copyright (C) 2008-2010, 2012 Texas Instrum
7 * Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17
18 #include "prm2xxx_3xxx.h"
19 #include "cm.h"
20 #include "cm3xxx.h"
21 #include "cm-regbits-34xx.h"
22 #include "clockdomain.h"
23
24 static const u8 omap3xxx_cm_idlest_offs[] = {
25 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_ID
26 };
27
28 /*
29 *
30 */
31
32 static void _write_clktrctrl(u8 c, s16 module,
33 {
34 u32 v;
35
36 v = omap2_cm_read_mod_reg(module, OMAP
37 v &= ~mask;
38 v |= c << __ffs(mask);
39 omap2_cm_write_mod_reg(v, module, OMAP
40 }
41
42 static bool omap3xxx_cm_is_clkdm_in_hwsup(s16
43 {
44 u32 v;
45
46 v = omap2_cm_read_mod_reg(module, OMAP
47 v &= mask;
48 v >>= __ffs(mask);
49
50 return (v == OMAP34XX_CLKSTCTRL_ENABLE
51 }
52
53 static void omap3xxx_cm_clkdm_enable_hwsup(s16
54 {
55 _write_clktrctrl(OMAP34XX_CLKSTCTRL_EN
56 }
57
58 static void omap3xxx_cm_clkdm_disable_hwsup(s1
59 {
60 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DI
61 }
62
63 static void omap3xxx_cm_clkdm_force_sleep(s16
64 {
65 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FO
66 }
67
68 static void omap3xxx_cm_clkdm_force_wakeup(s16
69 {
70 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FO
71 }
72
73 /*
74 *
75 */
76
77 /**
78 * omap3xxx_cm_wait_module_ready - wait for a
79 * @part: PRCM partition, ignored for OMAP3
80 * @prcm_mod: PRCM module offset
81 * @idlest_id: CM_IDLESTx register ID (i.e., x
82 * @idlest_shift: shift of the bit in the CM_I
83 *
84 * Wait for the PRCM to indicate that the modu
85 * (@prcm_mod, @idlest_id, @idlest_shift) is c
86 * success or -EBUSY if the module doesn't ena
87 */
88 static int omap3xxx_cm_wait_module_ready(u8 pa
89 u8 id
90 {
91 int ena = 0, i = 0;
92 u8 cm_idlest_reg;
93 u32 mask;
94
95 if (!idlest_id || (idlest_id > ARRAY_S
96 return -EINVAL;
97
98 cm_idlest_reg = omap3xxx_cm_idlest_off
99
100 mask = 1 << idlest_shift;
101 ena = 0;
102
103 omap_test_timeout(((omap2_cm_read_mod_
104 mask) == ena), MAX
105
106 return (i < MAX_MODULE_READY_TIME) ? 0
107 }
108
109 /**
110 * omap3xxx_cm_split_idlest_reg - split CM_IDL
111 * @idlest_reg: CM_IDLEST* virtual address
112 * @prcm_inst: pointer to an s16 to return the
113 * @idlest_reg_id: pointer to a u8 to return t
114 *
115 * XXX This function is only needed until abso
116 * removed from the OMAP struct clk records.
117 */
118 static int omap3xxx_cm_split_idlest_reg(struct
119 s16 *p
120 u8 *id
121 {
122 unsigned long offs;
123 u8 idlest_offs;
124 int i;
125
126 idlest_offs = idlest_reg->offset & 0xf
127 for (i = 0; i < ARRAY_SIZE(omap3xxx_cm
128 if (idlest_offs == omap3xxx_cm
129 *idlest_reg_id = i + 1
130 break;
131 }
132 }
133
134 if (i == ARRAY_SIZE(omap3xxx_cm_idlest
135 return -EINVAL;
136
137 offs = idlest_reg->offset;
138 offs &= 0xff00;
139 *prcm_inst = offs;
140
141 return 0;
142 }
143
144 /* Clockdomain low-level operations */
145
146 static int omap3xxx_clkdm_add_sleepdep(struct
147 struct
148 {
149 omap2_cm_set_mod_reg_bits((1 << clkdm2
150 clkdm1->pwrd
151 OMAP3430_CM_
152 return 0;
153 }
154
155 static int omap3xxx_clkdm_del_sleepdep(struct
156 struct
157 {
158 omap2_cm_clear_mod_reg_bits((1 << clkd
159 clkdm1->pw
160 OMAP3430_C
161 return 0;
162 }
163
164 static int omap3xxx_clkdm_read_sleepdep(struct
165 struct
166 {
167 return omap2_cm_read_mod_bits_shift(cl
168 OM
169 (1
170 }
171
172 static int omap3xxx_clkdm_clear_all_sleepdeps(
173 {
174 struct clkdm_dep *cd;
175 u32 mask = 0;
176
177 for (cd = clkdm->sleepdep_srcs; cd &&
178 if (!cd->clkdm)
179 continue; /* only happ
180
181 mask |= 1 << cd->clkdm->dep_bi
182 cd->sleepdep_usecount = 0;
183 }
184 omap2_cm_clear_mod_reg_bits(mask, clkd
185 OMAP3430_C
186 return 0;
187 }
188
189 static int omap3xxx_clkdm_sleep(struct clockdo
190 {
191 omap3xxx_cm_clkdm_force_sleep(clkdm->p
192 clkdm->c
193 return 0;
194 }
195
196 static int omap3xxx_clkdm_wakeup(struct clockd
197 {
198 omap3xxx_cm_clkdm_force_wakeup(clkdm->
199 clkdm->
200 return 0;
201 }
202
203 static void omap3xxx_clkdm_allow_idle(struct c
204 {
205 if (clkdm->usecount > 0)
206 clkdm_add_autodeps(clkdm);
207
208 omap3xxx_cm_clkdm_enable_hwsup(clkdm->
209 clkdm->
210 }
211
212 static void omap3xxx_clkdm_deny_idle(struct cl
213 {
214 omap3xxx_cm_clkdm_disable_hwsup(clkdm-
215 clkdm-
216
217 if (clkdm->usecount > 0)
218 clkdm_del_autodeps(clkdm);
219 }
220
221 static int omap3xxx_clkdm_clk_enable(struct cl
222 {
223 bool hwsup = false;
224
225 if (!clkdm->clktrctrl_mask)
226 return 0;
227
228 /*
229 * The CLKDM_MISSING_IDLE_REPORTING fl
230 * more details on the unpleasant prob
231 * around
232 */
233 if ((clkdm->flags & CLKDM_MISSING_IDLE
234 (clkdm->flags & CLKDM_CAN_FORCE_WA
235 omap3xxx_clkdm_wakeup(clkdm);
236 return 0;
237 }
238
239 hwsup = omap3xxx_cm_is_clkdm_in_hwsup(
240
241
242 if (hwsup) {
243 /* Disable HW transitions when
244 omap3xxx_cm_clkdm_disable_hwsu
245
246 clkdm_add_autodeps(clkdm);
247 omap3xxx_cm_clkdm_enable_hwsup
248
249 } else {
250 if (clkdm->flags & CLKDM_CAN_F
251 omap3xxx_clkdm_wakeup(
252 }
253
254 return 0;
255 }
256
257 static int omap3xxx_clkdm_clk_disable(struct c
258 {
259 bool hwsup = false;
260
261 if (!clkdm->clktrctrl_mask)
262 return 0;
263
264 /*
265 * The CLKDM_MISSING_IDLE_REPORTING fl
266 * more details on the unpleasant prob
267 * around
268 */
269 if (clkdm->flags & CLKDM_MISSING_IDLE_
270 !(clkdm->flags & CLKDM_CAN_FORCE_S
271 omap3xxx_cm_clkdm_enable_hwsup
272
273 return 0;
274 }
275
276 hwsup = omap3xxx_cm_is_clkdm_in_hwsup(
277
278
279 if (hwsup) {
280 /* Disable HW transitions when
281 omap3xxx_cm_clkdm_disable_hwsu
282
283 clkdm_del_autodeps(clkdm);
284 omap3xxx_cm_clkdm_enable_hwsup
285
286 } else {
287 if (clkdm->flags & CLKDM_CAN_F
288 omap3xxx_clkdm_sleep(c
289 }
290
291 return 0;
292 }
293
294 struct clkdm_ops omap3_clkdm_operations = {
295 .clkdm_add_wkdep = omap2_clkdm_
296 .clkdm_del_wkdep = omap2_clkdm_
297 .clkdm_read_wkdep = omap2_clkdm_
298 .clkdm_clear_all_wkdeps = omap2_clkdm_
299 .clkdm_add_sleepdep = omap3xxx_clk
300 .clkdm_del_sleepdep = omap3xxx_clk
301 .clkdm_read_sleepdep = omap3xxx_clk
302 .clkdm_clear_all_sleepdeps = omap
303 .clkdm_sleep = omap3xxx_clk
304 .clkdm_wakeup = omap3xxx_clk
305 .clkdm_allow_idle = omap3xxx_clk
306 .clkdm_deny_idle = omap3xxx_clk
307 .clkdm_clk_enable = omap3xxx_clk
308 .clkdm_clk_disable = omap3xxx_clk
309 };
310
311 /*
312 * Context save/restore code - OMAP3 only
313 */
314 struct omap3_cm_regs {
315 u32 iva2_cm_clksel1;
316 u32 iva2_cm_clksel2;
317 u32 cm_sysconfig;
318 u32 sgx_cm_clksel;
319 u32 dss_cm_clksel;
320 u32 cam_cm_clksel;
321 u32 per_cm_clksel;
322 u32 emu_cm_clksel;
323 u32 emu_cm_clkstctrl;
324 u32 pll_cm_autoidle;
325 u32 pll_cm_autoidle2;
326 u32 pll_cm_clksel4;
327 u32 pll_cm_clksel5;
328 u32 pll_cm_clken2;
329 u32 cm_polctrl;
330 u32 iva2_cm_fclken;
331 u32 iva2_cm_clken_pll;
332 u32 core_cm_fclken1;
333 u32 core_cm_fclken3;
334 u32 sgx_cm_fclken;
335 u32 wkup_cm_fclken;
336 u32 dss_cm_fclken;
337 u32 cam_cm_fclken;
338 u32 per_cm_fclken;
339 u32 usbhost_cm_fclken;
340 u32 core_cm_iclken1;
341 u32 core_cm_iclken2;
342 u32 core_cm_iclken3;
343 u32 sgx_cm_iclken;
344 u32 wkup_cm_iclken;
345 u32 dss_cm_iclken;
346 u32 cam_cm_iclken;
347 u32 per_cm_iclken;
348 u32 usbhost_cm_iclken;
349 u32 iva2_cm_autoidle2;
350 u32 mpu_cm_autoidle2;
351 u32 iva2_cm_clkstctrl;
352 u32 mpu_cm_clkstctrl;
353 u32 core_cm_clkstctrl;
354 u32 sgx_cm_clkstctrl;
355 u32 dss_cm_clkstctrl;
356 u32 cam_cm_clkstctrl;
357 u32 per_cm_clkstctrl;
358 u32 neon_cm_clkstctrl;
359 u32 usbhost_cm_clkstctrl;
360 u32 core_cm_autoidle1;
361 u32 core_cm_autoidle2;
362 u32 core_cm_autoidle3;
363 u32 wkup_cm_autoidle;
364 u32 dss_cm_autoidle;
365 u32 cam_cm_autoidle;
366 u32 per_cm_autoidle;
367 u32 usbhost_cm_autoidle;
368 u32 sgx_cm_sleepdep;
369 u32 dss_cm_sleepdep;
370 u32 cam_cm_sleepdep;
371 u32 per_cm_sleepdep;
372 u32 usbhost_cm_sleepdep;
373 u32 cm_clkout_ctrl;
374 };
375
376 static struct omap3_cm_regs cm_context;
377
378 void omap3_cm_save_context(void)
379 {
380 cm_context.iva2_cm_clksel1 =
381 omap2_cm_read_mod_reg(OMAP3430
382 cm_context.iva2_cm_clksel2 =
383 omap2_cm_read_mod_reg(OMAP3430
384 cm_context.cm_sysconfig =
385 omap2_cm_read_mod_reg(OCP_MOD,
386 cm_context.sgx_cm_clksel =
387 omap2_cm_read_mod_reg(OMAP3430
388 cm_context.dss_cm_clksel =
389 omap2_cm_read_mod_reg(OMAP3430
390 cm_context.cam_cm_clksel =
391 omap2_cm_read_mod_reg(OMAP3430
392 cm_context.per_cm_clksel =
393 omap2_cm_read_mod_reg(OMAP3430
394 cm_context.emu_cm_clksel =
395 omap2_cm_read_mod_reg(OMAP3430
396 cm_context.emu_cm_clkstctrl =
397 omap2_cm_read_mod_reg(OMAP3430
398 /*
399 * As per erratum i671, ROM code does
400 * programming scheme if CM_AUTOIDLE_P
401 * In this case, even though this regi
402 * scratchpad contents, we need to res
403 * by ourselves. So, we need to save i
404 */
405 cm_context.pll_cm_autoidle =
406 omap2_cm_read_mod_reg(PLL_MOD,
407 cm_context.pll_cm_autoidle2 =
408 omap2_cm_read_mod_reg(PLL_MOD,
409 cm_context.pll_cm_clksel4 =
410 omap2_cm_read_mod_reg(PLL_MOD,
411 cm_context.pll_cm_clksel5 =
412 omap2_cm_read_mod_reg(PLL_MOD,
413 cm_context.pll_cm_clken2 =
414 omap2_cm_read_mod_reg(PLL_MOD,
415 cm_context.cm_polctrl =
416 omap2_cm_read_mod_reg(OCP_MOD,
417 cm_context.iva2_cm_fclken =
418 omap2_cm_read_mod_reg(OMAP3430
419 cm_context.iva2_cm_clken_pll =
420 omap2_cm_read_mod_reg(OMAP3430
421 cm_context.core_cm_fclken1 =
422 omap2_cm_read_mod_reg(CORE_MOD
423 cm_context.core_cm_fclken3 =
424 omap2_cm_read_mod_reg(CORE_MOD
425 cm_context.sgx_cm_fclken =
426 omap2_cm_read_mod_reg(OMAP3430
427 cm_context.wkup_cm_fclken =
428 omap2_cm_read_mod_reg(WKUP_MOD
429 cm_context.dss_cm_fclken =
430 omap2_cm_read_mod_reg(OMAP3430
431 cm_context.cam_cm_fclken =
432 omap2_cm_read_mod_reg(OMAP3430
433 cm_context.per_cm_fclken =
434 omap2_cm_read_mod_reg(OMAP3430
435 cm_context.usbhost_cm_fclken =
436 omap2_cm_read_mod_reg(OMAP3430
437 cm_context.core_cm_iclken1 =
438 omap2_cm_read_mod_reg(CORE_MOD
439 cm_context.core_cm_iclken2 =
440 omap2_cm_read_mod_reg(CORE_MOD
441 cm_context.core_cm_iclken3 =
442 omap2_cm_read_mod_reg(CORE_MOD
443 cm_context.sgx_cm_iclken =
444 omap2_cm_read_mod_reg(OMAP3430
445 cm_context.wkup_cm_iclken =
446 omap2_cm_read_mod_reg(WKUP_MOD
447 cm_context.dss_cm_iclken =
448 omap2_cm_read_mod_reg(OMAP3430
449 cm_context.cam_cm_iclken =
450 omap2_cm_read_mod_reg(OMAP3430
451 cm_context.per_cm_iclken =
452 omap2_cm_read_mod_reg(OMAP3430
453 cm_context.usbhost_cm_iclken =
454 omap2_cm_read_mod_reg(OMAP3430
455 cm_context.iva2_cm_autoidle2 =
456 omap2_cm_read_mod_reg(OMAP3430
457 cm_context.mpu_cm_autoidle2 =
458 omap2_cm_read_mod_reg(MPU_MOD,
459 cm_context.iva2_cm_clkstctrl =
460 omap2_cm_read_mod_reg(OMAP3430
461 cm_context.mpu_cm_clkstctrl =
462 omap2_cm_read_mod_reg(MPU_MOD,
463 cm_context.core_cm_clkstctrl =
464 omap2_cm_read_mod_reg(CORE_MOD
465 cm_context.sgx_cm_clkstctrl =
466 omap2_cm_read_mod_reg(OMAP3430
467 cm_context.dss_cm_clkstctrl =
468 omap2_cm_read_mod_reg(OMAP3430
469 cm_context.cam_cm_clkstctrl =
470 omap2_cm_read_mod_reg(OMAP3430
471 cm_context.per_cm_clkstctrl =
472 omap2_cm_read_mod_reg(OMAP3430
473 cm_context.neon_cm_clkstctrl =
474 omap2_cm_read_mod_reg(OMAP3430
475 cm_context.usbhost_cm_clkstctrl =
476 omap2_cm_read_mod_reg(OMAP3430
477 OMAP2_CM
478 cm_context.core_cm_autoidle1 =
479 omap2_cm_read_mod_reg(CORE_MOD
480 cm_context.core_cm_autoidle2 =
481 omap2_cm_read_mod_reg(CORE_MOD
482 cm_context.core_cm_autoidle3 =
483 omap2_cm_read_mod_reg(CORE_MOD
484 cm_context.wkup_cm_autoidle =
485 omap2_cm_read_mod_reg(WKUP_MOD
486 cm_context.dss_cm_autoidle =
487 omap2_cm_read_mod_reg(OMAP3430
488 cm_context.cam_cm_autoidle =
489 omap2_cm_read_mod_reg(OMAP3430
490 cm_context.per_cm_autoidle =
491 omap2_cm_read_mod_reg(OMAP3430
492 cm_context.usbhost_cm_autoidle =
493 omap2_cm_read_mod_reg(OMAP3430
494 cm_context.sgx_cm_sleepdep =
495 omap2_cm_read_mod_reg(OMAP3430
496 OMAP3430
497 cm_context.dss_cm_sleepdep =
498 omap2_cm_read_mod_reg(OMAP3430
499 cm_context.cam_cm_sleepdep =
500 omap2_cm_read_mod_reg(OMAP3430
501 cm_context.per_cm_sleepdep =
502 omap2_cm_read_mod_reg(OMAP3430
503 cm_context.usbhost_cm_sleepdep =
504 omap2_cm_read_mod_reg(OMAP3430
505 OMAP3430
506 cm_context.cm_clkout_ctrl =
507 omap2_cm_read_mod_reg(OMAP3430
508 OMAP3_CM
509 }
510
511 void omap3_cm_restore_context(void)
512 {
513 omap2_cm_write_mod_reg(cm_context.iva2
514 CM_CLKSEL1);
515 omap2_cm_write_mod_reg(cm_context.iva2
516 CM_CLKSEL2);
517 omap2_cm_write_mod_reg(cm_context.cm_s
518 OMAP3430_CM_SYS
519 omap2_cm_write_mod_reg(cm_context.sgx_
520 CM_CLKSEL);
521 omap2_cm_write_mod_reg(cm_context.dss_
522 CM_CLKSEL);
523 omap2_cm_write_mod_reg(cm_context.cam_
524 CM_CLKSEL);
525 omap2_cm_write_mod_reg(cm_context.per_
526 CM_CLKSEL);
527 omap2_cm_write_mod_reg(cm_context.emu_
528 CM_CLKSEL1);
529 omap2_cm_write_mod_reg(cm_context.emu_
530 OMAP2_CM_CLKSTC
531 /*
532 * As per erratum i671, ROM code does
533 * programming scheme if CM_AUTOIDLE_P
534 * In this case, we need to restore AU
535 */
536 omap2_cm_write_mod_reg(cm_context.pll_
537 CM_AUTOIDLE);
538 omap2_cm_write_mod_reg(cm_context.pll_
539 CM_AUTOIDLE2);
540 omap2_cm_write_mod_reg(cm_context.pll_
541 OMAP3430ES2_CM_
542 omap2_cm_write_mod_reg(cm_context.pll_
543 OMAP3430ES2_CM_
544 omap2_cm_write_mod_reg(cm_context.pll_
545 OMAP3430ES2_CM_
546 omap2_cm_write_mod_reg(cm_context.cm_p
547 OMAP3430_CM_POL
548 omap2_cm_write_mod_reg(cm_context.iva2
549 CM_FCLKEN);
550 omap2_cm_write_mod_reg(cm_context.iva2
551 OMAP3430_CM_CLK
552 omap2_cm_write_mod_reg(cm_context.core
553 CM_FCLKEN1);
554 omap2_cm_write_mod_reg(cm_context.core
555 OMAP3430ES2_CM_
556 omap2_cm_write_mod_reg(cm_context.sgx_
557 CM_FCLKEN);
558 omap2_cm_write_mod_reg(cm_context.wkup
559 omap2_cm_write_mod_reg(cm_context.dss_
560 CM_FCLKEN);
561 omap2_cm_write_mod_reg(cm_context.cam_
562 CM_FCLKEN);
563 omap2_cm_write_mod_reg(cm_context.per_
564 CM_FCLKEN);
565 omap2_cm_write_mod_reg(cm_context.usbh
566 OMAP3430ES2_USB
567 omap2_cm_write_mod_reg(cm_context.core
568 CM_ICLKEN1);
569 omap2_cm_write_mod_reg(cm_context.core
570 CM_ICLKEN2);
571 omap2_cm_write_mod_reg(cm_context.core
572 CM_ICLKEN3);
573 omap2_cm_write_mod_reg(cm_context.sgx_
574 CM_ICLKEN);
575 omap2_cm_write_mod_reg(cm_context.wkup
576 omap2_cm_write_mod_reg(cm_context.dss_
577 CM_ICLKEN);
578 omap2_cm_write_mod_reg(cm_context.cam_
579 CM_ICLKEN);
580 omap2_cm_write_mod_reg(cm_context.per_
581 CM_ICLKEN);
582 omap2_cm_write_mod_reg(cm_context.usbh
583 OMAP3430ES2_USB
584 omap2_cm_write_mod_reg(cm_context.iva2
585 CM_AUTOIDLE2);
586 omap2_cm_write_mod_reg(cm_context.mpu_
587 CM_AUTOIDLE2);
588 omap2_cm_write_mod_reg(cm_context.iva2
589 OMAP2_CM_CLKSTC
590 omap2_cm_write_mod_reg(cm_context.mpu_
591 OMAP2_CM_CLKSTC
592 omap2_cm_write_mod_reg(cm_context.core
593 OMAP2_CM_CLKSTC
594 omap2_cm_write_mod_reg(cm_context.sgx_
595 OMAP2_CM_CLKSTC
596 omap2_cm_write_mod_reg(cm_context.dss_
597 OMAP2_CM_CLKSTC
598 omap2_cm_write_mod_reg(cm_context.cam_
599 OMAP2_CM_CLKSTC
600 omap2_cm_write_mod_reg(cm_context.per_
601 OMAP2_CM_CLKSTC
602 omap2_cm_write_mod_reg(cm_context.neon
603 OMAP2_CM_CLKSTC
604 omap2_cm_write_mod_reg(cm_context.usbh
605 OMAP3430ES2_USB
606 omap2_cm_write_mod_reg(cm_context.core
607 CM_AUTOIDLE1);
608 omap2_cm_write_mod_reg(cm_context.core
609 CM_AUTOIDLE2);
610 omap2_cm_write_mod_reg(cm_context.core
611 CM_AUTOIDLE3);
612 omap2_cm_write_mod_reg(cm_context.wkup
613 CM_AUTOIDLE);
614 omap2_cm_write_mod_reg(cm_context.dss_
615 CM_AUTOIDLE);
616 omap2_cm_write_mod_reg(cm_context.cam_
617 CM_AUTOIDLE);
618 omap2_cm_write_mod_reg(cm_context.per_
619 CM_AUTOIDLE);
620 omap2_cm_write_mod_reg(cm_context.usbh
621 OMAP3430ES2_USB
622 omap2_cm_write_mod_reg(cm_context.sgx_
623 OMAP3430_CM_SLE
624 omap2_cm_write_mod_reg(cm_context.dss_
625 OMAP3430_CM_SLE
626 omap2_cm_write_mod_reg(cm_context.cam_
627 OMAP3430_CM_SLE
628 omap2_cm_write_mod_reg(cm_context.per_
629 OMAP3430_CM_SLE
630 omap2_cm_write_mod_reg(cm_context.usbh
631 OMAP3430ES2_USB
632 omap2_cm_write_mod_reg(cm_context.cm_c
633 OMAP3_CM_CLKOUT
634 }
635
636 void omap3_cm_save_scratchpad_contents(u32 *pt
637 {
638 *ptr++ = omap2_cm_read_mod_reg(CORE_MO
639 *ptr++ = omap2_cm_read_mod_reg(WKUP_MO
640 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD
641
642 /*
643 * As per erratum i671, ROM code does
644 * programming scheme if CM_AUTOIDLE_P
645 * Then, in any case, clear these bit
646 */
647 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD
648 ~OMAP3430_AUTO_PERIPH_DPLL_MAS
649 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD
650 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD
651 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD
652 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD
653 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD
654 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD
655 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD
656 }
657
658 /*
659 *
660 */
661
662 static const struct cm_ll_data omap3xxx_cm_ll_
663 .split_idlest_reg = &omap3xxx_cm
664 .wait_module_ready = &omap3xxx_cm
665 };
666
667 int __init omap3xxx_cm_init(const struct omap_
668 {
669 omap2_clk_legacy_provider_init(TI_CLKM
670 OMAP343
671 return cm_register(&omap3xxx_cm_ll_dat
672 }
673
674 static void __exit omap3xxx_cm_exit(void)
675 {
676 cm_unregister(&omap3xxx_cm_ll_data);
677 }
678 __exitcall(omap3xxx_cm_exit);
679
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