1 /* 1
2 * arch/arm/mach-omap2/control.h
3 *
4 * OMAP2/3/4 System Control Module definitions
5 *
6 * Copyright (C) 2007-2010 Texas Instruments,
7 * Copyright (C) 2007-2008, 2010 Nokia Corpora
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redi
12 * it under the terms of the GNU General Publi
13 * the Free Software Foundation.
14 */
15
16 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
17 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
18
19 #include "am33xx.h"
20
21 #ifndef __ASSEMBLY__
22 #define OMAP242X_CTRL_REGADDR(reg)
23 OMAP2_L4_IO_ADDRESS(OMAP242X_C
24 #define OMAP243X_CTRL_REGADDR(reg)
25 OMAP2_L4_IO_ADDRESS(OMAP243X_C
26 #define OMAP343X_CTRL_REGADDR(reg)
27 OMAP2_L4_IO_ADDRESS(OMAP343X_C
28 #define AM33XX_CTRL_REGADDR(reg)
29 AM33XX_L4_WK_IO_ADDRESS(AM33XX
30 #else
31 #define OMAP242X_CTRL_REGADDR(reg)
32 OMAP2_L4_IO_ADDRESS(OMAP242X_C
33 #define OMAP243X_CTRL_REGADDR(reg)
34 OMAP2_L4_IO_ADDRESS(OMAP243X_C
35 #define OMAP343X_CTRL_REGADDR(reg)
36 OMAP2_L4_IO_ADDRESS(OMAP343X_C
37 #define AM33XX_CTRL_REGADDR(reg)
38 AM33XX_L4_WK_IO_ADDRESS(AM33XX
39 #endif /* __ASSEMBLY__ */
40
41 /*
42 * As elsewhere, the "OMAP2_" prefix indicates
43 * OMAP24XX and OMAP34XX.
44 */
45
46 /* Control submodule offsets */
47
48 #define OMAP2_CONTROL_INTERFACE 0x000
49 #define OMAP2_CONTROL_PADCONFS 0x030
50 #define OMAP2_CONTROL_GENERAL 0x270
51 #define OMAP343X_CONTROL_MEM_WKUP 0x600
52 #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
53 #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
54
55 /* TI81XX spefic control submodules */
56 #define TI81XX_CONTROL_DEVBOOT 0x040
57 #define TI81XX_CONTROL_DEVCONF 0x600
58
59 /* Control register offsets - read/write with
60
61 #define OMAP2_CONTROL_SYSCONFIG (OMAP2
62
63 /* CONTROL_GENERAL register offsets common to
64 #define OMAP2_CONTROL_DEVCONF0 (OMAP2
65 #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2
66 #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2
67 #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2
68 #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2
69 #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2
70 #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2
71 #define OMAP2_CONTROL_SEC_CTRL (OMAP2
72 #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2
73 #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2
74 #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2
75 #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2
76
77 /* 242x-only CONTROL_GENERAL register offsets
78 #define OMAP242X_CONTROL_DEVCONF OMAP2_
79 #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2
80
81 /* 243x-only CONTROL_GENERAL register offsets
82 /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same
83 #define OMAP243X_CONTROL_DEVCONF1 (OMAP2
84 #define OMAP243X_CONTROL_CSIRXFE (OMAP2
85 #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2
86 #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2
87 #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2
88 #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2
89
90 /* 24xx-only CONTROL_GENERAL register offsets
91 #define OMAP24XX_CONTROL_DEBOBS (OMAP2
92 #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2
93 #define OMAP24XX_CONTROL_SEC_TEST (OMAP2
94 #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2
95 #define OMAP24XX_CONTROL_PSA_CMD (OMAP2
96 #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2
97 #define OMAP24XX_CONTROL_SEC_EMU (OMAP2
98 #define OMAP24XX_CONTROL_SEC_TAP (OMAP2
99 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD
100 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD
101 #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD
102 #define OMAP24XX_CONTROL_SEC_STATUS
103 #define OMAP24XX_CONTROL_SEC_ERR_STATUS
104 #define OMAP24XX_CONTROL_STATUS
105 #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATU
106 #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2
107 #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2
108 #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2
109 #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2
110 #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2
111 #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2
112 #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2
113 #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2
114 #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2
115 #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2
116 #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2
117 #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2
118 #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2
119 #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2
120 #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2
121 #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2
122
123 #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP
124
125 /* 34xx-only CONTROL_GENERAL register offsets
126 #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2
127 #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2
128 #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2
129 #define OMAP343X_CONTROL_DEVCONF1 (OMAP2
130 #define OMAP343X_CONTROL_CSIRXFE
131 #define OMAP343X_CONTROL_SEC_STATUS
132 #define OMAP343X_CONTROL_SEC_ERR_STATUS
133 #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG
134 #define OMAP343X_CONTROL_STATUS
135 #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATU
136 #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2
137 #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2
138 #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2
139 #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2
140 #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2
141 #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2
142 #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2
143 #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2
144 #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2
145 #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2
146 #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2
147 #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2
148 #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2
149 #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2
150 #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2
151 #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2
152 #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2
153 #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2
154 #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2
155 #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2
156 #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2
157 #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2
158 #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2
159 #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2
160 #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2
161 #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2
162 #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2
163 #define OMAP343X_CONTROL_FUSE_SR (OMAP2
164 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2
165 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2
166 #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2
167 + ((i)
168 #define OMAP343X_CONTROL_PROG_IO0 (OMAP2
169 #define OMAP343X_CONTROL_PROG_IO1 (OMAP2
170 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING
171 #define OMAP343X_CONTROL_CORE_DPLL_SPREADING
172 #define OMAP343X_CONTROL_PER_DPLL_SPREADING
173 #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADIN
174 #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2
175 #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2
176 #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2
177 #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2
178 #define OMAP343X_CONTROL_CSI (OMAP2
179
180 /* OMAP3630 only CONTROL_GENERAL register offs
181 #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1
182 #define OMAP3630_CONTROL_FUSE_OPP50_VDD1
183 #define OMAP3630_CONTROL_FUSE_OPP100_VDD1
184 #define OMAP3630_CONTROL_FUSE_OPP120_VDD1
185 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2
186 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2
187 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL
188
189 /* OMAP44xx control efuse offsets */
190 #define OMAP44XX_CONTROL_FUSE_IVA_OPP50
191 #define OMAP44XX_CONTROL_FUSE_IVA_OPP100
192 #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO
193 #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO
194 #define OMAP44XX_CONTROL_FUSE_MPU_OPP50
195 #define OMAP44XX_CONTROL_FUSE_MPU_OPP100
196 #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO
197 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO
198 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB
199 #define OMAP44XX_CONTROL_FUSE_CORE_OPP50
200 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100
201 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV
202
203 /* AM35XX only CONTROL_GENERAL register offset
204 #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2
205 #define AM35XX_CONTROL_DEVCONF2 (OMAP2
206 #define AM35XX_CONTROL_DEVCONF3 (OMAP2
207 #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2
208 #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2
209 #define AM35XX_CONTROL_IP_SW_RESET (OMAP2
210 #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2
211
212 /* 34xx PADCONF register offsets */
213 #define OMAP343X_PADCONF_ETK(i) (OMAP2
214
215 #define OMAP343X_PADCONF_ETK_CLK OMAP34
216 #define OMAP343X_PADCONF_ETK_CTL OMAP34
217 #define OMAP343X_PADCONF_ETK_D0 OMAP34
218 #define OMAP343X_PADCONF_ETK_D1 OMAP34
219 #define OMAP343X_PADCONF_ETK_D2 OMAP34
220 #define OMAP343X_PADCONF_ETK_D3 OMAP34
221 #define OMAP343X_PADCONF_ETK_D4 OMAP34
222 #define OMAP343X_PADCONF_ETK_D5 OMAP34
223 #define OMAP343X_PADCONF_ETK_D6 OMAP34
224 #define OMAP343X_PADCONF_ETK_D7 OMAP34
225 #define OMAP343X_PADCONF_ETK_D8 OMAP34
226 #define OMAP343X_PADCONF_ETK_D9 OMAP34
227 #define OMAP343X_PADCONF_ETK_D10 OMAP34
228 #define OMAP343X_PADCONF_ETK_D11 OMAP34
229 #define OMAP343X_PADCONF_ETK_D12 OMAP34
230 #define OMAP343X_PADCONF_ETK_D13 OMAP34
231 #define OMAP343X_PADCONF_ETK_D14 OMAP34
232 #define OMAP343X_PADCONF_ETK_D15 OMAP34
233
234 /* 34xx GENERAL_WKUP register offsets */
235 #define OMAP34XX_CONTROL_WKUP_CTRL (OMAP3
236 #define OMAP36XX_GPIO_IO_PWRDNZ BIT(6)
237
238 #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OM
239
240 #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343
241 #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343
242 #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343
243 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343
244 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343
245
246 /* 36xx-only RTA - Retention till Access contr
247 #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
248 #define OMAP36XX_RTA_DISABLE 0x0
249
250 /* 34xx D2D idle-related pins, handled by PM c
251 #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
252 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
253
254 /* TI81XX CONTROL_DEVBOOT register offsets */
255 #define TI81XX_CONTROL_STATUS (TI81X
256
257 /* TI81XX CONTROL_DEVCONF register offsets */
258 #define TI81XX_CONTROL_DEVICE_ID (TI81X
259
260 /* OMAP4 CONTROL MODULE */
261 #define OMAP4_CTRL_MODULE_PAD_WKUP
262 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C
263 #define OMAP4_CTRL_MODULE_CORE_STATUS
264 #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_I
265 #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR
266 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSI
267 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAM
268
269 /* OMAP4 CONTROL_DSIPHY */
270 #define OMAP4_DSI2_LANEENABLE_SHIFT
271 #define OMAP4_DSI2_LANEENABLE_MASK
272 #define OMAP4_DSI1_LANEENABLE_SHIFT
273 #define OMAP4_DSI1_LANEENABLE_MASK
274 #define OMAP4_DSI1_PIPD_SHIFT
275 #define OMAP4_DSI1_PIPD_MASK
276 #define OMAP4_DSI2_PIPD_SHIFT
277 #define OMAP4_DSI2_PIPD_MASK
278
279 /* OMAP4 CONTROL_CAMERA_RX */
280 #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT
281 #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK
282 #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT
283 #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK
284 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT
285 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK
286 #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT
287 #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK
288 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT
289 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK
290 #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT
291 #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK
292
293 /* OMAP54XX CONTROL STATUS register */
294 #define OMAP5XXX_CONTROL_STATUS
295 #define OMAP5_DEVICETYPE_MASK (0x7 <<
296
297 /* DRA7XX CONTROL CORE BOOTSTRAP */
298 #define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
299 #define DRA7_SPEEDSELECT_MASK (0x3 <
300
301 /*
302 * REVISIT: This list of registers is not comp
303 * that should be added.
304 */
305
306 /*
307 * Control module register bit defines - these
308 * their own regbits file. Some of these will
309 * on the device type (general-purpose, emulat
310 * and the security mode (secure, non-secure,
311 */
312 /* CONTROL_DEVCONF0 bits */
313 #define OMAP2_MMCSDIO1ADPCLKISEL (1 <<
314 #define OMAP24XX_USBSTANDBYCTRL (1 <<
315 #define OMAP2_MCBSP2_CLKS_MASK (1 <<
316 #define OMAP2_MCBSP1_FSR_MASK (1 <<
317 #define OMAP2_MCBSP1_CLKR_MASK (1 <<
318 #define OMAP2_MCBSP1_CLKS_MASK (1 <<
319
320 /* CONTROL_DEVCONF1 bits */
321 #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 <<
322 #define OMAP2_MMCSDIO2ADPCLKISEL (1 <<
323 #define OMAP2_MCBSP5_CLKS_MASK (1 <<
324 #define OMAP2_MCBSP4_CLKS_MASK (1 <<
325 #define OMAP2_MCBSP3_CLKS_MASK (1 <<
326
327 /* CONTROL_STATUS bits */
328 #define OMAP2_DEVICETYPE_MASK (0x7 <
329 #define OMAP2_SYSBOOT_5_MASK (1 <<
330 #define OMAP2_SYSBOOT_4_MASK (1 <<
331 #define OMAP2_SYSBOOT_3_MASK (1 <<
332 #define OMAP2_SYSBOOT_2_MASK (1 <<
333 #define OMAP2_SYSBOOT_1_MASK (1 <<
334 #define OMAP2_SYSBOOT_0_MASK (1 <<
335
336 /* CONTROL_PBIAS_LITE bits */
337 #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 <<
338 #define OMAP343X_PBIASLITEVMODEERROR1 (1 <<
339 #define OMAP343X_PBIASSPEEDCTRL1 (1 <<
340 #define OMAP343X_PBIASLITEPWRDNZ1 (1 <<
341 #define OMAP343X_PBIASLITEVMODE1 (1 <<
342 #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 <<
343 #define OMAP343X_PBIASLITEVMODEERROR0 (1 <<
344 #define OMAP2_PBIASSPEEDCTRL0 (1 <<
345 #define OMAP2_PBIASLITEPWRDNZ0 (1 <<
346 #define OMAP2_PBIASLITEVMODE0 (1 <<
347
348 /* CONTROL_PROG_IO1 bits */
349 #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 <<
350
351 /* CONTROL_IVA2_BOOTMOD bits */
352 #define OMAP3_IVA2_BOOTMOD_SHIFT 0
353 #define OMAP3_IVA2_BOOTMOD_MASK (0xf <
354 #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 <
355
356 /* CONTROL_PADCONF_X bits */
357 #define OMAP3_PADCONF_WAKEUPEVENT0 (1 <<
358 #define OMAP3_PADCONF_WAKEUPENABLE0 (1 <<
359
360 #define OMAP343X_SCRATCHPAD_ROM (OMAP3
361 #define OMAP343X_SCRATCHPAD (OMAP3
362 #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
363 #define OMAP343X_SCRATCHPAD_REGADDR(reg)
364
365
366 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
367 #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
368 #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
369 #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
370 #define AM35XX_HECC_VBUSP_CLK_SHIFT 3
371 #define AM35XX_USBOTG_FCLK_SHIFT 8
372 #define AM35XX_CPGMAC_FCLK_SHIFT 9
373 #define AM35XX_VPFE_FCLK_SHIFT 10
374
375 /* AM35XX CONTROL_LVL_INTR_CLEAR bits */
376 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
377 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
378 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
379 #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
380 #define AM35XX_USBOTGSS_INT_CLR BIT(4)
381 #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
382 #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
383 #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
384
385 /* AM35XX CONTROL_IP_SW_RESET bits */
386 #define AM35XX_USBOTGSS_SW_RST BIT(0)
387 #define AM35XX_CPGMACSS_SW_RST BIT(1)
388 #define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
389 #define AM35XX_HECC_SW_RST BIT(3)
390 #define AM35XX_VPFE_PCLK_SW_RST BIT(4)
391
392 /* AM33XX CONTROL_STATUS register */
393 #define AM33XX_CONTROL_STATUS 0x040
394 #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
395
396 /* AM33XX CONTROL_STATUS bitfields (partial) *
397 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT
398 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH
399 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK
400
401 /* AM33XX PWMSS Control register */
402 #define AM33XX_PWMSS_TBCLK_CLKCTRL
403
404 /* AM33XX PWMSS Control bitfields */
405 #define AM33XX_PWMSS0_TBCLKEN_SHIFT
406 #define AM33XX_PWMSS1_TBCLKEN_SHIFT
407 #define AM33XX_PWMSS2_TBCLKEN_SHIFT
408
409 /* DEV Feature register to identify AM33XX fea
410 #define AM33XX_DEV_FEATURE 0x604
411 #define AM33XX_SGX_MASK BIT(29
412
413 /* Additional AM33XX/AM43XX CONTROL registers
414 #define AM33XX_CONTROL_SYSCONFIG_OFFSET
415 #define AM33XX_CONTROL_STATUS_OFFSET
416 #define AM43XX_CONTROL_MPU_L2_CTRL_OFFSET
417 #define AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFS
418 #define AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET
419 #define AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET
420 #define AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFF
421 #define AM33XX_CONTROL_BANDGAP_CTRL_OFFSET
422 #define AM33XX_CONTROL_BANDGAP_TRIM_OFFSET
423 #define AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFF
424 #define AM33XX_CONTROL_MOSC_CTRL_OFFSET
425 #define AM33XX_CONTROL_RCOSC_CTRL_OFFSET
426 #define AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET
427 #define AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET
428 #define AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET
429 #define AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET
430 #define AM33XX_CONTROL_MMU_CFG_OFFSET
431 #define AM33XX_CONTROL_TPTC_CFG_OFFSET
432 #define AM33XX_CONTROL_USB_CTRL0_OFFSET
433 #define AM33XX_CONTROL_USB_CTRL1_OFFSET
434 #define AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET
435 #define AM43XX_CONTROL_USB_CTRL2_OFFSET
436 #define AM43XX_CONTROL_GMII_SEL_OFFSET
437 #define AM43XX_CONTROL_MPUSS_CTRL_OFFSET
438 #define AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFS
439 #define AM43XX_CONTROL_PWMSS_CTRL_OFFSET
440 #define AM33XX_CONTROL_MREQPRIO_0_OFFSET
441 #define AM33XX_CONTROL_MREQPRIO_1_OFFSET
442 #define AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSE
443 #define AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSE
444 #define AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSE
445 #define AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSE
446 #define AM33XX_CONTROL_SMRT_CTRL_OFFSET
447 #define AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFS
448 #define AM43XX_CONTROL_CQDETECT_STS_OFFSET
449 #define AM43XX_CONTROL_CQDETECT_STS2_OFFSET
450 #define AM43XX_CONTROL_VTP_CTRL_OFFSET
451 #define AM33XX_CONTROL_VREF_CTRL_OFFSET
452 #define AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET
453 #define AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET
454 #define AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSE
455 #define AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFS
456 #define AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFS
457 #define AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFS
458 #define AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFS
459 #define AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFS
460 #define AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFS
461 #define AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFS
462 #define AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFS
463 #define AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFS
464 #define AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFS
465 #define AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFS
466 #define AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFS
467 #define AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFS
468 #define AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET
469 #define AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET
470 #define AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET
471 #define AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET
472 #define AM33XX_CONTROL_RESET_ISO_OFFSET
473
474 /* CONTROL OMAP STATUS register to identify OM
475 #define OMAP3_CONTROL_OMAP_STATUS 0x044c
476
477 #define OMAP3_SGX_SHIFT 13
478 #define OMAP3_SGX_MASK (3 <<
479 #define FEAT_SGX_FULL 0
480 #define FEAT_SGX_HALF 1
481 #define FEAT_SGX_NONE 2
482
483 #define OMAP3_IVA_SHIFT 12
484 #define OMAP3_IVA_MASK (1 <<
485 #define FEAT_IVA 0
486 #define FEAT_IVA_NONE 1
487
488 #define OMAP3_L2CACHE_SHIFT 10
489 #define OMAP3_L2CACHE_MASK (3 <<
490 #define FEAT_L2CACHE_NONE 0
491 #define FEAT_L2CACHE_64KB 1
492 #define FEAT_L2CACHE_128KB 2
493 #define FEAT_L2CACHE_256KB 3
494
495 #define OMAP3_ISP_SHIFT 5
496 #define OMAP3_ISP_MASK (1 <<
497 #define FEAT_ISP 0
498 #define FEAT_ISP_NONE 1
499
500 #define OMAP3_NEON_SHIFT 4
501 #define OMAP3_NEON_MASK (1 <<
502 #define FEAT_NEON 0
503 #define FEAT_NEON_NONE 1
504
505
506 #ifndef __ASSEMBLY__
507 #ifdef CONFIG_ARCH_OMAP2PLUS
508 extern u8 omap_ctrl_readb(u16 offset);
509 extern u16 omap_ctrl_readw(u16 offset);
510 extern u32 omap_ctrl_readl(u16 offset);
511 extern void omap_ctrl_writeb(u8 val, u16 offse
512 extern void omap_ctrl_writew(u16 val, u16 offs
513 extern void omap_ctrl_writel(u32 val, u16 offs
514
515 extern void omap3_restore(void);
516 extern void omap3_restore_es3(void);
517 extern void omap3_restore_3630(void);
518 extern u32 omap3_arm_context[128];
519 extern void omap3_control_save_context(void);
520 extern void omap3_control_restore_context(void
521 extern void omap3_ctrl_write_boot_mode(u8 boot
522 extern void omap3630_ctrl_disable_rta(void);
523 extern int omap3_ctrl_save_padconf(void);
524 void omap3_ctrl_init(void);
525 int omap2_control_base_init(void);
526 int omap_control_init(void);
527 #else
528 #define omap_ctrl_readb(x) 0
529 #define omap_ctrl_readw(x) 0
530 #define omap_ctrl_readl(x) 0
531 #define omap4_ctrl_pad_readl(x) 0
532 #define omap_ctrl_writeb(x, y) WARN_O
533 #define omap_ctrl_writew(x, y) WARN_O
534 #define omap_ctrl_writel(x, y) WARN_O
535 #define omap4_ctrl_pad_writel(x, y) WARN_O
536 #endif
537 #endif /* __ASSEMBLY__ */
538
539 #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
540
541
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