1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Secondary CPU startup routine source file.
4 *
5 * Copyright (C) 2009-2014 Texas Instruments,
6 *
7 * Author:
8 * Santosh Shilimkar <santosh.shilimkar@ti
9 *
10 * Interface functions needed for the SMP. Thi
11 * realview smp platform.
12 * Copyright (c) 2003 ARM Limited.
13 */
14
15 #include <linux/linkage.h>
16 #include <linux/init.h>
17 #include <asm/assembler.h>
18
19 #include "omap44xx.h"
20
21 /* Physical address needed since MMU not enabl
22 #define AUX_CORE_BOOT0_PA
23 #define API_HYP_ENTRY
24
25 ENTRY(omap_secondary_startup)
26 #ifdef CONFIG_SMP
27 b secondary_startup
28 #else
29 /* Should never get here */
30 again: wfi
31 b again
32 #endif
33 #ENDPROC(omap_secondary_startup)
34
35 /*
36 * OMAP5 specific entry point for secondary CP
37 * code. This routine also provides a holding
38 * secondary core is held until we're ready fo
39 * The primary core will update this flag usin
40 * register AuxCoreBoot0.
41 */
42 ENTRY(omap5_secondary_startup)
43 wait: ldr r2, =AUX_CORE_BOOT0_PA @ read
44 ldr r0, [r2]
45 mov r0, r0, lsr #5
46 mrc p15, 0, r4, c0, c0, 5
47 and r4, r4, #0x0f
48 cmp r0, r4
49 bne wait
50 b omap_secondary_startup
51 ENDPROC(omap5_secondary_startup)
52 /*
53 * Same as omap5_secondary_startup except we c
54 * enable HYP mode first. This is called inst
55 * omap5_secondary_startup if the primary CPU
56 * the boot loader.
57 */
58 .arch armv7-a
59 .arch_extension sec
60 ENTRY(omap5_secondary_hyp_startup)
61 wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read
62 ldr r0, [r2]
63 mov r0, r0, lsr #5
64 mrc p15, 0, r4, c0, c0, 5
65 and r4, r4, #0x0f
66 cmp r0, r4
67 bne wait_2
68 ldr r12, =API_HYP_ENTRY
69 badr r0, hyp_boot
70 smc #0
71 hyp_boot:
72 b omap_secondary_startup
73 ENDPROC(omap5_secondary_hyp_startup)
74 /*
75 * OMAP4 specific entry point for secondary CP
76 * code. This routine also provides a holding
77 * secondary core is held until we're ready fo
78 * The primary core will update this flag usin
79 * register AuxCoreBoot0.
80 */
81 ENTRY(omap4_secondary_startup)
82 hold: ldr r12,=0x103
83 dsb
84 smc #0 @ read
85 mov r0, r0, lsr #9
86 mrc p15, 0, r4, c0, c0, 5
87 and r4, r4, #0x0f
88 cmp r0, r4
89 bne hold
90
91 /*
92 * we've been released from the wait l
93 * should now contain the SVC stack fo
94 */
95 b omap_secondary_startup
96 ENDPROC(omap4_secondary_startup)
97
98 ENTRY(omap4460_secondary_startup)
99 hold_2: ldr r12,=0x103
100 dsb
101 smc #0 @ read
102 mov r0, r0, lsr #9
103 mrc p15, 0, r4, c0, c0, 5
104 and r4, r4, #0x0f
105 cmp r0, r4
106 bne hold_2
107
108 /*
109 * GIC distributor control register ha
110 * CortexA9 r1pX and r2pX. The Control
111 * banked version is now composed of 2
112 * bit 0 == Secure Enable
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has
115 * Because the ROM Code is based on th
116 * GIC restoration will cause a proble
117 * The workaround must be:
118 * 1) Before doing the CPU1 wakeup, CP
119 * the GIC distributor
120 * 2) CPU1 must re-enable the GIC dist
121 * it's wakeup path.
122 */
123 ldr r1, =OMAP44XX_GIC_DIST_BASE
124 ldr r0, [r1]
125 orr r0, #1
126 str r0, [r1]
127
128 /*
129 * we've been released from the wait l
130 * should now contain the SVC stack fo
131 */
132 b omap_secondary_startup
133 ENDPROC(omap4460_secondary_startup)
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