1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * omap4-sar-layout.h: OMAP4 SAR RAM layout he 4 * 5 * Copyright (C) 2011 Texas Instruments, Inc. 6 * Santosh Shilimkar <santosh.shilimkar@t 7 */ 8 #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H 9 #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H 10 11 /* 12 * SAR BANK offsets from base address OMAP44XX 13 */ 14 #define SAR_BANK1_OFFSET 0x0000 15 #define SAR_BANK2_OFFSET 0x1000 16 #define SAR_BANK3_OFFSET 0x2000 17 #define SAR_BANK4_OFFSET 0x3000 18 19 /* Scratch pad memory offsets from SAR_BANK1 * 20 #define SCU_OFFSET0 21 #define SCU_OFFSET1 22 #define OMAP_TYPE_OFFSET 23 #define L2X0_SAVE_OFFSET0 24 #define L2X0_SAVE_OFFSET1 25 #define L2X0_AUXCTRL_OFFSET 26 #define L2X0_PREFETCH_CTRL_OFFSET 27 28 /* CPUx Wakeup Non-Secure Physical Address off 29 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 30 #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 31 #define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 32 #define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 33 34 #define SAR_BACKUP_STATUS_OFFSET 35 #define SAR_SECURE_RAM_SIZE_OFFSET 36 #define SAR_SECRAM_SAVED_AT_OFFSET 37 38 /* WakeUpGen save restore offset from OMAP44XX 39 #define WAKEUPGENENB_OFFSET_CPU0 40 #define WAKEUPGENENB_SECURE_OFFSET_CPU0 41 #define WAKEUPGENENB_OFFSET_CPU1 42 #define WAKEUPGENENB_SECURE_OFFSET_CPU1 43 #define AUXCOREBOOT0_OFFSET 44 #define AUXCOREBOOT1_OFFSET 45 #define PTMSYNCREQ_MASK_OFFSET 46 #define PTMSYNCREQ_EN_OFFSET 47 #define SAR_BACKUP_STATUS_WAKEUPGEN 48 49 /* WakeUpGen save restore offset from OMAP54XX 50 #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 51 #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 52 #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 53 #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 54 #define OMAP5_AUXCOREBOOT0_OFFSET 55 #define OMAP5_AUXCOREBOOT1_OFFSET 56 #define OMAP5_AMBA_IF_MODE_OFFSET 57 #define OMAP5_SAR_BACKUP_STATUS_OFFSET 58 59 #endif 60
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