1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * AM33XX Power domain data
4 *
5 * Copyright (C) 2011-2012 Texas Instruments I
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10
11 #include "powerdomain.h"
12 #include "prcm-common.h"
13 #include "prm-regbits-33xx.h"
14 #include "prm33xx.h"
15
16 static struct powerdomain gfx_33xx_pwrdm = {
17 .name = "gfx_pwrdm",
18 .voltdm = { .name = "c
19 .prcm_offs = AM33XX_PRM_G
20 .pwrstctrl_offs = AM33XX_PM_GF
21 .pwrstst_offs = AM33XX_PM_GF
22 .pwrsts = PWRSTS_OFF_R
23 .pwrsts_logic_ret = PWRSTS_OFF_R
24 .flags = PWRDM_HAS_LO
25 .banks = 1,
26 .logicretstate_mask = AM33XX_LOGIC
27 .mem_on_mask = {
28 [0] = AM33XX_GFX_M
29 },
30 .mem_ret_mask = {
31 [0] = AM33XX_GFX_M
32 },
33 .mem_pwrst_mask = {
34 [0] = AM33XX_GFX_M
35 },
36 .mem_retst_mask = {
37 [0] = AM33XX_GFX_M
38 },
39 .pwrsts_mem_ret = {
40 [0] = PWRSTS_OFF_R
41 },
42 .pwrsts_mem_on = {
43 [0] = PWRSTS_ON,
44 },
45 };
46
47 static struct powerdomain rtc_33xx_pwrdm = {
48 .name = "rtc_pwrdm",
49 .voltdm = { .name = "r
50 .prcm_offs = AM33XX_PRM_R
51 .pwrstctrl_offs = AM33XX_PM_RT
52 .pwrstst_offs = AM33XX_PM_RT
53 .pwrsts = PWRSTS_ON,
54 .logicretstate_mask = AM33XX_LOGIC
55 };
56
57 static struct powerdomain wkup_33xx_pwrdm = {
58 .name = "wkup_pwrdm"
59 .voltdm = { .name = "c
60 .prcm_offs = AM33XX_PRM_W
61 .pwrstctrl_offs = AM33XX_PM_WK
62 .pwrstst_offs = AM33XX_PM_WK
63 .pwrsts = PWRSTS_ON,
64 .logicretstate_mask = AM33XX_LOGIC
65 };
66
67 static struct powerdomain per_33xx_pwrdm = {
68 .name = "per_pwrdm",
69 .voltdm = { .name = "c
70 .prcm_offs = AM33XX_PRM_P
71 .pwrstctrl_offs = AM33XX_PM_PE
72 .pwrstst_offs = AM33XX_PM_PE
73 .pwrsts = PWRSTS_OFF_R
74 .pwrsts_logic_ret = PWRSTS_OFF_R
75 .flags = PWRDM_HAS_LO
76 .banks = 3,
77 .logicretstate_mask = AM33XX_LOGIC
78 .mem_on_mask = {
79 [0] = AM33XX_PRUSS
80 [1] = AM33XX_PER_M
81 [2] = AM33XX_RAM_M
82 },
83 .mem_ret_mask = {
84 [0] = AM33XX_PRUSS
85 [1] = AM33XX_PER_M
86 [2] = AM33XX_RAM_M
87 },
88 .mem_pwrst_mask = {
89 [0] = AM33XX_PRUSS
90 [1] = AM33XX_PER_M
91 [2] = AM33XX_RAM_M
92 },
93 .mem_retst_mask = {
94 [0] = AM33XX_PRUSS
95 [1] = AM33XX_PER_M
96 [2] = AM33XX_RAM_M
97 },
98 .pwrsts_mem_ret = {
99 [0] = PWRSTS_OFF_R
100 [1] = PWRSTS_OFF_R
101 [2] = PWRSTS_OFF_R
102 },
103 .pwrsts_mem_on = {
104 [0] = PWRSTS_ON,
105 [1] = PWRSTS_ON,
106 [2] = PWRSTS_ON,
107 },
108 };
109
110 static struct powerdomain mpu_33xx_pwrdm = {
111 .name = "mpu_pwrdm",
112 .voltdm = { .name = "m
113 .prcm_offs = AM33XX_PRM_M
114 .pwrstctrl_offs = AM33XX_PM_MP
115 .pwrstst_offs = AM33XX_PM_MP
116 .pwrsts = PWRSTS_OFF_R
117 .pwrsts_logic_ret = PWRSTS_OFF_R
118 .flags = PWRDM_HAS_LO
119 .banks = 3,
120 .logicretstate_mask = AM33XX_LOGIC
121 .mem_on_mask = {
122 [0] = AM33XX_MPU_L
123 [1] = AM33XX_MPU_L
124 [2] = AM33XX_MPU_R
125 },
126 .mem_ret_mask = {
127 [0] = AM33XX_MPU_L
128 [1] = AM33XX_MPU_L
129 [2] = AM33XX_MPU_R
130 },
131 .mem_pwrst_mask = {
132 [0] = AM33XX_MPU_L
133 [1] = AM33XX_MPU_L
134 [2] = AM33XX_MPU_R
135 },
136 .mem_retst_mask = {
137 [0] = AM33XX_MPU_L
138 [1] = AM33XX_MPU_L
139 [2] = AM33XX_MPU_R
140 },
141 .pwrsts_mem_ret = {
142 [0] = PWRSTS_OFF_R
143 [1] = PWRSTS_OFF_R
144 [2] = PWRSTS_OFF_R
145 },
146 .pwrsts_mem_on = {
147 [0] = PWRSTS_ON,
148 [1] = PWRSTS_ON,
149 [2] = PWRSTS_ON,
150 },
151 };
152
153 static struct powerdomain cefuse_33xx_pwrdm =
154 .name = "cefuse_pwrdm",
155 .voltdm = { .name = "core" },
156 .prcm_offs = AM33XX_PRM_CEFUSE_MO
157 .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWR
158 .pwrstst_offs = AM33XX_PM_CEFUSE_PWR
159 .pwrsts = PWRSTS_OFF_ON,
160 };
161
162 static struct powerdomain *powerdomains_am33xx
163 &gfx_33xx_pwrdm,
164 &rtc_33xx_pwrdm,
165 &wkup_33xx_pwrdm,
166 &per_33xx_pwrdm,
167 &mpu_33xx_pwrdm,
168 &cefuse_33xx_pwrdm,
169 NULL,
170 };
171
172 void __init am33xx_powerdomains_init(void)
173 {
174 pwrdm_register_platform_funcs(&am33xx_
175 pwrdm_register_pwrdms(powerdomains_am3
176 pwrdm_complete_init();
177 }
178
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