1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * OMAP4 Power domains framework
4 *
5 * Copyright (C) 2009-2011 Texas Instruments,
6 * Copyright (C) 2009-2011 Nokia Corporation
7 *
8 * Abhijit Pagare (abhijitpagare@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Paul Walmsley (paul@pwsan.com)
11 *
12 * This file is automatically generated from t
13 * We respectfully ask that any modifications
14 * with the public linux-omap@vger.kernel.org
15 * authors above to ensure that the autogenera
16 * up-to-date with the file contents.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21
22 #include "powerdomain.h"
23
24 #include "prcm-common.h"
25 #include "prcm44xx.h"
26 #include "prm-regbits-44xx.h"
27 #include "prm44xx.h"
28 #include "prcm_mpu44xx.h"
29
30 /* core_44xx_pwrdm: CORE power domain */
31 static struct powerdomain core_44xx_pwrdm = {
32 .name = "core_pwrdm",
33 .voltdm = { .name = "core" }
34 .prcm_offs = OMAP4430_PRM_CORE_
35 .prcm_partition = OMAP4430_PRM_PARTI
36 .pwrsts = PWRSTS_RET_ON,
37 .pwrsts_logic_ret = PWRSTS_OFF_RET,
38 .banks = 5,
39 .pwrsts_mem_ret = {
40 [0] = PWRSTS_OFF, /* cor
41 [1] = PWRSTS_RET, /* cor
42 [2] = PWRSTS_RET, /* cor
43 [3] = PWRSTS_OFF_RET, /* duc
44 [4] = PWRSTS_OFF_RET, /* duc
45 },
46 .pwrsts_mem_on = {
47 [0] = PWRSTS_ON, /* cor
48 [1] = PWRSTS_ON, /* cor
49 [2] = PWRSTS_ON, /* cor
50 [3] = PWRSTS_ON, /* duc
51 [4] = PWRSTS_ON, /* duc
52 },
53 .flags = PWRDM_HAS_LOWPOWER
54 };
55
56 /* gfx_44xx_pwrdm: 3D accelerator power domain
57 static struct powerdomain gfx_44xx_pwrdm = {
58 .name = "gfx_pwrdm",
59 .voltdm = { .name = "core" }
60 .prcm_offs = OMAP4430_PRM_GFX_I
61 .prcm_partition = OMAP4430_PRM_PARTI
62 .pwrsts = PWRSTS_OFF_ON,
63 .banks = 1,
64 .pwrsts_mem_ret = {
65 [0] = PWRSTS_OFF, /* gfx
66 },
67 .pwrsts_mem_on = {
68 [0] = PWRSTS_ON, /* gfx
69 },
70 .flags = PWRDM_HAS_LOWPOWER
71 };
72
73 /* abe_44xx_pwrdm: Audio back end power domain
74 static struct powerdomain abe_44xx_pwrdm = {
75 .name = "abe_pwrdm",
76 .voltdm = { .name = "iva" },
77 .prcm_offs = OMAP4430_PRM_ABE_I
78 .prcm_partition = OMAP4430_PRM_PARTI
79 .pwrsts = PWRSTS_OFF_RET_ON,
80 .pwrsts_logic_ret = PWRSTS_OFF,
81 .banks = 2,
82 .pwrsts_mem_ret = {
83 [0] = PWRSTS_RET, /* aes
84 [1] = PWRSTS_OFF, /* per
85 },
86 .pwrsts_mem_on = {
87 [0] = PWRSTS_ON, /* aes
88 [1] = PWRSTS_ON, /* per
89 },
90 .flags = PWRDM_HAS_LOWPOWER
91 };
92
93 /* dss_44xx_pwrdm: Display subsystem power dom
94 static struct powerdomain dss_44xx_pwrdm = {
95 .name = "dss_pwrdm",
96 .voltdm = { .name = "core" }
97 .prcm_offs = OMAP4430_PRM_DSS_I
98 .prcm_partition = OMAP4430_PRM_PARTI
99 .pwrsts = PWRSTS_OFF_RET_ON,
100 .pwrsts_logic_ret = PWRSTS_OFF,
101 .banks = 1,
102 .pwrsts_mem_ret = {
103 [0] = PWRSTS_OFF, /* dss
104 },
105 .pwrsts_mem_on = {
106 [0] = PWRSTS_ON, /* dss
107 },
108 .flags = PWRDM_HAS_LOWPOWER
109 };
110
111 /* tesla_44xx_pwrdm: Tesla processor power dom
112 static struct powerdomain tesla_44xx_pwrdm = {
113 .name = "tesla_pwrdm",
114 .voltdm = { .name = "iva" },
115 .prcm_offs = OMAP4430_PRM_TESLA
116 .prcm_partition = OMAP4430_PRM_PARTI
117 .pwrsts = PWRSTS_OFF_RET_ON,
118 .pwrsts_logic_ret = PWRSTS_OFF_RET,
119 .banks = 3,
120 .pwrsts_mem_ret = {
121 [0] = PWRSTS_RET, /* tes
122 [1] = PWRSTS_OFF_RET, /* tes
123 [2] = PWRSTS_OFF_RET, /* tes
124 },
125 .pwrsts_mem_on = {
126 [0] = PWRSTS_ON, /* tes
127 [1] = PWRSTS_ON, /* tes
128 [2] = PWRSTS_ON, /* tes
129 },
130 .flags = PWRDM_HAS_LOWPOWER
131 };
132
133 /* wkup_44xx_pwrdm: Wake-up power domain */
134 static struct powerdomain wkup_44xx_pwrdm = {
135 .name = "wkup_pwrdm",
136 .voltdm = { .name = "wakeup"
137 .prcm_offs = OMAP4430_PRM_WKUP_
138 .prcm_partition = OMAP4430_PRM_PARTI
139 .pwrsts = PWRSTS_ON,
140 .banks = 1,
141 .pwrsts_mem_ret = {
142 [0] = PWRSTS_OFF, /* wku
143 },
144 .pwrsts_mem_on = {
145 [0] = PWRSTS_ON, /* wku
146 },
147 };
148
149 /* cpu0_44xx_pwrdm: MPU0 processor and Neon co
150 static struct powerdomain cpu0_44xx_pwrdm = {
151 .name = "cpu0_pwrdm",
152 .voltdm = { .name = "mpu" },
153 .prcm_offs = OMAP4430_PRCM_MPU_
154 .prcm_partition = OMAP4430_PRCM_MPU_
155 .pwrsts = PWRSTS_OFF_RET_ON,
156 .pwrsts_logic_ret = PWRSTS_OFF_RET,
157 .banks = 1,
158 .pwrsts_mem_ret = {
159 [0] = PWRSTS_OFF_RET, /* cpu
160 },
161 .pwrsts_mem_on = {
162 [0] = PWRSTS_ON, /* cpu
163 },
164 };
165
166 /* cpu1_44xx_pwrdm: MPU1 processor and Neon co
167 static struct powerdomain cpu1_44xx_pwrdm = {
168 .name = "cpu1_pwrdm",
169 .voltdm = { .name = "mpu" },
170 .prcm_offs = OMAP4430_PRCM_MPU_
171 .prcm_partition = OMAP4430_PRCM_MPU_
172 .pwrsts = PWRSTS_OFF_RET_ON,
173 .pwrsts_logic_ret = PWRSTS_OFF_RET,
174 .banks = 1,
175 .pwrsts_mem_ret = {
176 [0] = PWRSTS_OFF_RET, /* cpu
177 },
178 .pwrsts_mem_on = {
179 [0] = PWRSTS_ON, /* cpu
180 },
181 };
182
183 /* emu_44xx_pwrdm: Emulation power domain */
184 static struct powerdomain emu_44xx_pwrdm = {
185 .name = "emu_pwrdm",
186 .voltdm = { .name = "wakeup"
187 .prcm_offs = OMAP4430_PRM_EMU_I
188 .prcm_partition = OMAP4430_PRM_PARTI
189 .pwrsts = PWRSTS_OFF_ON,
190 .banks = 1,
191 .pwrsts_mem_ret = {
192 [0] = PWRSTS_OFF, /* emu
193 },
194 .pwrsts_mem_on = {
195 [0] = PWRSTS_ON, /* emu
196 },
197 };
198
199 /* mpu_44xx_pwrdm: Modena processor and the Ne
200 static struct powerdomain mpu_44xx_pwrdm = {
201 .name = "mpu_pwrdm",
202 .voltdm = { .name = "mpu" },
203 .prcm_offs = OMAP4430_PRM_MPU_I
204 .prcm_partition = OMAP4430_PRM_PARTI
205 .pwrsts = PWRSTS_RET_ON,
206 .pwrsts_logic_ret = PWRSTS_OFF_RET,
207 .banks = 3,
208 .pwrsts_mem_ret = {
209 [0] = PWRSTS_OFF_RET, /* mpu
210 [1] = PWRSTS_OFF_RET, /* mpu
211 [2] = PWRSTS_RET, /* mpu
212 },
213 .pwrsts_mem_on = {
214 [0] = PWRSTS_ON, /* mpu
215 [1] = PWRSTS_ON, /* mpu
216 [2] = PWRSTS_ON, /* mpu
217 },
218 };
219
220 /* ivahd_44xx_pwrdm: IVA-HD power domain */
221 static struct powerdomain ivahd_44xx_pwrdm = {
222 .name = "ivahd_pwrdm",
223 .voltdm = { .name = "iva" },
224 .prcm_offs = OMAP4430_PRM_IVAHD
225 .prcm_partition = OMAP4430_PRM_PARTI
226 .pwrsts = PWRSTS_OFF_RET_ON,
227 .pwrsts_logic_ret = PWRSTS_OFF,
228 .banks = 4,
229 .pwrsts_mem_ret = {
230 [0] = PWRSTS_OFF, /* hwa
231 [1] = PWRSTS_OFF_RET, /* sl2
232 [2] = PWRSTS_OFF_RET, /* tcm
233 [3] = PWRSTS_OFF_RET, /* tcm
234 },
235 .pwrsts_mem_on = {
236 [0] = PWRSTS_ON, /* hwa
237 [1] = PWRSTS_ON, /* sl2
238 [2] = PWRSTS_ON, /* tcm
239 [3] = PWRSTS_ON, /* tcm
240 },
241 .flags = PWRDM_HAS_LOWPOWER
242 };
243
244 /* cam_44xx_pwrdm: Camera subsystem power doma
245 static struct powerdomain cam_44xx_pwrdm = {
246 .name = "cam_pwrdm",
247 .voltdm = { .name = "core" }
248 .prcm_offs = OMAP4430_PRM_CAM_I
249 .prcm_partition = OMAP4430_PRM_PARTI
250 .pwrsts = PWRSTS_OFF_ON,
251 .banks = 1,
252 .pwrsts_mem_ret = {
253 [0] = PWRSTS_OFF, /* cam
254 },
255 .pwrsts_mem_on = {
256 [0] = PWRSTS_ON, /* cam
257 },
258 .flags = PWRDM_HAS_LOWPOWER
259 };
260
261 /* l3init_44xx_pwrdm: L3 initators pheripheral
262 static struct powerdomain l3init_44xx_pwrdm =
263 .name = "l3init_pwrdm",
264 .voltdm = { .name = "core" }
265 .prcm_offs = OMAP4430_PRM_L3INI
266 .prcm_partition = OMAP4430_PRM_PARTI
267 .pwrsts = PWRSTS_RET_ON,
268 .pwrsts_logic_ret = PWRSTS_OFF_RET,
269 .banks = 1,
270 .pwrsts_mem_ret = {
271 [0] = PWRSTS_OFF, /* l3i
272 },
273 .pwrsts_mem_on = {
274 [0] = PWRSTS_ON, /* l3i
275 },
276 .flags = PWRDM_HAS_LOWPOWER
277 };
278
279 /* l4per_44xx_pwrdm: Target peripherals power
280 static struct powerdomain l4per_44xx_pwrdm = {
281 .name = "l4per_pwrdm",
282 .voltdm = { .name = "core" }
283 .prcm_offs = OMAP4430_PRM_L4PER
284 .prcm_partition = OMAP4430_PRM_PARTI
285 .pwrsts = PWRSTS_RET_ON,
286 .pwrsts_logic_ret = PWRSTS_OFF_RET,
287 .banks = 2,
288 .pwrsts_mem_ret = {
289 [0] = PWRSTS_OFF, /* non
290 [1] = PWRSTS_RET, /* ret
291 },
292 .pwrsts_mem_on = {
293 [0] = PWRSTS_ON, /* non
294 [1] = PWRSTS_ON, /* ret
295 },
296 .flags = PWRDM_HAS_LOWPOWER
297 };
298
299 /*
300 * always_on_core_44xx_pwrdm: Always ON logic
301 * domain
302 */
303 static struct powerdomain always_on_core_44xx_
304 .name = "always_on_core_pw
305 .voltdm = { .name = "core" }
306 .prcm_offs = OMAP4430_PRM_ALWAY
307 .prcm_partition = OMAP4430_PRM_PARTI
308 .pwrsts = PWRSTS_ON,
309 };
310
311 /* cefuse_44xx_pwrdm: Customer efuse controlle
312 static struct powerdomain cefuse_44xx_pwrdm =
313 .name = "cefuse_pwrdm",
314 .voltdm = { .name = "core" }
315 .prcm_offs = OMAP4430_PRM_CEFUS
316 .prcm_partition = OMAP4430_PRM_PARTI
317 .pwrsts = PWRSTS_OFF_ON,
318 .flags = PWRDM_HAS_LOWPOWER
319 };
320
321 /*
322 * The following power domains are not under S
323 *
324 * always_on_iva
325 * always_on_mpu
326 * stdefuse
327 */
328
329 /* As powerdomains are added or removed above,
330 static struct powerdomain *powerdomains_omap44
331 &core_44xx_pwrdm,
332 &gfx_44xx_pwrdm,
333 &abe_44xx_pwrdm,
334 &dss_44xx_pwrdm,
335 &tesla_44xx_pwrdm,
336 &wkup_44xx_pwrdm,
337 &cpu0_44xx_pwrdm,
338 &cpu1_44xx_pwrdm,
339 &emu_44xx_pwrdm,
340 &mpu_44xx_pwrdm,
341 &ivahd_44xx_pwrdm,
342 &cam_44xx_pwrdm,
343 &l3init_44xx_pwrdm,
344 &l4per_44xx_pwrdm,
345 &always_on_core_44xx_pwrdm,
346 &cefuse_44xx_pwrdm,
347 NULL
348 };
349
350 void __init omap44xx_powerdomains_init(void)
351 {
352 pwrdm_register_platform_funcs(&omap4_p
353 pwrdm_register_pwrdms(powerdomains_oma
354 pwrdm_complete_init();
355 }
356
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