1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
3 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
4
5 /*
6 * OMAP2/3 PRCM base and module definitions
7 *
8 * Copyright (C) 2007-2009, 2011 Texas Instrum
9 * Copyright (C) 2007-2009 Nokia Corporation
10 *
11 * Written by Paul Walmsley
12 */
13
14 /* Module offsets from both CM_BASE & PRM_BASE
15
16 /*
17 * Offsets that are the same on 24xx and 34xx
18 *
19 * Technically, in terms of the TRM, OCP_MOD i
20 * CCR_MOD on 3430; and GFX_MOD only exists <
21 */
22 #define OCP_MOD
23 #define MPU_MOD
24 #define CORE_MOD
25 #define GFX_MOD
26 #define WKUP_MOD
27 #define PLL_MOD
28
29
30 /* Chip-specific module offsets */
31 #define OMAP24XX_GR_MOD
32 #define OMAP24XX_DSP_MOD
33
34 #define OMAP2430_MDM_MOD
35
36 /* IVA2 module is < base on 3430 */
37 #define OMAP3430_IVA2_MOD
38 #define OMAP3430ES2_SGX_MOD
39 #define OMAP3430_CCR_MOD
40 #define OMAP3430_DSS_MOD
41 #define OMAP3430_CAM_MOD
42 #define OMAP3430_PER_MOD
43 #define OMAP3430_EMU_MOD
44 #define OMAP3430_GR_MOD
45 #define OMAP3430_NEON_MOD
46 #define OMAP3430ES2_USBHOST_MOD
47
48 /*
49 * TI81XX PRM module offsets
50 */
51 #define TI814X_PRM_DSP_MOD
52 #define TI814X_PRM_HDVICP_MOD
53 #define TI814X_PRM_ISP_MOD
54 #define TI814X_PRM_HDVPSS_MOD
55 #define TI814X_PRM_GFX_MOD
56
57 #define TI81XX_PRM_DEVICE_MOD
58 #define TI816X_PRM_ACTIVE_MOD
59 #define TI81XX_PRM_DEFAULT_MOD
60 #define TI816X_PRM_IVAHD0_MOD
61 #define TI816X_PRM_IVAHD1_MOD
62 #define TI816X_PRM_IVAHD2_MOD
63 #define TI816X_PRM_SGX_MOD
64 #define TI81XX_PRM_ALWON_MOD
65
66 /* 24XX register bits shared between CM & PRM
67
68 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_
69 #define OMAP2420_EN_MMC_SHIFT
70 #define OMAP2420_EN_MMC_MASK
71 #define OMAP24XX_EN_UART2_SHIFT
72 #define OMAP24XX_EN_UART2_MASK
73 #define OMAP24XX_EN_UART1_SHIFT
74 #define OMAP24XX_EN_UART1_MASK
75 #define OMAP24XX_EN_MCSPI2_SHIFT
76 #define OMAP24XX_EN_MCSPI2_MASK
77 #define OMAP24XX_EN_MCSPI1_SHIFT
78 #define OMAP24XX_EN_MCSPI1_MASK
79 #define OMAP24XX_EN_MCBSP2_SHIFT
80 #define OMAP24XX_EN_MCBSP2_MASK
81 #define OMAP24XX_EN_MCBSP1_SHIFT
82 #define OMAP24XX_EN_MCBSP1_MASK
83 #define OMAP24XX_EN_GPT12_SHIFT
84 #define OMAP24XX_EN_GPT12_MASK
85 #define OMAP24XX_EN_GPT11_SHIFT
86 #define OMAP24XX_EN_GPT11_MASK
87 #define OMAP24XX_EN_GPT10_SHIFT
88 #define OMAP24XX_EN_GPT10_MASK
89 #define OMAP24XX_EN_GPT9_SHIFT
90 #define OMAP24XX_EN_GPT9_MASK
91 #define OMAP24XX_EN_GPT8_SHIFT
92 #define OMAP24XX_EN_GPT8_MASK
93 #define OMAP24XX_EN_GPT7_SHIFT
94 #define OMAP24XX_EN_GPT7_MASK
95 #define OMAP24XX_EN_GPT6_SHIFT
96 #define OMAP24XX_EN_GPT6_MASK
97 #define OMAP24XX_EN_GPT5_SHIFT
98 #define OMAP24XX_EN_GPT5_MASK
99 #define OMAP24XX_EN_GPT4_SHIFT
100 #define OMAP24XX_EN_GPT4_MASK
101 #define OMAP24XX_EN_GPT3_SHIFT
102 #define OMAP24XX_EN_GPT3_MASK
103 #define OMAP24XX_EN_GPT2_SHIFT
104 #define OMAP24XX_EN_GPT2_MASK
105 #define OMAP2420_EN_VLYNQ_SHIFT
106 #define OMAP2420_EN_VLYNQ_MASK
107
108 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_
109 #define OMAP2430_EN_GPIO5_SHIFT
110 #define OMAP2430_EN_GPIO5_MASK
111 #define OMAP2430_EN_MCSPI3_SHIFT
112 #define OMAP2430_EN_MCSPI3_MASK
113 #define OMAP2430_EN_MMCHS2_SHIFT
114 #define OMAP2430_EN_MMCHS2_MASK
115 #define OMAP2430_EN_MMCHS1_SHIFT
116 #define OMAP2430_EN_MMCHS1_MASK
117 #define OMAP24XX_EN_UART3_SHIFT
118 #define OMAP24XX_EN_UART3_MASK
119 #define OMAP24XX_EN_USB_SHIFT
120 #define OMAP24XX_EN_USB_MASK
121
122 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits
123 #define OMAP2430_EN_MDM_INTC_SHIFT
124 #define OMAP2430_EN_MDM_INTC_MASK
125 #define OMAP2430_EN_USBHS_SHIFT
126 #define OMAP2430_EN_USBHS_MASK
127 #define OMAP24XX_EN_GPMC_SHIFT
128 #define OMAP24XX_EN_GPMC_MASK
129
130 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits
131 #define OMAP2420_ST_MMC_SHIFT
132 #define OMAP2420_ST_MMC_MASK
133 #define OMAP24XX_ST_UART2_SHIFT
134 #define OMAP24XX_ST_UART2_MASK
135 #define OMAP24XX_ST_UART1_SHIFT
136 #define OMAP24XX_ST_UART1_MASK
137 #define OMAP24XX_ST_MCSPI2_SHIFT
138 #define OMAP24XX_ST_MCSPI2_MASK
139 #define OMAP24XX_ST_MCSPI1_SHIFT
140 #define OMAP24XX_ST_MCSPI1_MASK
141 #define OMAP24XX_ST_MCBSP2_SHIFT
142 #define OMAP24XX_ST_MCBSP2_MASK
143 #define OMAP24XX_ST_MCBSP1_SHIFT
144 #define OMAP24XX_ST_MCBSP1_MASK
145 #define OMAP24XX_ST_GPT12_SHIFT
146 #define OMAP24XX_ST_GPT12_MASK
147 #define OMAP24XX_ST_GPT11_SHIFT
148 #define OMAP24XX_ST_GPT11_MASK
149 #define OMAP24XX_ST_GPT10_SHIFT
150 #define OMAP24XX_ST_GPT10_MASK
151 #define OMAP24XX_ST_GPT9_SHIFT
152 #define OMAP24XX_ST_GPT9_MASK
153 #define OMAP24XX_ST_GPT8_SHIFT
154 #define OMAP24XX_ST_GPT8_MASK
155 #define OMAP24XX_ST_GPT7_SHIFT
156 #define OMAP24XX_ST_GPT7_MASK
157 #define OMAP24XX_ST_GPT6_SHIFT
158 #define OMAP24XX_ST_GPT6_MASK
159 #define OMAP24XX_ST_GPT5_SHIFT
160 #define OMAP24XX_ST_GPT5_MASK
161 #define OMAP24XX_ST_GPT4_SHIFT
162 #define OMAP24XX_ST_GPT4_MASK
163 #define OMAP24XX_ST_GPT3_SHIFT
164 #define OMAP24XX_ST_GPT3_MASK
165 #define OMAP24XX_ST_GPT2_SHIFT
166 #define OMAP24XX_ST_GPT2_MASK
167 #define OMAP2420_ST_VLYNQ_SHIFT
168 #define OMAP2420_ST_VLYNQ_MASK
169
170 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits
171 #define OMAP2430_ST_MDM_INTC_SHIFT
172 #define OMAP2430_ST_MDM_INTC_MASK
173 #define OMAP2430_ST_GPIO5_SHIFT
174 #define OMAP2430_ST_GPIO5_MASK
175 #define OMAP2430_ST_MCSPI3_SHIFT
176 #define OMAP2430_ST_MCSPI3_MASK
177 #define OMAP2430_ST_MMCHS2_SHIFT
178 #define OMAP2430_ST_MMCHS2_MASK
179 #define OMAP2430_ST_MMCHS1_SHIFT
180 #define OMAP2430_ST_MMCHS1_MASK
181 #define OMAP2430_ST_USBHS_SHIFT
182 #define OMAP2430_ST_USBHS_MASK
183 #define OMAP24XX_ST_UART3_SHIFT
184 #define OMAP24XX_ST_UART3_MASK
185 #define OMAP24XX_ST_USB_SHIFT
186 #define OMAP24XX_ST_USB_MASK
187
188 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKU
189 #define OMAP24XX_EN_GPIOS_SHIFT
190 #define OMAP24XX_EN_GPIOS_MASK
191 #define OMAP24XX_EN_GPT1_SHIFT
192 #define OMAP24XX_EN_GPT1_MASK
193
194 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
195 #define OMAP24XX_ST_GPIOS_SHIFT
196 #define OMAP24XX_ST_GPIOS_MASK
197 #define OMAP24XX_ST_32KSYNC_SHIFT
198 #define OMAP24XX_ST_32KSYNC_MASK
199 #define OMAP24XX_ST_GPT1_SHIFT
200 #define OMAP24XX_ST_GPT1_MASK
201
202 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits *
203 #define OMAP2430_ST_MDM_SHIFT
204 #define OMAP2430_ST_MDM_MASK
205
206
207 /* 3430 register bits shared between CM & PRM
208
209 /* CM_REVISION, PRM_REVISION shared bits */
210 #define OMAP3430_REV_SHIFT
211 #define OMAP3430_REV_MASK
212
213 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
214 #define OMAP3430_AUTOIDLE_MASK
215
216 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_
217 #define OMAP3430_EN_MMC3_MASK
218 #define OMAP3430_EN_MMC3_SHIFT
219 #define OMAP3430_EN_MMC2_MASK
220 #define OMAP3430_EN_MMC2_SHIFT
221 #define OMAP3430_EN_MMC1_MASK
222 #define OMAP3430_EN_MMC1_SHIFT
223 #define AM35XX_EN_UART4_MASK
224 #define AM35XX_EN_UART4_SHIFT
225 #define OMAP3430_EN_MCSPI4_MASK
226 #define OMAP3430_EN_MCSPI4_SHIFT
227 #define OMAP3430_EN_MCSPI3_MASK
228 #define OMAP3430_EN_MCSPI3_SHIFT
229 #define OMAP3430_EN_MCSPI2_MASK
230 #define OMAP3430_EN_MCSPI2_SHIFT
231 #define OMAP3430_EN_MCSPI1_MASK
232 #define OMAP3430_EN_MCSPI1_SHIFT
233 #define OMAP3430_EN_I2C3_MASK
234 #define OMAP3430_EN_I2C3_SHIFT
235 #define OMAP3430_EN_I2C2_MASK
236 #define OMAP3430_EN_I2C2_SHIFT
237 #define OMAP3430_EN_I2C1_MASK
238 #define OMAP3430_EN_I2C1_SHIFT
239 #define OMAP3430_EN_UART2_MASK
240 #define OMAP3430_EN_UART2_SHIFT
241 #define OMAP3430_EN_UART1_MASK
242 #define OMAP3430_EN_UART1_SHIFT
243 #define OMAP3430_EN_GPT11_MASK
244 #define OMAP3430_EN_GPT11_SHIFT
245 #define OMAP3430_EN_GPT10_MASK
246 #define OMAP3430_EN_GPT10_SHIFT
247 #define OMAP3430_EN_MCBSP5_MASK
248 #define OMAP3430_EN_MCBSP5_SHIFT
249 #define OMAP3430_EN_MCBSP1_MASK
250 #define OMAP3430_EN_MCBSP1_SHIFT
251 #define OMAP3430_EN_FSHOSTUSB_MASK
252 #define OMAP3430_EN_FSHOSTUSB_SHIFT
253 #define OMAP3430_EN_D2D_MASK
254 #define OMAP3430_EN_D2D_SHIFT
255
256 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits
257 #define OMAP3430_EN_HSOTGUSB_MASK
258 #define OMAP3430_EN_HSOTGUSB_SHIFT
259
260 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits
261 #define OMAP3430_ST_MMC3_SHIFT
262 #define OMAP3430_ST_MMC3_MASK
263 #define OMAP3430_ST_MMC2_SHIFT
264 #define OMAP3430_ST_MMC2_MASK
265 #define OMAP3430_ST_MMC1_SHIFT
266 #define OMAP3430_ST_MMC1_MASK
267 #define OMAP3430_ST_MCSPI4_SHIFT
268 #define OMAP3430_ST_MCSPI4_MASK
269 #define OMAP3430_ST_MCSPI3_SHIFT
270 #define OMAP3430_ST_MCSPI3_MASK
271 #define OMAP3430_ST_MCSPI2_SHIFT
272 #define OMAP3430_ST_MCSPI2_MASK
273 #define OMAP3430_ST_MCSPI1_SHIFT
274 #define OMAP3430_ST_MCSPI1_MASK
275 #define OMAP3430_ST_I2C3_SHIFT
276 #define OMAP3430_ST_I2C3_MASK
277 #define OMAP3430_ST_I2C2_SHIFT
278 #define OMAP3430_ST_I2C2_MASK
279 #define OMAP3430_ST_I2C1_SHIFT
280 #define OMAP3430_ST_I2C1_MASK
281 #define OMAP3430_ST_UART2_SHIFT
282 #define OMAP3430_ST_UART2_MASK
283 #define OMAP3430_ST_UART1_SHIFT
284 #define OMAP3430_ST_UART1_MASK
285 #define OMAP3430_ST_GPT11_SHIFT
286 #define OMAP3430_ST_GPT11_MASK
287 #define OMAP3430_ST_GPT10_SHIFT
288 #define OMAP3430_ST_GPT10_MASK
289 #define OMAP3430_ST_MCBSP5_SHIFT
290 #define OMAP3430_ST_MCBSP5_MASK
291 #define OMAP3430_ST_MCBSP1_SHIFT
292 #define OMAP3430_ST_MCBSP1_MASK
293 #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT
294 #define OMAP3430ES1_ST_FSHOSTUSB_MASK
295 #define OMAP3430ES1_ST_HSOTGUSB_SHIFT
296 #define OMAP3430ES1_ST_HSOTGUSB_MASK
297 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT
298 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK
299 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
300 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK
301 #define OMAP3430_ST_D2D_SHIFT
302 #define OMAP3430_ST_D2D_MASK
303
304 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKU
305 #define OMAP3430_EN_GPIO1_MASK
306 #define OMAP3430_EN_GPIO1_SHIFT
307 #define OMAP3430_EN_GPT12_MASK
308 #define OMAP3430_EN_GPT12_SHIFT
309 #define OMAP3430_EN_GPT1_MASK
310 #define OMAP3430_EN_GPT1_SHIFT
311
312 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
313 #define OMAP3430_EN_SR2_MASK
314 #define OMAP3430_EN_SR2_SHIFT
315 #define OMAP3430_EN_SR1_MASK
316 #define OMAP3430_EN_SR1_SHIFT
317
318 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
319 #define OMAP3430_EN_GPT12_MASK
320 #define OMAP3430_EN_GPT12_SHIFT
321
322 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
323 #define OMAP3430_ST_SR2_SHIFT
324 #define OMAP3430_ST_SR2_MASK
325 #define OMAP3430_ST_SR1_SHIFT
326 #define OMAP3430_ST_SR1_MASK
327 #define OMAP3430_ST_GPIO1_SHIFT
328 #define OMAP3430_ST_GPIO1_MASK
329 #define OMAP3430_ST_32KSYNC_SHIFT
330 #define OMAP3430_ST_32KSYNC_MASK
331 #define OMAP3430_ST_GPT12_SHIFT
332 #define OMAP3430_ST_GPT12_MASK
333 #define OMAP3430_ST_GPT1_SHIFT
334 #define OMAP3430_ST_GPT1_MASK
335
336 /*
337 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPD
338 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GF
339 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, P
340 */
341 #define OMAP3430_EN_MPU_MASK
342 #define OMAP3430_EN_MPU_SHIFT
343
344 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER s
345
346 #define OMAP3630_EN_UART4_MASK
347 #define OMAP3630_EN_UART4_SHIFT
348 #define OMAP3430_EN_GPIO6_MASK
349 #define OMAP3430_EN_GPIO6_SHIFT
350 #define OMAP3430_EN_GPIO5_MASK
351 #define OMAP3430_EN_GPIO5_SHIFT
352 #define OMAP3430_EN_GPIO4_MASK
353 #define OMAP3430_EN_GPIO4_SHIFT
354 #define OMAP3430_EN_GPIO3_MASK
355 #define OMAP3430_EN_GPIO3_SHIFT
356 #define OMAP3430_EN_GPIO2_MASK
357 #define OMAP3430_EN_GPIO2_SHIFT
358 #define OMAP3430_EN_UART3_MASK
359 #define OMAP3430_EN_UART3_SHIFT
360 #define OMAP3430_EN_GPT9_MASK
361 #define OMAP3430_EN_GPT9_SHIFT
362 #define OMAP3430_EN_GPT8_MASK
363 #define OMAP3430_EN_GPT8_SHIFT
364 #define OMAP3430_EN_GPT7_MASK
365 #define OMAP3430_EN_GPT7_SHIFT
366 #define OMAP3430_EN_GPT6_MASK
367 #define OMAP3430_EN_GPT6_SHIFT
368 #define OMAP3430_EN_GPT5_MASK
369 #define OMAP3430_EN_GPT5_SHIFT
370 #define OMAP3430_EN_GPT4_MASK
371 #define OMAP3430_EN_GPT4_SHIFT
372 #define OMAP3430_EN_GPT3_MASK
373 #define OMAP3430_EN_GPT3_SHIFT
374 #define OMAP3430_EN_GPT2_MASK
375 #define OMAP3430_EN_GPT2_SHIFT
376
377 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER,
378 /* XXX Possible TI documentation bug: should t
379 * be ST_* bits instead? */
380 #define OMAP3430_EN_MCBSP4_MASK
381 #define OMAP3430_EN_MCBSP4_SHIFT
382 #define OMAP3430_EN_MCBSP3_MASK
383 #define OMAP3430_EN_MCBSP3_SHIFT
384 #define OMAP3430_EN_MCBSP2_MASK
385 #define OMAP3430_EN_MCBSP2_SHIFT
386
387 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
388 #define OMAP3630_ST_UART4_SHIFT
389 #define OMAP3630_ST_UART4_MASK
390 #define OMAP3430_ST_GPIO6_SHIFT
391 #define OMAP3430_ST_GPIO6_MASK
392 #define OMAP3430_ST_GPIO5_SHIFT
393 #define OMAP3430_ST_GPIO5_MASK
394 #define OMAP3430_ST_GPIO4_SHIFT
395 #define OMAP3430_ST_GPIO4_MASK
396 #define OMAP3430_ST_GPIO3_SHIFT
397 #define OMAP3430_ST_GPIO3_MASK
398 #define OMAP3430_ST_GPIO2_SHIFT
399 #define OMAP3430_ST_GPIO2_MASK
400 #define OMAP3430_ST_UART3_SHIFT
401 #define OMAP3430_ST_UART3_MASK
402 #define OMAP3430_ST_GPT9_SHIFT
403 #define OMAP3430_ST_GPT9_MASK
404 #define OMAP3430_ST_GPT8_SHIFT
405 #define OMAP3430_ST_GPT8_MASK
406 #define OMAP3430_ST_GPT7_SHIFT
407 #define OMAP3430_ST_GPT7_MASK
408 #define OMAP3430_ST_GPT6_SHIFT
409 #define OMAP3430_ST_GPT6_MASK
410 #define OMAP3430_ST_GPT5_SHIFT
411 #define OMAP3430_ST_GPT5_MASK
412 #define OMAP3430_ST_GPT4_SHIFT
413 #define OMAP3430_ST_GPT4_MASK
414 #define OMAP3430_ST_GPT3_SHIFT
415 #define OMAP3430_ST_GPT3_MASK
416 #define OMAP3430_ST_GPT2_SHIFT
417 #define OMAP3430_ST_GPT2_MASK
418
419 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MP
420 #define OMAP3430_EN_CORE_SHIFT
421 #define OMAP3430_EN_CORE_MASK
422
423
424
425 /*
426 * Maximum time(us) it takes to output the sig
427 * pad of the I/O ring after asserting WUCLKIN
428 * the actual time at 7 to 8 microseconds on O
429 * microseconds on OMAP4, so this timeout may
430 */
431 #define MAX_IOPAD_LATCH_TIME
432 # ifndef __ASSEMBLER__
433
434 #include <linux/delay.h>
435
436 /**
437 * omap_test_timeout - busy-loop, testing a co
438 * @cond: condition to test until it evaluates
439 * @timeout: maximum number of microseconds in
440 * @index: loop index (integer)
441 *
442 * Loop waiting for @cond to become true or un
443 * microseconds have passed. To use, define s
444 * calling code. After running, if @index ==
445 * timed out.
446 */
447 #define omap_test_timeout(cond, timeout, index
448 ({
449 for (index = 0; index < timeout; index
450 if (cond)
451 break;
452 udelay(1);
453 }
454 })
455
456 /**
457 * struct omap_prcm_irq - describes a PRCM int
458 * @name: a short name describing the interrup
459 * @offset: the bit shift of the interrupt ins
460 * @priority: should this interrupt be handled
461 *
462 * Describes interrupt bits inside the PRM_IRQ
463 * On systems with multiple PRM MPU IRQ regist
464 * the registers are concatenated, so @offset
465 * see omap_prm_irq_handler() for more details
466 * have @priority set to true.
467 */
468 struct omap_prcm_irq {
469 const char *name;
470 unsigned int offset;
471 bool priority;
472 };
473
474 /**
475 * struct omap_prcm_irq_setup - PRCM interrupt
476 * @ack: PRM register offset for the first PRM
477 * @mask: PRM register offset for the first PR
478 * @pm_ctrl: PRM register offset for the PRM_I
479 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_
480 * @nr_irqs: number of entries in the @irqs ar
481 * @irqs: ptr to an array of PRCM interrupt bi
482 * @irq: MPU IRQ asserted when a PRCM interrup
483 * @read_pending_irqs: fn ptr to determine if
484 * @ocp_barrier: fn ptr to force buffered PRM
485 * @save_and_clear_irqen: fn ptr to save and c
486 * @restore_irqen: fn ptr to save and clear IR
487 * @reconfigure_io_chain: fn ptr to reconfigur
488 * @saved_mask: IRQENABLE regs are saved here
489 * @priority_mask: 1 bit per IRQ, set to 1 if
490 * @base_irq: base dynamic IRQ number, returne
491 * @suspended: set to true after Linux suspend
492 * @suspend_save_flag: set to true after IRQ m
493 *
494 * @saved_mask, @priority_mask, @base_irq, @su
495 * @suspend_save_flag are populated dynamicall
496 * specified in static initializers.
497 */
498 struct omap_prcm_irq_setup {
499 u16 ack;
500 u16 mask;
501 u16 pm_ctrl;
502 u8 nr_regs;
503 u8 nr_irqs;
504 const struct omap_prcm_irq *irqs;
505 int irq;
506 void (*read_pending_irqs)(unsigned lon
507 void (*ocp_barrier)(void);
508 void (*save_and_clear_irqen)(u32 *save
509 void (*restore_irqen)(u32 *saved_mask)
510 void (*reconfigure_io_chain)(void);
511 u32 *saved_mask;
512 u32 *priority_mask;
513 int base_irq;
514 bool suspended;
515 bool suspend_save_flag;
516 };
517
518 /* OMAP_PRCM_IRQ: convenience macro for creati
519 #define OMAP_PRCM_IRQ(_name, _offset, _priorit
520 .name = _name,
521 .offset = _offset,
522 .priority = _priority
523 }
524
525 struct omap_domain_base {
526 u32 pa;
527 void __iomem *va;
528 s16 offset;
529 };
530
531 /**
532 * struct omap_prcm_init_data - PRCM driver in
533 * @index: clock memory mapping index to be us
534 * @mem: IO mem pointer for this module
535 * @phys: IO mem physical base address for thi
536 * @offset: module base address offset from th
537 * @flags: PRCM module init flags
538 * @device_inst_offset: device instance offset
539 * @init: low level PRCM init function for thi
540 * @np: device node for this PRCM module
541 */
542 struct omap_prcm_init_data {
543 int index;
544 void __iomem *mem;
545 u32 phys;
546 s16 offset;
547 u16 flags;
548 s32 device_inst_offset;
549 int (*init)(const struct omap_prcm_ini
550 struct device_node *np;
551 };
552
553 extern int omap_prcm_register_chain_handler(
554 struct omap_prcm_irq_setup *irq_setup)
555 extern int omap_prcm_event_to_irq(const char *
556 extern void omap_prcm_irq_prepare(void);
557 extern void omap_prcm_irq_complete(void);
558
559 # endif
560
561 #endif
562
563
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