1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * OMAP44xx PRCM MPU instance offset macros 4 * 5 * Copyright (C) 2010, 2012 Texas Instruments, 6 * Copyright (C) 2010 Nokia Corporation 7 * 8 * Paul Walmsley (paul@pwsan.com) 9 * Rajendra Nayak (rnayak@ti.com) 10 * Benoit Cousson (b-cousson@ti.com) 11 * 12 * This file is automatically generated from t 13 * We respectfully ask that any modifications 14 * with the public linux-omap@vger.kernel.org 15 * authors above to ensure that the autogenera 16 * up-to-date with the file contents. 17 * 18 * XXX This file needs to be updated to align 19 * or "OMAP4430". 20 */ 21 22 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 23 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 24 25 #include "prcm_mpu_44xx_54xx.h" 26 27 #define OMAP4430_PRCM_MPU_BASE 28 29 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) 30 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_ 31 32 /* PRCM_MPU instances */ 33 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 34 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 35 #define OMAP4430_PRCM_MPU_CPU0_INST 36 #define OMAP4430_PRCM_MPU_CPU1_INST 37 38 /* PRCM_MPU clockdomain register offsets (from 39 #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 40 #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 41 42 43 /* 44 * PRCM_MPU 45 * 46 * The PRCM_MPU is a local PRCM inside the MPU 47 * point of view the PRCM_MPU is a single enti 48 * programming model as the global PRCM and th 49 * MOD inside the PRCM 50 */ 51 52 /* PRCM_MPU.OCP_SOCKET_PRCM register offsets * 53 #define OMAP4_REVISION_PRCM_OFFSET 54 #define OMAP4430_REVISION_PRCM 55 56 /* PRCM_MPU.DEVICE_PRM register offsets */ 57 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 58 #define OMAP4430_PRCM_MPU_PRM_RSTST 59 #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 60 #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT 61 62 /* PRCM_MPU.CPU0 register offsets */ 63 #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 64 #define OMAP4430_PM_CPU0_PWRSTCTRL 65 #define OMAP4_PM_CPU0_PWRSTST_OFFSET 66 #define OMAP4430_PM_CPU0_PWRSTST 67 #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 68 #define OMAP4430_RM_CPU0_CPU0_CONTEXT 69 #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 70 #define OMAP4430_RM_CPU0_CPU0_RSTCTRL 71 #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 72 #define OMAP4430_RM_CPU0_CPU0_RSTST 73 #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 74 #define OMAP4430_CM_CPU0_CPU0_CLKCTRL 75 #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 76 #define OMAP4430_CM_CPU0_CLKSTCTRL 77 78 /* PRCM_MPU.CPU1 register offsets */ 79 #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 80 #define OMAP4430_PM_CPU1_PWRSTCTRL 81 #define OMAP4_PM_CPU1_PWRSTST_OFFSET 82 #define OMAP4430_PM_CPU1_PWRSTST 83 #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 84 #define OMAP4430_RM_CPU1_CPU1_CONTEXT 85 #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 86 #define OMAP4430_RM_CPU1_CPU1_RSTCTRL 87 #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 88 #define OMAP4430_RM_CPU1_CPU1_RSTST 89 #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 90 #define OMAP4430_CM_CPU1_CPU1_CLKCTRL 91 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 92 #define OMAP4430_CM_CPU1_CLKSTCTRL 93 94 #endif 95
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