1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * OMAP3430 Power/Reset Management register bi 4 * 5 * Copyright (C) 2007-2008 Texas Instruments, 6 * Copyright (C) 2007-2008 Nokia Corporation 7 * 8 * Written by Paul Walmsley 9 */ 10 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX 11 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX 12 13 14 #include "prm3xxx.h" 15 16 #define OMAP3430_ERROROFFSET_MASK 17 #define OMAP3430_ERRORGAIN_MASK 18 #define OMAP3430_INITVOLTAGE_MASK 19 #define OMAP3430_TIMEOUTEN_MASK 20 #define OMAP3430_INITVDD_MASK 21 #define OMAP3430_FORCEUPDATE_MASK 22 #define OMAP3430_VPENABLE_MASK 23 #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 24 #define OMAP3430_VSTEPMIN_SHIFT 25 #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 26 #define OMAP3430_VSTEPMAX_SHIFT 27 #define OMAP3430_VDDMAX_SHIFT 28 #define OMAP3430_VDDMIN_SHIFT 29 #define OMAP3430_TIMEOUT_SHIFT 30 #define OMAP3430_VPVOLTAGE_MASK 31 #define OMAP3430_EN_PER_SHIFT 32 #define OMAP3430_LOGICSTATEST_MASK 33 #define OMAP3430_LASTLOGICSTATEENTERED_MASK 34 #define OMAP3430_LASTPOWERSTATEENTERED_MASK 35 #define OMAP3430_GRPSEL_MCBSP5_MASK 36 #define OMAP3430_GRPSEL_MCBSP1_MASK 37 #define OMAP3630_GRPSEL_UART4_MASK 38 #define OMAP3430_GRPSEL_GPIO6_MASK 39 #define OMAP3430_GRPSEL_GPIO5_MASK 40 #define OMAP3430_GRPSEL_GPIO4_MASK 41 #define OMAP3430_GRPSEL_GPIO3_MASK 42 #define OMAP3430_GRPSEL_GPIO2_MASK 43 #define OMAP3430_GRPSEL_UART3_MASK 44 #define OMAP3430_GRPSEL_GPT8_MASK 45 #define OMAP3430_GRPSEL_GPT7_MASK 46 #define OMAP3430_GRPSEL_GPT6_MASK 47 #define OMAP3430_GRPSEL_GPT5_MASK 48 #define OMAP3430_GRPSEL_MCBSP4_MASK 49 #define OMAP3430_GRPSEL_MCBSP3_MASK 50 #define OMAP3430_GRPSEL_MCBSP2_MASK 51 #define OMAP3430_GRPSEL_GPIO1_MASK 52 #define OMAP3430_GRPSEL_GPT12_MASK 53 #define OMAP3430_GRPSEL_GPT1_MASK 54 #define OMAP3430_RST3_IVA2_MASK 55 #define OMAP3430_RST2_IVA2_MASK 56 #define OMAP3430_RST1_IVA2_MASK 57 #define OMAP3430_L2FLATMEMONSTATE_MASK 58 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK 59 #define OMAP3430_L1FLATMEMONSTATE_MASK 60 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK 61 #define OMAP3430_L2FLATMEMRETSTATE_MASK 62 #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MAS 63 #define OMAP3430_L1FLATMEMRETSTATE_MASK 64 #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MAS 65 #define OMAP3430_L2FLATMEMSTATEST_MASK 66 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK 67 #define OMAP3430_L1FLATMEMSTATEST_MASK 68 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK 69 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MAS 70 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENT 71 #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 72 #define OMAP3430_VP2_TRANXDONE_ST_MASK 73 #define OMAP3430_VP1_TRANXDONE_ST_MASK 74 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_S 75 #define OMAP3430_MPU_DPLL_ST_SHIFT 76 #define OMAP3430_PERIPH_DPLL_ST_SHIFT 77 #define OMAP3430_CORE_DPLL_ST_SHIFT 78 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_S 79 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_R 80 #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 81 #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 82 #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 83 #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 84 #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 85 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTP 86 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_ 87 #define OMAP3430_LASTMEM2STATEENTERED_MASK 88 #define OMAP3430_LASTMEM1STATEENTERED_MASK 89 #define OMAP3430_EN_IO_CHAIN_MASK 90 #define OMAP3430_EN_IO_MASK 91 #define OMAP3430_EN_GPIO1_MASK 92 #define OMAP3430_ST_IO_CHAIN_MASK 93 #define OMAP3430_ST_IO_MASK 94 #define OMAP3430_SYS_CLKIN_SEL_SHIFT 95 #define OMAP3430_SYS_CLKIN_SEL_WIDTH 96 #define OMAP3430_CLKOUT_EN_SHIFT 97 #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK 98 #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 99 #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 100 #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK 101 #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 102 #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK 103 #define OMAP3430_VOLRA1_MASK 104 #define OMAP3430_VOLRA0_MASK 105 #define OMAP3430_CMDRA1_MASK 106 #define OMAP3430_CMDRA0_MASK 107 #define OMAP3430_VC_CMD_ON_SHIFT 108 #define OMAP3430_VC_CMD_ON_MASK 109 #define OMAP3430_VC_CMD_ONLP_SHIFT 110 #define OMAP3430_VC_CMD_RET_SHIFT 111 #define OMAP3430_VC_CMD_OFF_SHIFT 112 #define OMAP3430_SREN_MASK 113 #define OMAP3430_HSEN_MASK 114 #define OMAP3430_MCODE_MASK 115 #define OMAP3430_VALID_MASK 116 #define OMAP3430_DATA_SHIFT 117 #define OMAP3430_REGADDR_SHIFT 118 #define OMAP3430_SLAVEADDR_SHIFT 119 #define OMAP3430_ICECRUSHER_RST_SHIFT 120 #define OMAP3430_ICEPICK_RST_SHIFT 121 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIF 122 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIF 123 #define OMAP3430_EXTERNAL_WARM_RST_SHIFT 124 #define OMAP3430_SECURE_WD_RST_SHIFT 125 #define OMAP3430_MPU_WD_RST_SHIFT 126 #define OMAP3430_SECURITY_VIOL_RST_SHIFT 127 #define OMAP3430_GLOBAL_SW_RST_SHIFT 128 #define OMAP3430_GLOBAL_COLD_RST_SHIFT 129 #define OMAP3430_GLOBAL_COLD_RST_MASK 130 #define OMAP3430_PRM_VOLTCTRL_SEL_VMODE 131 #define OMAP3430_PRM_VOLTCTRL_SEL_OFF 132 #define OMAP3430_PRM_VOLTCTRL_AUTO_OFF 133 #define OMAP3430_PRM_VOLTCTRL_AUTO_RET 134 #define OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP 135 #define OMAP3430_SETUP_TIME2_MASK 136 #define OMAP3430_SETUP_TIME1_MASK 137 #define OMAP3430_PRM_POLCTRL_OFFMODE_POL 138 #define OMAP3430_PRM_POLCTRL_CLKOUT_POL 139 #define OMAP3430_PRM_POLCTRL_CLKREQ_POL 140 #define OMAP3430_PRM_POLCTRL_EXTVOL_POL 141 #endif 142
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