1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * OMAP44xx Power Management register bits 4 * 5 * Copyright (C) 2009-2010 Texas Instruments, 6 * Copyright (C) 2009-2010 Nokia Corporation 7 * 8 * Paul Walmsley (paul@pwsan.com) 9 * Rajendra Nayak (rnayak@ti.com) 10 * Benoit Cousson (b-cousson@ti.com) 11 * 12 * This file is automatically generated from t 13 * We respectfully ask that any modifications 14 * with the public linux-omap@vger.kernel.org 15 * authors above to ensure that the autogenera 16 * up-to-date with the file contents. 17 */ 18 19 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX 20 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX 21 22 #define OMAP4430_C2C_RST_SHIFT 23 #define OMAP4430_CMDRA_VDD_CORE_L_MASK 24 #define OMAP4430_CMDRA_VDD_IVA_L_MASK 25 #define OMAP4430_CMDRA_VDD_MPU_L_MASK 26 #define OMAP4430_DATA_SHIFT 27 #define OMAP4430_ERRORGAIN_MASK 28 #define OMAP4430_ERROROFFSET_MASK 29 #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 30 #define OMAP4430_FORCEUPDATE_MASK 31 #define OMAP4430_GLOBAL_COLD_RST_SHIFT 32 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 33 #define OMAP4430_GLOBAL_WUEN_MASK 34 #define OMAP4430_HSMCODE_MASK 35 #define OMAP4430_SRMODEEN_MASK 36 #define OMAP4430_HSMODEEN_MASK 37 #define OMAP4430_HSSCLL_SHIFT 38 #define OMAP4430_ICEPICK_RST_SHIFT 39 #define OMAP4430_INITVDD_MASK 40 #define OMAP4430_INITVOLTAGE_MASK 41 #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 42 #define OMAP4430_LASTPOWERSTATEENTERED_MASK 43 #define OMAP4430_LOGICRETSTATE_SHIFT 44 #define OMAP4430_LOGICRETSTATE_MASK 45 #define OMAP4430_LOGICSTATEST_SHIFT 46 #define OMAP4430_LOGICSTATEST_MASK 47 #define OMAP4430_LOSTCONTEXT_DFF_MASK 48 #define OMAP4430_LOSTMEM_AESSMEM_MASK 49 #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 50 #define OMAP4430_LOWPOWERSTATECHANGE_MASK 51 #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 52 #define OMAP4430_MPU_WDT_RST_SHIFT 53 #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK 54 #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK 55 #define OMAP4430_OCP_NRET_BANK_STATEST_MASK 56 #define OMAP4430_OFF_SHIFT 57 #define OMAP4430_ON_SHIFT 58 #define OMAP4430_ON_MASK 59 #define OMAP4430_ONLP_SHIFT 60 #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 61 #define OMAP4430_RAMP_UP_COUNT_SHIFT 62 #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 63 #define OMAP4430_REGADDR_SHIFT 64 #define OMAP4430_RET_SHIFT 65 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK 66 #define OMAP4430_SA_VDD_CORE_L_SHIFT 67 #define OMAP4430_SA_VDD_CORE_L_0_6_MASK 68 #define OMAP4430_SA_VDD_IVA_L_SHIFT 69 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_M 70 #define OMAP4430_SA_VDD_MPU_L_SHIFT 71 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_M 72 #define OMAP4430_SCLH_SHIFT 73 #define OMAP4430_SCLL_SHIFT 74 #define OMAP4430_SECURE_WDT_RST_SHIFT 75 #define OMAP4430_SLAVEADDR_SHIFT 76 #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 77 #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 78 #define OMAP4430_TIMEOUT_SHIFT 79 #define OMAP4430_TIMEOUTEN_MASK 80 #define OMAP4430_VALID_MASK 81 #define OMAP4430_VDDMAX_SHIFT 82 #define OMAP4430_VDDMIN_SHIFT 83 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 84 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 85 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 86 #define OMAP4430_VOLRA_VDD_CORE_L_MASK 87 #define OMAP4430_VOLRA_VDD_IVA_L_MASK 88 #define OMAP4430_VOLRA_VDD_MPU_L_MASK 89 #define OMAP4430_VPENABLE_MASK 90 #define OMAP4430_VPVOLTAGE_MASK 91 #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK 92 #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK 93 #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK 94 #define OMAP4430_VSTEPMAX_SHIFT 95 #define OMAP4430_VSTEPMIN_SHIFT 96 #define OMAP4430_WUCLK_CTRL_MASK 97 #define OMAP4430_WUCLK_STATUS_SHIFT 98 #define OMAP4430_WUCLK_STATUS_MASK 99 #endif 100
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