1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * OMAP2xxx Power/Reset Management (PRM) regis
4 *
5 * Copyright (C) 2007-2009, 2011-2012 Texas In
6 * Copyright (C) 2008-2010 Nokia Corporation
7 * Paul Walmsley
8 *
9 * The PRM hardware modules on the OMAP2/3 are
10 * other. The PRM on OMAP4 has a new register
11 * in a separate file.
12 */
13 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
14 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
15
16 #include "prcm-common.h"
17 #include "prm.h"
18 #include "prm2xxx_3xxx.h"
19
20 #define OMAP2420_PRM_REGADDR(module, reg)
21 OMAP2_L4_IO_ADDRESS(OMAP2420_P
22 #define OMAP2430_PRM_REGADDR(module, reg)
23 OMAP2_L4_IO_ADDRESS(OMAP2430_P
24
25 /*
26 * OMAP2-specific global PRM registers
27 * Use {read,write}l_relaxed() with these regi
28 *
29 * With a few exceptions, these are the regist
30 * PRCM_* on 24xx. (The exceptions are the IR
31 * bits.)
32 *
33 */
34
35 #define OMAP2_PRCM_REVISION_OFFSET 0x0000
36 #define OMAP2420_PRCM_REVISION OMAP24
37 #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
38 #define OMAP2420_PRCM_SYSCONFIG OMAP24
39
40 #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
41 #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP24
42 #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
43 #define OMAP2420_PRCM_IRQENABLE_MPU OMAP24
44
45 #define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
46 #define OMAP2420_PRCM_VOLTCTRL OMAP24
47 #define OMAP2_PRCM_VOLTST_OFFSET 0x0054
48 #define OMAP2420_PRCM_VOLTST OMAP24
49 #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
50 #define OMAP2420_PRCM_CLKSRC_CTRL OMAP24
51 #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
52 #define OMAP2420_PRCM_CLKOUT_CTRL OMAP24
53 #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
54 #define OMAP2420_PRCM_CLKEMUL_CTRL OMAP24
55 #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
56 #define OMAP2420_PRCM_CLKCFG_CTRL OMAP24
57 #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
58 #define OMAP2420_PRCM_CLKCFG_STATUS OMAP24
59 #define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
60 #define OMAP2420_PRCM_VOLTSETUP OMAP24
61 #define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
62 #define OMAP2420_PRCM_CLKSSETUP OMAP24
63 #define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
64 #define OMAP2420_PRCM_POLCTRL OMAP24
65
66 #define OMAP2430_PRCM_REVISION OMAP24
67 #define OMAP2430_PRCM_SYSCONFIG OMAP24
68
69 #define OMAP2430_PRCM_IRQSTATUS_MPU OMAP24
70 #define OMAP2430_PRCM_IRQENABLE_MPU OMAP24
71
72 #define OMAP2430_PRCM_VOLTCTRL OMAP24
73 #define OMAP2430_PRCM_VOLTST OMAP24
74 #define OMAP2430_PRCM_CLKSRC_CTRL OMAP24
75 #define OMAP2430_PRCM_CLKOUT_CTRL OMAP24
76 #define OMAP2430_PRCM_CLKEMUL_CTRL OMAP24
77 #define OMAP2430_PRCM_CLKCFG_CTRL OMAP24
78 #define OMAP2430_PRCM_CLKCFG_STATUS OMAP24
79 #define OMAP2430_PRCM_VOLTSETUP OMAP24
80 #define OMAP2430_PRCM_CLKSSETUP OMAP24
81 #define OMAP2430_PRCM_POLCTRL OMAP24
82
83 /*
84 * Module specific PRM register offsets from P
85 *
86 * Use prm_{read,write}_mod_reg() with these r
87 *
88 * With a few exceptions, these are the regist
89 * {PM,RM}_* on both OMAP2/3 SoC families.. (
90 * IRQSTATUS and IRQENABLE bits.)
91 */
92
93 /* Register offsets appearing on both OMAP2 an
94
95 #define OMAP2_RM_RSTCTRL
96 #define OMAP2_RM_RSTTIME
97 #define OMAP2_RM_RSTST
98 #define OMAP2_PM_PWSTCTRL
99 #define OMAP2_PM_PWSTST
100
101 #define PM_WKEN
102 #define PM_WKEN1
103 #define PM_WKST
104 #define PM_WKST1
105 #define PM_WKDEP
106 #define PM_EVGENCTRL
107 #define PM_EVGENONTIM
108 #define PM_EVGENOFFTIM
109
110 /* OMAP2xxx specific register offsets */
111 #define OMAP24XX_PM_WKEN2
112 #define OMAP24XX_PM_WKST2
113
114 #define OMAP24XX_PRCM_IRQSTATUS_DSP
115 #define OMAP24XX_PRCM_IRQENABLE_DSP
116 #define OMAP24XX_PRCM_IRQSTATUS_IVA
117 #define OMAP24XX_PRCM_IRQENABLE_IVA
118
119 #ifndef __ASSEMBLER__
120 /* Function prototypes */
121 extern int omap2xxx_clkdm_sleep(struct clockdo
122 extern int omap2xxx_clkdm_wakeup(struct clockd
123
124 int __init omap2xxx_prm_init(const struct omap
125
126 #endif
127
128 #endif
129
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