1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * OMAP3xxx PRM module functions
4 *
5 * Copyright (C) 2010-2012 Texas Instruments,
6 * Copyright (C) 2010 Nokia Corporation
7 * Benoît Cousson
8 * Paul Walmsley
9 * Rajendra Nayak <rnayak@ti.com>
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/of_irq.h>
18
19 #include "soc.h"
20 #include "common.h"
21 #include "vp.h"
22 #include "powerdomain.h"
23 #include "prm3xxx.h"
24 #include "prm2xxx_3xxx.h"
25 #include "cm2xxx_3xxx.h"
26 #include "prm-regbits-34xx.h"
27 #include "cm3xxx.h"
28 #include "cm-regbits-34xx.h"
29 #include "clock.h"
30
31 static void omap3xxx_prm_read_pending_irqs(uns
32 static void omap3xxx_prm_ocp_barrier(void);
33 static void omap3xxx_prm_save_and_clear_irqen(
34 static void omap3xxx_prm_restore_irqen(u32 *sa
35 static void omap3xxx_prm_iva_idle(void);
36
37 static const struct omap_prcm_irq omap3_prcm_i
38 OMAP_PRCM_IRQ("wkup", 0, 0),
39 OMAP_PRCM_IRQ("io", 9, 1),
40 };
41
42 static struct omap_prcm_irq_setup omap3_prcm_i
43 .ack = OMAP3_PRM_IR
44 .mask = OMAP3_PRM_IR
45 .nr_regs = 1,
46 .irqs = omap3_prcm_i
47 .nr_irqs = ARRAY_SIZE(o
48 .irq = 11 + OMAP_IN
49 .read_pending_irqs = &omap3xxx_pr
50 .ocp_barrier = &omap3xxx_pr
51 .save_and_clear_irqen = &omap3xxx_pr
52 .restore_irqen = &omap3xxx_pr
53 .reconfigure_io_chain = NULL,
54 };
55
56 /*
57 * omap3_prm_reset_src_map - map from bits in
58 * register (which are specific to OMAP3xxx
59 * bit shifts (which is an OMAP SoC-independ
60 */
61 static struct prm_reset_src_map omap3xxx_prm_r
62 { OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP
63 { OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_G
64 { OMAP3430_SECURITY_VIOL_RST_SHIFT, OM
65 { OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_
66 { OMAP3430_SECURE_WD_RST_SHIFT, OMAP_M
67 { OMAP3430_EXTERNAL_WARM_RST_SHIFT, OM
68 { OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SH
69 OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
70 { OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SH
71 OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
72 { OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICE
73 { OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_
74 { -1, -1 },
75 };
76
77 /* PRM VP */
78
79 /*
80 * struct omap3_vp - OMAP3 VP register access
81 * @tranxdone_status: VP_TRANXDONE_ST bitmask
82 */
83 struct omap3_vp {
84 u32 tranxdone_status;
85 };
86
87 static struct omap3_vp omap3_vp[] = {
88 [OMAP3_VP_VDD_MPU_ID] = {
89 .tranxdone_status = OMAP3430_V
90 },
91 [OMAP3_VP_VDD_CORE_ID] = {
92 .tranxdone_status = OMAP3430_V
93 },
94 };
95
96 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
97
98 static u32 omap3_prm_vp_check_txdone(u8 vp_id)
99 {
100 struct omap3_vp *vp = &omap3_vp[vp_id]
101 u32 irqstatus;
102
103 irqstatus = omap2_prm_read_mod_reg(OCP
104 OMA
105 return irqstatus & vp->tranxdone_statu
106 }
107
108 static void omap3_prm_vp_clear_txdone(u8 vp_id
109 {
110 struct omap3_vp *vp = &omap3_vp[vp_id]
111
112 omap2_prm_write_mod_reg(vp->tranxdone_
113 OCP_MOD, OMAP3
114 }
115
116 u32 omap3_prm_vcvp_read(u8 offset)
117 {
118 return omap2_prm_read_mod_reg(OMAP3430
119 }
120
121 void omap3_prm_vcvp_write(u32 val, u8 offset)
122 {
123 omap2_prm_write_mod_reg(val, OMAP3430_
124 }
125
126 u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8
127 {
128 return omap2_prm_rmw_mod_reg_bits(mask
129 }
130
131 /**
132 * omap3xxx_prm_dpll3_reset - use DPLL3 reset
133 *
134 * Set the DPLL3 reset bit, which should reboo
135 * recommended way to restart the SoC, conside
136 * return value.
137 */
138 static void omap3xxx_prm_dpll3_reset(void)
139 {
140 omap2_prm_set_mod_reg_bits(OMAP_RST_DP
141 OMAP2_RM_RS
142 /* OCP barrier */
143 omap2_prm_read_mod_reg(OMAP3430_GR_MOD
144 }
145
146 /**
147 * omap3xxx_prm_read_pending_irqs - read pendi
148 * @events: ptr to a u32, preallocated by call
149 *
150 * Read PRM_IRQSTATUS_MPU bits, AND'ed with th
151 * MPU IRQs, and store the result into the u32
152 * No return value.
153 */
154 static void omap3xxx_prm_read_pending_irqs(uns
155 {
156 u32 mask, st;
157
158 /* XXX Can the mask read be avoided (e
159 mask = omap2_prm_read_mod_reg(OCP_MOD,
160 st = omap2_prm_read_mod_reg(OCP_MOD, O
161
162 events[0] = mask & st;
163 }
164
165 /**
166 * omap3xxx_prm_ocp_barrier - force buffered M
167 *
168 * Force any buffered writes to the PRM IP blo
169 * by the PRM IRQ handler, which reads and wri
170 * block, to avoid race conditions after ackno
171 * bits. No return value.
172 */
173 static void omap3xxx_prm_ocp_barrier(void)
174 {
175 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_
176 }
177
178 /**
179 * omap3xxx_prm_save_and_clear_irqen - save/cl
180 * @saved_mask: ptr to a u32 array to save IRQ
181 *
182 * Save the PRM_IRQENABLE_MPU register to @sav
183 * must be allocated by the caller. Intended
184 * interrupt handler suspend callback. The OC
185 * ensure the write to disable PRM interrupts
186 * returning; otherwise, spurious interrupts m
187 * value.
188 */
189 static void omap3xxx_prm_save_and_clear_irqen(
190 {
191 saved_mask[0] = omap2_prm_read_mod_reg
192
193 omap2_prm_write_mod_reg(0, OCP_MOD, OM
194
195 /* OCP barrier */
196 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_
197 }
198
199 /**
200 * omap3xxx_prm_restore_irqen - set PRM_IRQENA
201 * @saved_mask: ptr to a u32 array of IRQENABL
202 *
203 * Restore the PRM_IRQENABLE_MPU register from
204 * to be used in the PRM interrupt handler res
205 * values saved by omap3xxx_prm_save_and_clear
206 * barrier should be needed here; any pending
207 * once the writes reach the PRM. No return v
208 */
209 static void omap3xxx_prm_restore_irqen(u32 *sa
210 {
211 omap2_prm_write_mod_reg(saved_mask[0],
212 OMAP3_PRM_IRQE
213 }
214
215 /**
216 * omap3xxx_prm_clear_mod_irqs - clear wake-up
217 * @module: PRM module to clear wakeups from
218 * @regs: register set to clear, 1 or 3
219 * @wkst_mask: wkst bits to clear
220 *
221 * The purpose of this function is to clear an
222 * in the PRCM PM_WKST_x registers. It is poss
223 * may occur whilst attempting to clear a PM_W
224 * set another bit in this register. A while l
225 * that any peripheral wake-up events occurrin
226 * clear the PM_WKST_x are detected and cleare
227 */
228 static int omap3xxx_prm_clear_mod_irqs(s16 mod
229 {
230 u32 wkst, fclk, iclk, clken;
231 u16 wkst_off = (regs == 3) ? OMAP3430E
232 u16 fclk_off = (regs == 3) ? OMAP3430E
233 u16 iclk_off = (regs == 3) ? CM_ICLKEN
234 u16 grpsel_off = (regs == 3) ?
235 OMAP3430ES2_PM_MPUGRPSEL3 : OM
236 int c = 0;
237
238 wkst = omap2_prm_read_mod_reg(module,
239 wkst &= omap2_prm_read_mod_reg(module,
240 wkst &= wkst_mask;
241 if (wkst) {
242 iclk = omap2_cm_read_mod_reg(m
243 fclk = omap2_cm_read_mod_reg(m
244 while (wkst) {
245 clken = wkst;
246 omap2_cm_set_mod_reg_b
247 /*
248 * For USBHOST, we don
249 * HOST2 woke us up, s
250 */
251 if (module == OMAP3430
252 clken |= 1 <<
253 omap2_cm_set_mod_reg_b
254 omap2_prm_write_mod_re
255 wkst = omap2_prm_read_
256 wkst &= wkst_mask;
257 c++;
258 }
259 omap2_cm_write_mod_reg(iclk, m
260 omap2_cm_write_mod_reg(fclk, m
261 }
262
263 return c;
264 }
265
266 /**
267 * omap3_prm_reset_modem - toggle reset signal
268 *
269 * Toggles the reset signal to modem IP block.
270 * OMAP3430 without stacked modem to idle prop
271 */
272 static void __init omap3_prm_reset_modem(void)
273 {
274 omap2_prm_write_mod_reg(
275 OMAP3430_RM_RSTCTRL_CORE_MODEM
276 OMAP3430_RM_RSTCTRL_CORE_MODEM
277 CORE_MOD, OMAP
278 omap2_prm_write_mod_reg(0, CORE_MOD, O
279 }
280
281 /**
282 * omap3_prm_init_pm - initialize PM related r
283 * @has_uart4: SoC has UART4
284 * @has_iva: SoC has IVA
285 *
286 * Initializes PRM registers for PM use. Calle
287 */
288 void __init omap3_prm_init_pm(bool has_uart4,
289 {
290 u32 en_uart4_mask;
291 u32 grpsel_uart4_mask;
292
293 /*
294 * Enable control of expternal oscilla
295 * sys_clkreq. In the long run clock f
296 * take care of this.
297 */
298 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEX
299 1 << OMAP_A
300 OMAP3430_GR
301 OMAP3_PRM_C
302
303 /* setup wakup source */
304 omap2_prm_write_mod_reg(OMAP3430_EN_IO
305 OMAP3430_EN_GP
306 WKUP_MOD, PM_W
307 /* No need to write EN_IO, that is alw
308 omap2_prm_write_mod_reg(OMAP3430_GRPSE
309 OMAP3430_GRPSE
310 OMAP3430_GRPSE
311 WKUP_MOD, OMAP
312
313 /* Enable PM_WKEN to support DSS LPR *
314 omap2_prm_write_mod_reg(OMAP3430_PM_WK
315 OMAP3430_DSS_M
316
317 if (has_uart4) {
318 en_uart4_mask = OMAP3630_EN_UA
319 grpsel_uart4_mask = OMAP3630_G
320 } else {
321 en_uart4_mask = 0;
322 grpsel_uart4_mask = 0;
323 }
324
325 /* Enable wakeups in PER */
326 omap2_prm_write_mod_reg(en_uart4_mask
327 OMAP3430_EN_GP
328 OMAP3430_EN_GP
329 OMAP3430_EN_GP
330 OMAP3430_EN_GP
331 OMAP3430_EN_GP
332 OMAP3430_EN_UA
333 OMAP3430_EN_MC
334 OMAP3430_EN_MC
335 OMAP3430_EN_MC
336 OMAP3430_PER_M
337
338 /* and allow them to wake up MPU */
339 omap2_prm_write_mod_reg(grpsel_uart4_m
340 OMAP3430_GRPSE
341 OMAP3430_GRPSE
342 OMAP3430_GRPSE
343 OMAP3430_GRPSE
344 OMAP3430_GRPSE
345 OMAP3430_GRPSE
346 OMAP3430_GRPSE
347 OMAP3430_GRPSE
348 OMAP3430_GRPSE
349 OMAP3430_PER_M
350
351 /* Don't attach IVA interrupts */
352 if (has_iva) {
353 omap2_prm_write_mod_reg(0, WKU
354 omap2_prm_write_mod_reg(0, COR
355 omap2_prm_write_mod_reg(0, COR
356 omap2_prm_write_mod_reg(0, OMA
357 OMAP34
358 }
359
360 /* Clear any pending 'reset' flags */
361 omap2_prm_write_mod_reg(0xffffffff, MP
362 omap2_prm_write_mod_reg(0xffffffff, CO
363 omap2_prm_write_mod_reg(0xffffffff, OM
364 omap2_prm_write_mod_reg(0xffffffff, OM
365 omap2_prm_write_mod_reg(0xffffffff, OM
366 omap2_prm_write_mod_reg(0xffffffff, OM
367 omap2_prm_write_mod_reg(0xffffffff, OM
368 OMAP2_RM_RSTST
369
370 /* Clear any pending PRCM interrupts *
371 omap2_prm_write_mod_reg(0, OCP_MOD, OM
372
373 /* We need to idle iva2_pwrdm even on
374 omap3xxx_prm_iva_idle();
375
376 omap3_prm_reset_modem();
377 }
378
379 /**
380 * omap3430_pre_es3_1_reconfigure_io_chain - r
381 *
382 * The ST_IO_CHAIN bit does not exist in 3430
383 * thing we can do is toggle EN_IO bit for ear
384 */
385 static void omap3430_pre_es3_1_reconfigure_io_
386 {
387 omap2_prm_clear_mod_reg_bits(OMAP3430_
388 PM_WKEN);
389 omap2_prm_set_mod_reg_bits(OMAP3430_EN
390 PM_WKEN);
391 omap2_prm_read_mod_reg(WKUP_MOD, PM_WK
392 }
393
394 /**
395 * omap3_prm_reconfigure_io_chain - clear latc
396 *
397 * Clear any previously-latched I/O wakeup eve
398 * I/O wakeup gates are aligned with the curre
399 * by asserting WUCLKIN, waiting for WUCLKOUT
400 * deasserting WUCLKIN and clearing the ST_IO_
401 * return value. These registers are only avai
402 */
403 static void omap3_prm_reconfigure_io_chain(voi
404 {
405 int i = 0;
406
407 omap2_prm_set_mod_reg_bits(OMAP3430_EN
408 PM_WKEN);
409
410 omap_test_timeout(omap2_prm_read_mod_r
411 OMAP3430_ST_IO_CHAIN
412 MAX_IOPAD_LATCH_TIME
413 if (i == MAX_IOPAD_LATCH_TIME)
414 pr_warn("PRM: I/O chain clock
415
416 omap2_prm_clear_mod_reg_bits(OMAP3430_
417 PM_WKEN);
418
419 omap2_prm_set_mod_reg_bits(OMAP3430_ST
420 PM_WKST);
421
422 omap2_prm_read_mod_reg(WKUP_MOD, PM_WK
423 }
424
425 /**
426 * omap3xxx_prm_enable_io_wakeup - enable wake
427 *
428 * Activates the I/O wakeup event latches and
429 * those latches to signal a wakeup event to t
430 * wakeups to occur, WAKEUPENABLE bits must be
431 * registers, and omap3xxx_prm_reconfigure_io_
432 * No return value.
433 */
434 static void omap3xxx_prm_enable_io_wakeup(void
435 {
436 if (prm_features & PRM_HAS_IO_WAKEUP)
437 omap2_prm_set_mod_reg_bits(OMA
438 PM_
439 }
440
441 /**
442 * omap3xxx_prm_read_reset_sources - return th
443 *
444 * Return a u32 representing the last reset so
445 * returned reset source bits are standardized
446 */
447 static u32 omap3xxx_prm_read_reset_sources(voi
448 {
449 struct prm_reset_src_map *p;
450 u32 r = 0;
451 u32 v;
452
453 v = omap2_prm_read_mod_reg(WKUP_MOD, O
454
455 p = omap3xxx_prm_reset_src_map;
456 while (p->reg_shift >= 0 && p->std_shi
457 if (v & (1 << p->reg_shift))
458 r |= 1 << p->std_shift
459 p++;
460 }
461
462 return r;
463 }
464
465 /**
466 * omap3xxx_prm_iva_idle - ensure IVA is in id
467 *
468 * In cases where IVA2 is activated by bootcod
469 * full-chip retention or off-mode because it
470 * function forces the IVA2 into idle state so
471 * into retention/off and thus allow full-chip
472 */
473 static void omap3xxx_prm_iva_idle(void)
474 {
475 /* ensure IVA2 clock is disabled */
476 omap2_cm_write_mod_reg(0, OMAP3430_IVA
477
478 /* if no clock activity, nothing else
479 if (!(omap2_cm_read_mod_reg(OMAP3430_I
480 OMAP3430_CLKACTIVITY_IVA2_MASK))
481 return;
482
483 /* Reset IVA2 */
484 omap2_prm_write_mod_reg(OMAP3430_RST1_
485 OMAP3430_RST2_
486 OMAP3430_RST3_
487 OMAP3430_IVA2_
488
489 /* Enable IVA2 clock */
490 omap2_cm_write_mod_reg(OMAP3430_CM_FCL
491 OMAP3430_IVA2_M
492
493 /* Un-reset IVA2 */
494 omap2_prm_write_mod_reg(0, OMAP3430_IV
495
496 /* Disable IVA2 clock */
497 omap2_cm_write_mod_reg(0, OMAP3430_IVA
498
499 /* Reset IVA2 */
500 omap2_prm_write_mod_reg(OMAP3430_RST1_
501 OMAP3430_RST2_
502 OMAP3430_RST3_
503 OMAP3430_IVA2_
504 }
505
506 /**
507 * omap3xxx_prm_clear_global_cold_reset - chec
508 * and
509 *
510 * Checks if cold-reset has occurred and clear
511 * 1 if cold-reset has occurred, 0 otherwise.
512 */
513 int omap3xxx_prm_clear_global_cold_reset(void)
514 {
515 if (omap2_prm_read_mod_reg(OMAP3430_GR
516 OMAP3430_GLOBAL_COLD_RST_MASK) {
517 omap2_prm_set_mod_reg_bits(OMA
518 OMA
519 OMA
520 return 1;
521 }
522
523 return 0;
524 }
525
526 void omap3_prm_save_scratchpad_contents(u32 *p
527 {
528 *ptr++ = omap2_prm_read_mod_reg(OMAP34
529 OMAP3_
530
531 *ptr++ = omap2_prm_read_mod_reg(OMAP34
532 OMAP3_
533 }
534
535 /* Powerdomain low-level functions */
536
537 static int omap3_pwrdm_set_next_pwrst(struct p
538 {
539 omap2_prm_rmw_mod_reg_bits(OMAP_POWERS
540 (pwrst << O
541 pwrdm->prcm
542 return 0;
543 }
544
545 static int omap3_pwrdm_read_next_pwrst(struct
546 {
547 return omap2_prm_read_mod_bits_shift(p
548 O
549 O
550 }
551
552 static int omap3_pwrdm_read_pwrst(struct power
553 {
554 return omap2_prm_read_mod_bits_shift(p
555 O
556 O
557 }
558
559 /* Applicable only for OMAP3. Not supported on
560 static int omap3_pwrdm_read_prev_pwrst(struct
561 {
562 return omap2_prm_read_mod_bits_shift(p
563 O
564 O
565 }
566
567 static int omap3_pwrdm_read_logic_pwrst(struct
568 {
569 return omap2_prm_read_mod_bits_shift(p
570 O
571 O
572 }
573
574 static int omap3_pwrdm_read_logic_retst(struct
575 {
576 return omap2_prm_read_mod_bits_shift(p
577 O
578 O
579 }
580
581 static int omap3_pwrdm_read_prev_logic_pwrst(s
582 {
583 return omap2_prm_read_mod_bits_shift(p
584 O
585 O
586 }
587
588 static int omap3_get_mem_bank_lastmemst_mask(u
589 {
590 switch (bank) {
591 case 0:
592 return OMAP3430_LASTMEM1STATEE
593 case 1:
594 return OMAP3430_LASTMEM2STATEE
595 case 2:
596 return OMAP3430_LASTSHAREDL2CA
597 case 3:
598 return OMAP3430_LASTL2FLATMEMS
599 default:
600 WARN_ON(1); /* should never ha
601 return -EEXIST;
602 }
603 return 0;
604 }
605
606 static int omap3_pwrdm_read_prev_mem_pwrst(str
607 {
608 u32 m;
609
610 m = omap3_get_mem_bank_lastmemst_mask(
611
612 return omap2_prm_read_mod_bits_shift(p
613 OMAP3430_PM_PR
614 }
615
616 static int omap3_pwrdm_clear_all_prev_pwrst(st
617 {
618 omap2_prm_write_mod_reg(0, pwrdm->prcm
619 return 0;
620 }
621
622 static int omap3_pwrdm_enable_hdwr_sar(struct
623 {
624 return omap2_prm_rmw_mod_reg_bits(0,
625 1 <<
626 pwrd
627 }
628
629 static int omap3_pwrdm_disable_hdwr_sar(struct
630 {
631 return omap2_prm_rmw_mod_reg_bits(1 <<
632 0, p
633 OMAP
634 }
635
636 struct pwrdm_ops omap3_pwrdm_operations = {
637 .pwrdm_set_next_pwrst = omap3_pwrdm_
638 .pwrdm_read_next_pwrst = omap3_pwrdm_
639 .pwrdm_read_pwrst = omap3_pwrdm_
640 .pwrdm_read_prev_pwrst = omap3_pwrdm_
641 .pwrdm_set_logic_retst = omap2_pwrdm_
642 .pwrdm_read_logic_pwrst = omap3_pwrdm_
643 .pwrdm_read_logic_retst = omap3_pwrdm_
644 .pwrdm_read_prev_logic_pwrst = omap
645 .pwrdm_set_mem_onst = omap2_pwrdm_
646 .pwrdm_set_mem_retst = omap2_pwrdm_
647 .pwrdm_read_mem_pwrst = omap2_pwrdm_
648 .pwrdm_read_mem_retst = omap2_pwrdm_
649 .pwrdm_read_prev_mem_pwrst = omap
650 .pwrdm_clear_all_prev_pwrst = omap
651 .pwrdm_enable_hdwr_sar = omap3_pwrdm_
652 .pwrdm_disable_hdwr_sar = omap3_pwrdm_
653 .pwrdm_wait_transition = omap2_pwrdm_
654 };
655
656 /*
657 *
658 */
659
660 static int omap3xxx_prm_late_init(void);
661
662 static struct prm_ll_data omap3xxx_prm_ll_data
663 .read_reset_sources = &omap3xxx_prm_re
664 .late_init = &omap3xxx_prm_late_init,
665 .assert_hardreset = &omap2_prm_assert_
666 .deassert_hardreset = &omap2_prm_deass
667 .is_hardreset_asserted = &omap2_prm_is
668 .reset_system = &omap3xxx_prm_dpll3_re
669 .clear_mod_irqs = &omap3xxx_prm_clear_
670 .vp_check_txdone = &omap3_prm_vp_check
671 .vp_clear_txdone = &omap3_prm_vp_clear
672 };
673
674 int __init omap3xxx_prm_init(const struct omap
675 {
676 omap2_clk_legacy_provider_init(TI_CLKM
677 prm_bas
678 if (omap3_has_io_wakeup())
679 prm_features |= PRM_HAS_IO_WAK
680
681 return prm_register(&omap3xxx_prm_ll_d
682 }
683
684 static const struct of_device_id omap3_prm_dt_
685 { .compatible = "ti,omap3-prm" },
686 { }
687 };
688
689 static int omap3xxx_prm_late_init(void)
690 {
691 struct device_node *np;
692 int irq_num;
693
694 if (!(prm_features & PRM_HAS_IO_WAKEUP
695 return 0;
696
697 if (omap3_has_io_chain_ctrl())
698 omap3_prcm_irq_setup.reconfigu
699 omap3_prm_reconfigure_
700 else
701 omap3_prcm_irq_setup.reconfigu
702 omap3430_pre_es3_1_rec
703
704 np = of_find_matching_node(NULL, omap3
705 if (!np) {
706 pr_err("PRM: no device tree no
707
708 return -ENODEV;
709 }
710
711 irq_num = of_irq_get(np, 0);
712 of_node_put(np);
713 if (irq_num == -EPROBE_DEFER)
714 return irq_num;
715
716 omap3_prcm_irq_setup.irq = irq_num;
717
718 omap3xxx_prm_enable_io_wakeup();
719
720 return omap_prcm_register_chain_handle
721 }
722
723 static void __exit omap3xxx_prm_exit(void)
724 {
725 prm_unregister(&omap3xxx_prm_ll_data);
726 }
727 __exitcall(omap3xxx_prm_exit);
728
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