1 /* SPDX-License-Identifier: GPL-2.0-or-later *
2 /*
3 * linux/arch/arm/mach-omap2/sram243x.S
4 *
5 * Omap2 specific functions that need to be ru
6 *
7 * (C) Copyright 2004
8 * Texas Instruments, <www.ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 *
11 * Richard Woodruff notes that any changes to
12 * audited and tested to ensure that they don'
13 * the SDRAM is inaccessible. Such a situatio
14 * since it will cause the ARM MMU to attempt
15 * These crashes may be intermittent.
16 */
17 #include <linux/linkage.h>
18
19 #include <asm/assembler.h>
20
21 #include "soc.h"
22 #include "iomap.h"
23 #include "prm2xxx.h"
24 #include "cm2xxx.h"
25 #include "sdrc.h"
26
27 .text
28
29 .align 3
30 ENTRY(omap243x_sram_ddr_init)
31 stmfd sp!, {r0 - r12, lr} @ save
32
33 mov r12, r2 @ capt
34 mov r8, r3 @ capt
35
36 /* frequency shift down */
37 ldr r2, omap243x_sdi_cm_clksel2_pl
38 mov r3, #0x1 @ valu
39 str r3, [r2] @ go t
40
41 /* voltage shift down */
42 mov r9, #0x1 @ set
43 bl voltage_shift @ go d
44
45 /* dll lock mode */
46 ldr r11, omap243x_sdi_sdrc_dlla_ct
47 ldr r10, [r11] @ get
48 cmp r12, #0x1 @ cs1
49 addeq r11, r11, #0x8 @ if c
50 mvn r9, #0x4 @ mask
51 and r10, r10, r9 @ clea
52 orr r10, r10, #0x8 @ make
53 orr r10, r10, #0x2 @ 90 d
54 str r10, [r11] @ comm
55 bl i_dll_wait @ wait
56
57 /* get dll value */
58 add r11, r11, #0x4 @ get
59 ldr r10, [r11] @ get
60
61 /* voltage shift up */
62 mov r9, #0x0 @ shif
63 bl voltage_shift @ go r
64
65 /* frequency shift up */
66 mov r3, #0x2 @ valu
67 str r3, [r2] @ go t
68
69 /* reset entry mode for dllctrl */
70 sub r11, r11, #0x4 @ move
71 cmp r12, #0x1 @ norm
72 subeq r11, r11, #0x8 @ poss
73 cmp r8, #0x1 @ if f
74 orreq r1, r1, #0x4 @ make
75 str r1, [r11] @ rest
76 add r11, r11, #0x8 @ move
77 str r1, [r11] @ set
78 bl i_dll_wait @ wait
79
80 /* set up for return, DDR should be go
81 str r10, [r0] @ writ
82 ldmfd sp!, {r0 - r12, pc} @ rest
83
84 /* ensure the DLL has relocked */
85 i_dll_wait:
86 mov r4, #0x800 @ dela
87 i_dll_delay:
88 subs r4, r4, #0x1
89 bne i_dll_delay
90 ret lr
91
92 /*
93 * shift up or down voltage, use R9 as
94 * wait for it to finish, use 32k sync
95 */
96 voltage_shift:
97 ldr r4, omap243x_sdi_prcm_voltctrl
98 ldr r5, [r4] @ get
99 ldr r6, prcm_mask_val @ get
100 and r5, r5, r6 @ appl
101 orr r5, r5, r9 @ bull
102 str r5, [r4] @ set
103 mov r3, #0x4000 @ get
104 orr r5, r5, r3 @ buil
105 str r5, [r4] @ Forc
106
107 ldr r3, omap243x_sdi_timer_32ksync
108 ldr r5, [r3] @ get
109 add r5, r5, #0x3 @ give
110 volt_delay:
111 ldr r7, [r3] @ get
112 cmp r5, r7 @ time
113 bhi volt_delay @ not
114 ret lr @ back
115
116 omap243x_sdi_cm_clksel2_pll:
117 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_
118 omap243x_sdi_sdrc_dlla_ctrl:
119 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_
120 omap243x_sdi_prcm_voltctrl:
121 .word OMAP2430_PRCM_VOLTCTRL
122 prcm_mask_val:
123 .word 0xFFFF3FFC
124 omap243x_sdi_timer_32ksynct_cr:
125 .word OMAP2_L4_IO_ADDRESS(OMAP2430_32K
126 ENTRY(omap243x_sram_ddr_init_sz)
127 .word . - omap243x_sram_ddr_init
128
129 /*
130 * Reprograms memory timings.
131 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR
133 */
134 .align 3
135 ENTRY(omap243x_sram_reprogram_sdrc)
136 stmfd sp!, {r0 - r10, lr} @ save
137 mov r3, #0x0 @ clea
138 mcr p15, 0, r3, c7, c10, 4 @ memo
139 nop
140 nop
141 ldr r6, omap243x_srs_sdrc_rfr_ctrl
142 ldr r5, [r6] @ get
143 mov r5, r5, lsr #8 @ isol
144
145 cmp r0, #0x1 @ goin
146 movne r9, #0x0 @ if u
147
148 blne voltage_shift_c @ adju
149
150 cmp r0, #0x1 @ goin
151 moveq r5, r5, lsr #1 @ divi
152 movne r5, r5, lsl #1 @ mult
153 mov r5, r5, lsl #8 @ put
154 add r5, r5, #0x1 @ turn
155 ldr r4, omap243x_srs_cm_clksel2_pl
156 ldr r3, [r4] @ get
157 orr r3, r3, #0x3
158 bic r3, r3, #0x3 @ clea
159 orr r3, r3, r0 @ new
160 str r3, [r4] @ set
161 nop
162 nop
163
164 moveq r9, #0x1 @ if s
165 bleq voltage_shift_c
166
167 mcr p15, 0, r3, c7, c10, 4 @ memo
168 str r5, [r6] @ set
169 add r6, r6, #0x30 @ get
170 str r5, [r6] @ set
171 nop
172 cmp r2, #0x1 @ (SDR
173 bne freq_out @ leav
174
175 /* With DDR, we need to take care of t
176 ldr r2, omap243x_srs_sdrc_dlla_ctr
177 str r1, [r2] @ writ
178 add r2, r2, #0x8 @ addr
179 str r1, [r2] @ comm
180 mov r1, #0x2000 @ wait
181 dll_wait:
182 subs r1, r1, #0x1
183 bne dll_wait
184 freq_out:
185 ldmfd sp!, {r0 - r10, pc} @ rest
186
187 /*
188 * shift up or down voltage, use R9 as inp
189 * wait for it to finish, use 32k sync co
190 */
191 voltage_shift_c:
192 ldr r10, omap243x_srs_prcm_voltctr
193 ldr r8, [r10] @ get
194 ldr r7, ddr_prcm_mask_val @ get
195 and r8, r8, r7 @ appl
196 orr r8, r8, r9 @ bull
197 str r8, [r10] @ set
198 mov r7, #0x4000 @ get
199 orr r8, r8, r7 @ buil
200 str r8, [r10] @ Forc
201
202 ldr r10, omap243x_srs_timer_32ksyn
203 ldr r8, [r10] @ get
204 add r8, r8, #0x2 @ give
205 volt_delay_c:
206 ldr r7, [r10] @ get
207 cmp r8, r7 @ time
208 bhi volt_delay_c @ not
209 ret lr @ back
210
211 omap243x_srs_cm_clksel2_pll:
212 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_
213 omap243x_srs_sdrc_dlla_ctrl:
214 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_
215 omap243x_srs_sdrc_rfr_ctrl:
216 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_C
217 omap243x_srs_prcm_voltctrl:
218 .word OMAP2430_PRCM_VOLTCTRL
219 ddr_prcm_mask_val:
220 .word 0xFFFF3FFC
221 omap243x_srs_timer_32ksynct:
222 .word OMAP2_L4_IO_ADDRESS(OMAP2430_32K
223
224 ENTRY(omap243x_sram_reprogram_sdrc_sz)
225 .word . - omap243x_sram_reprogram_sd
226
227 /*
228 * Set dividers and pll. Also recalculate DLL
229 */
230 .align 3
231 ENTRY(omap243x_sram_set_prcm)
232 stmfd sp!, {r0-r12, lr} @ regs
233 adr r4, pbegin @ addr
234 adr r8, pend @ addr
235 mcrr p15, 1, r8, r4, c12 @ prel
236 pbegin:
237 /* move into fast relock bypass */
238 ldr r8, omap243x_ssp_pll_ctl
239 ldr r5, [r8] @ get
240 mvn r6, #0x3 @ clea
241 and r5, r5, r6 @ clea
242 orr r7, r5, #0x2 @ fast
243 str r7, [r8] @ go t
244 ldr r4, omap243x_ssp_pll_stat
245 block:
246 /* wait for bypass */
247 ldr r8, [r4] @ stat
248 and r8, r8, #0x3 @ mask
249 cmp r8, #0x1 @ ther
250 bne block @ loop
251
252 /* set new dpll dividers _after_ in by
253 ldr r4, omap243x_ssp_pll_div
254 str r0, [r4] @ set
255
256 ldr r4, omap243x_ssp_set_config
257 mov r8, #1 @ vali
258 str r8, [r4] @ make
259
260 mov r4, #100 @ dead
261 wait_a_bit:
262 subs r4, r4, #1 @ dec
263 bne wait_a_bit @ dela
264
265 /* check if staying in bypass */
266 cmp r2, #0x1 @ stay
267 beq pend @ jump
268
269 /* relock DPLL with new vals */
270 ldr r5, omap243x_ssp_pll_stat
271 ldr r4, omap243x_ssp_pll_ctl
272 orr r8, r7, #0x3 @ val
273 str r8, [r4] @ set
274 mov r0, #1000 @ dead
275 wait_more:
276 subs r0, r0, #1 @ dec
277 bne wait_more @ dela
278 wait_lock:
279 ldr r8, [r5] @ get
280 and r8, r8, #3 @ isol
281 cmp r8, #2 @ lock
282 bne wait_lock @ wait
283 pend:
284 /* update memory timings & briefly loc
285 ldr r4, omap243x_ssp_sdrc_rfr
286 str r1, [r4] @ upda
287 ldr r11, omap243x_ssp_dlla_ctrl
288 ldr r10, [r11] @ get
289 mvn r9, #0x4 @ mask
290 and r10, r10, r9 @ clea
291 orr r10, r10, #0x8 @ make
292 str r10, [r11] @ comm
293 add r11, r11, #0x8 @ move
294 str r10, [r11] @ hit
295
296 mov r4, #0x800 @ relo
297 wait_dll_lock:
298 subs r4, r4, #0x1
299 bne wait_dll_lock
300 nop
301 ldmfd sp!, {r0-r12, pc} @ rest
302
303 omap243x_ssp_set_config:
304 .word OMAP2430_PRCM_CLKCFG_CTRL
305 omap243x_ssp_pll_ctl:
306 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_
307 omap243x_ssp_pll_stat:
308 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_
309 omap243x_ssp_pll_div:
310 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_
311 omap243x_ssp_sdrc_rfr:
312 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_C
313 omap243x_ssp_dlla_ctrl:
314 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_
315
316 ENTRY(omap243x_sram_set_prcm_sz)
317 .word . - omap243x_sram_set_prcm
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