1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 #ifndef _ASM_ARCH_PXA27X_UDC_H 3 #define _ASM_ARCH_PXA27X_UDC_H 4 5 #include "pxa-regs.h" 6 7 #ifdef _ASM_ARCH_PXA25X_UDC_H 8 #error You cannot include both PXA25x and PXA2 9 #endif 10 11 #define UDCCR __REG(0x40600000) /* U 12 #define UDCCR_OEN (1 << 31) /* On- 13 #define UDCCR_AALTHNP (1 << 30) /* A-d 14 Pro 15 #define UDCCR_AHNP (1 << 29) /* A-d 16 Sup 17 #define UDCCR_BHNP (1 << 28) /* B-d 18 Ena 19 #define UDCCR_DWRE (1 << 16) /* Dev 20 #define UDCCR_ACN (0x03 << 11) /* Act 21 #define UDCCR_ACN_S 11 22 #define UDCCR_AIN (0x07 << 8) /* Act 23 #define UDCCR_AIN_S 8 24 #define UDCCR_AAISN (0x07 << 5) /* Act 25 Set 26 #define UDCCR_AAISN_S 5 27 #define UDCCR_SMAC (1 << 4) /* Swi 28 Con 29 #define UDCCR_EMCE (1 << 3) /* End 30 Err 31 #define UDCCR_UDR (1 << 2) /* UDC 32 #define UDCCR_UDA (1 << 1) /* UDC 33 #define UDCCR_UDE (1 << 0) /* UDC 34 35 #define UDCICR0 __REG(0x40600004) /* U 36 #define UDCICR1 __REG(0x40600008) /* U 37 #define UDCICR_FIFOERR (1 << 1) /* FIF 38 #define UDCICR_PKTCOMPL (1 << 0) /* Pac 39 40 #define UDC_INT_FIFOERROR (0x2) 41 #define UDC_INT_PACKETCMP (0x1) 42 43 #define UDCICR_INT(n,intr) (((intr) & 0x03) << 44 #define UDCICR1_IECC (1 << 31) /* Int 45 #define UDCICR1_IESOF (1 << 30) /* Int 46 #define UDCICR1_IERU (1 << 29) /* Int 47 #define UDCICR1_IESU (1 << 28) /* Int 48 #define UDCICR1_IERS (1 << 27) /* Int 49 50 #define UDCISR0 __REG(0x4060000C) /* U 51 #define UDCISR1 __REG(0x40600010) /* U 52 #define UDCISR_INT(n,intr) (((intr) & 0x03) << 53 #define UDCISR1_IRCC (1 << 31) /* Int 54 #define UDCISR1_IRSOF (1 << 30) /* Int 55 #define UDCISR1_IRRU (1 << 29) /* Int 56 #define UDCISR1_IRSU (1 << 28) /* Int 57 #define UDCISR1_IRRS (1 << 27) /* Int 58 59 #define UDCFNR __REG(0x40600014) /* U 60 #define UDCOTGICR __REG(0x40600018) /* U 61 #define UDCOTGICR_IESF (1 << 24) /* OTG 62 #define UDCOTGICR_IEXR (1 << 17) /* Ext 63 Ris 64 #define UDCOTGICR_IEXF (1 << 16) /* Ext 65 Fal 66 #define UDCOTGICR_IEVV40R (1 << 9) /* OTG 67 Int 68 #define UDCOTGICR_IEVV40F (1 << 8) /* OTG 69 Int 70 #define UDCOTGICR_IEVV44R (1 << 7) /* OTG 71 Int 72 #define UDCOTGICR_IEVV44F (1 << 6) /* OTG 73 Int 74 #define UDCOTGICR_IESVR (1 << 5) /* OTG 75 Int 76 #define UDCOTGICR_IESVF (1 << 4) /* OTG 77 Int 78 #define UDCOTGICR_IESDR (1 << 3) /* OTG 79 Edg 80 #define UDCOTGICR_IESDF (1 << 2) /* OTG 81 Edg 82 #define UDCOTGICR_IEIDR (1 << 1) /* OTG 83 Int 84 #define UDCOTGICR_IEIDF (1 << 0) /* OTG 85 Int 86 87 #define UP2OCR __REG(0x40600020) / 88 #define UP3OCR __REG(0x40600024) / 89 90 #define UP2OCR_CPVEN (1 << 0) /* Cha 91 #define UP2OCR_CPVPE (1 << 1) /* Cha 92 #define UP2OCR_DPPDE (1 << 2) /* Hos 93 #define UP2OCR_DMPDE (1 << 3) /* Hos 94 #define UP2OCR_DPPUE (1 << 4) /* Hos 95 #define UP2OCR_DMPUE (1 << 5) /* Hos 96 #define UP2OCR_DPPUBE (1 << 6) /* Hos 97 #define UP2OCR_DMPUBE (1 << 7) /* Hos 98 #define UP2OCR_EXSP (1 << 8) 99 #define UP2OCR_EXSUS (1 << 9) /* Ext 100 #define UP2OCR_IDON (1 << 10) 101 #define UP2OCR_HXS (1 << 16) 102 #define UP2OCR_HXOE (1 << 17) 103 #define UP2OCR_SEOS(x) ((x & 7) << 24 104 105 #define UDCCSN(x) __REG2(0x40600100, (x) 106 #define UDCCSR0 __REG(0x40600100) /* U 107 #define UDCCSR0_SA (1 << 7) /* Set 108 #define UDCCSR0_RNE (1 << 6) /* Rec 109 #define UDCCSR0_FST (1 << 5) /* For 110 #define UDCCSR0_SST (1 << 4) /* Sen 111 #define UDCCSR0_DME (1 << 3) /* DMA 112 #define UDCCSR0_FTF (1 << 2) /* Flu 113 #define UDCCSR0_IPR (1 << 1) /* IN 114 #define UDCCSR0_OPC (1 << 0) /* OUT 115 116 #define UDCCSRA __REG(0x40600104) /* U 117 #define UDCCSRB __REG(0x40600108) /* U 118 #define UDCCSRC __REG(0x4060010C) /* U 119 #define UDCCSRD __REG(0x40600110) /* U 120 #define UDCCSRE __REG(0x40600114) /* U 121 #define UDCCSRF __REG(0x40600118) /* U 122 #define UDCCSRG __REG(0x4060011C) /* U 123 #define UDCCSRH __REG(0x40600120) /* U 124 #define UDCCSRI __REG(0x40600124) /* U 125 #define UDCCSRJ __REG(0x40600128) /* U 126 #define UDCCSRK __REG(0x4060012C) /* U 127 #define UDCCSRL __REG(0x40600130) /* U 128 #define UDCCSRM __REG(0x40600134) /* U 129 #define UDCCSRN __REG(0x40600138) /* U 130 #define UDCCSRP __REG(0x4060013C) /* U 131 #define UDCCSRQ __REG(0x40600140) /* U 132 #define UDCCSRR __REG(0x40600144) /* U 133 #define UDCCSRS __REG(0x40600148) /* U 134 #define UDCCSRT __REG(0x4060014C) /* U 135 #define UDCCSRU __REG(0x40600150) /* U 136 #define UDCCSRV __REG(0x40600154) /* U 137 #define UDCCSRW __REG(0x40600158) /* U 138 #define UDCCSRX __REG(0x4060015C) /* U 139 140 #define UDCCSR_DPE (1 << 9) /* Dat 141 #define UDCCSR_FEF (1 << 8) /* Flu 142 #define UDCCSR_SP (1 << 7) /* Sho 143 #define UDCCSR_BNE (1 << 6) /* Buf 144 #define UDCCSR_BNF (1 << 6) /* Buf 145 #define UDCCSR_FST (1 << 5) /* For 146 #define UDCCSR_SST (1 << 4) /* Sen 147 #define UDCCSR_DME (1 << 3) /* DMA 148 #define UDCCSR_TRN (1 << 2) /* Tx/ 149 #define UDCCSR_PC (1 << 1) /* Pac 150 #define UDCCSR_FS (1 << 0) /* FIF 151 152 #define UDCBCN(x) __REG2(0x40600200, (x) 153 #define UDCBCR0 __REG(0x40600200) /* B 154 #define UDCBCRA __REG(0x40600204) /* B 155 #define UDCBCRB __REG(0x40600208) /* B 156 #define UDCBCRC __REG(0x4060020C) /* B 157 #define UDCBCRD __REG(0x40600210) /* B 158 #define UDCBCRE __REG(0x40600214) /* B 159 #define UDCBCRF __REG(0x40600218) /* B 160 #define UDCBCRG __REG(0x4060021C) /* B 161 #define UDCBCRH __REG(0x40600220) /* B 162 #define UDCBCRI __REG(0x40600224) /* B 163 #define UDCBCRJ __REG(0x40600228) /* B 164 #define UDCBCRK __REG(0x4060022C) /* B 165 #define UDCBCRL __REG(0x40600230) /* B 166 #define UDCBCRM __REG(0x40600234) /* B 167 #define UDCBCRN __REG(0x40600238) /* B 168 #define UDCBCRP __REG(0x4060023C) /* B 169 #define UDCBCRQ __REG(0x40600240) /* B 170 #define UDCBCRR __REG(0x40600244) /* B 171 #define UDCBCRS __REG(0x40600248) /* B 172 #define UDCBCRT __REG(0x4060024C) /* B 173 #define UDCBCRU __REG(0x40600250) /* B 174 #define UDCBCRV __REG(0x40600254) /* B 175 #define UDCBCRW __REG(0x40600258) /* B 176 #define UDCBCRX __REG(0x4060025C) /* B 177 178 #define UDCDN(x) __REG2(0x40600300, (x) 179 #define PHYS_UDCDN(x) (0x40600300 + ((x)<<2) 180 #define PUDCDN(x) (volatile u32 *)(io_p2 181 #define UDCDR0 __REG(0x40600300) /* D 182 #define UDCDRA __REG(0x40600304) /* D 183 #define UDCDRB __REG(0x40600308) /* D 184 #define UDCDRC __REG(0x4060030C) /* D 185 #define UDCDRD __REG(0x40600310) /* D 186 #define UDCDRE __REG(0x40600314) /* D 187 #define UDCDRF __REG(0x40600318) /* D 188 #define UDCDRG __REG(0x4060031C) /* D 189 #define UDCDRH __REG(0x40600320) /* D 190 #define UDCDRI __REG(0x40600324) /* D 191 #define UDCDRJ __REG(0x40600328) /* D 192 #define UDCDRK __REG(0x4060032C) /* D 193 #define UDCDRL __REG(0x40600330) /* D 194 #define UDCDRM __REG(0x40600334) /* D 195 #define UDCDRN __REG(0x40600338) /* D 196 #define UDCDRP __REG(0x4060033C) /* D 197 #define UDCDRQ __REG(0x40600340) /* D 198 #define UDCDRR __REG(0x40600344) /* D 199 #define UDCDRS __REG(0x40600348) /* D 200 #define UDCDRT __REG(0x4060034C) /* D 201 #define UDCDRU __REG(0x40600350) /* D 202 #define UDCDRV __REG(0x40600354) /* D 203 #define UDCDRW __REG(0x40600358) /* D 204 #define UDCDRX __REG(0x4060035C) /* D 205 206 #define UDCCN(x) __REG2(0x40600400, (x)< 207 #define UDCCRA __REG(0x40600404) /* C 208 #define UDCCRB __REG(0x40600408) /* C 209 #define UDCCRC __REG(0x4060040C) /* C 210 #define UDCCRD __REG(0x40600410) /* C 211 #define UDCCRE __REG(0x40600414) /* C 212 #define UDCCRF __REG(0x40600418) /* C 213 #define UDCCRG __REG(0x4060041C) /* C 214 #define UDCCRH __REG(0x40600420) /* C 215 #define UDCCRI __REG(0x40600424) /* C 216 #define UDCCRJ __REG(0x40600428) /* C 217 #define UDCCRK __REG(0x4060042C) /* C 218 #define UDCCRL __REG(0x40600430) /* C 219 #define UDCCRM __REG(0x40600434) /* C 220 #define UDCCRN __REG(0x40600438) /* C 221 #define UDCCRP __REG(0x4060043C) /* C 222 #define UDCCRQ __REG(0x40600440) /* C 223 #define UDCCRR __REG(0x40600444) /* C 224 #define UDCCRS __REG(0x40600448) /* C 225 #define UDCCRT __REG(0x4060044C) /* C 226 #define UDCCRU __REG(0x40600450) /* C 227 #define UDCCRV __REG(0x40600454) /* C 228 #define UDCCRW __REG(0x40600458) /* C 229 #define UDCCRX __REG(0x4060045C) /* C 230 231 #define UDCCONR_CN (0x03 << 25) /* Con 232 #define UDCCONR_CN_S (25) 233 #define UDCCONR_IN (0x07 << 22) /* Int 234 #define UDCCONR_IN_S (22) 235 #define UDCCONR_AISN (0x07 << 19) /* Alt 236 #define UDCCONR_AISN_S (19) 237 #define UDCCONR_EN (0x0f << 15) /* End 238 #define UDCCONR_EN_S (15) 239 #define UDCCONR_ET (0x03 << 13) /* End 240 #define UDCCONR_ET_S (13) 241 #define UDCCONR_ET_INT (0x03 << 13) /* I 242 #define UDCCONR_ET_BULK (0x02 << 13) /* B 243 #define UDCCONR_ET_ISO (0x01 << 13) /* I 244 #define UDCCONR_ET_NU (0x00 << 13) /* N 245 #define UDCCONR_ED (1 << 12) /* End 246 #define UDCCONR_MPS (0x3ff << 2) /* Max 247 #define UDCCONR_MPS_S (2) 248 #define UDCCONR_DE (1 << 1) /* Dou 249 #define UDCCONR_EE (1 << 0) /* End 250 251 252 #define UDC_INT_FIFOERROR (0x2) 253 #define UDC_INT_PACKETCMP (0x1) 254 255 #define UDC_FNR_MASK (0x7ff) 256 257 #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FS 258 #define UDC_BCR_MASK (0x3ff) 259 260 #endif 261
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