1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * arch/arm/mach-pxa/include/mach/pxa2xx-regs 4 * 5 * Taken from pxa-regs.h by Russell King 6 * 7 * Author: Nicolas Pitre 8 * Copyright: MontaVista Software Inc. 9 */ 10 11 #ifndef __PXA2XX_REGS_H 12 #define __PXA2XX_REGS_H 13 14 #include "pxa-regs.h" 15 16 /* 17 * Power Manager 18 */ 19 20 #define PMCR __REG(0x40F00000) /* 21 #define PSSR __REG(0x40F00004) /* 22 #define PSPR __REG(0x40F00008) /* 23 #define PWER __REG(0x40F0000C) /* 24 #define PRER __REG(0x40F00010) /* 25 #define PFER __REG(0x40F00014) /* 26 #define PEDR __REG(0x40F00018) /* 27 #define PCFR __REG(0x40F0001C) /* 28 #define PGSR0 __REG(0x40F00020) /* 29 #define PGSR1 __REG(0x40F00024) /* 30 #define PGSR2 __REG(0x40F00028) /* 31 #define PGSR3 __REG(0x40F0002C) /* 32 #define RCSR __REG(0x40F00030) /* 33 34 #define PSLR __REG(0x40F00034) 35 #define PSTR __REG(0x40F00038) 36 #define PSNR __REG(0x40F0003C) 37 #define PVCR __REG(0x40F00040) 38 #define PKWR __REG(0x40F00050) 39 #define PKSR __REG(0x40F00054) 40 #define PCMD(x) __REG2(0x40F00080, (x)<<2) 41 #define PCMD0 __REG(0x40F00080 + 0 * 4) 42 #define PCMD1 __REG(0x40F00080 + 1 * 4) 43 #define PCMD2 __REG(0x40F00080 + 2 * 4) 44 #define PCMD3 __REG(0x40F00080 + 3 * 4) 45 #define PCMD4 __REG(0x40F00080 + 4 * 4) 46 #define PCMD5 __REG(0x40F00080 + 5 * 4) 47 #define PCMD6 __REG(0x40F00080 + 6 * 4) 48 #define PCMD7 __REG(0x40F00080 + 7 * 4) 49 #define PCMD8 __REG(0x40F00080 + 8 * 4) 50 #define PCMD9 __REG(0x40F00080 + 9 * 4) 51 #define PCMD10 __REG(0x40F00080 + 10 * 4) 52 #define PCMD11 __REG(0x40F00080 + 11 * 4) 53 #define PCMD12 __REG(0x40F00080 + 12 * 4) 54 #define PCMD13 __REG(0x40F00080 + 13 * 4) 55 #define PCMD14 __REG(0x40F00080 + 14 * 4) 56 #define PCMD15 __REG(0x40F00080 + 15 * 4) 57 #define PCMD16 __REG(0x40F00080 + 16 * 4) 58 #define PCMD17 __REG(0x40F00080 + 17 * 4) 59 #define PCMD18 __REG(0x40F00080 + 18 * 4) 60 #define PCMD19 __REG(0x40F00080 + 19 * 4) 61 #define PCMD20 __REG(0x40F00080 + 20 * 4) 62 #define PCMD21 __REG(0x40F00080 + 21 * 4) 63 #define PCMD22 __REG(0x40F00080 + 22 * 4) 64 #define PCMD23 __REG(0x40F00080 + 23 * 4) 65 #define PCMD24 __REG(0x40F00080 + 24 * 4) 66 #define PCMD25 __REG(0x40F00080 + 25 * 4) 67 #define PCMD26 __REG(0x40F00080 + 26 * 4) 68 #define PCMD27 __REG(0x40F00080 + 27 * 4) 69 #define PCMD28 __REG(0x40F00080 + 28 * 4) 70 #define PCMD29 __REG(0x40F00080 + 29 * 4) 71 #define PCMD30 __REG(0x40F00080 + 30 * 4) 72 #define PCMD31 __REG(0x40F00080 + 31 * 4) 73 74 #define PCMD_MBC (1<<12) 75 #define PCMD_DCE (1<<11) 76 #define PCMD_LC (1<<10) 77 /* FIXME: PCMD_SQC need be checked. */ 78 #define PCMD_SQC (3<<8) /* currently o 79 bit 9 shoul 80 #define PVCR_VCSA (0x1<<14) 81 #define PVCR_CommandDelay (0xf80) 82 #define PCFR_PI2C_EN (0x1 << 6) 83 84 #define PSSR_OTGPH (1 << 6) /* OTG 85 #define PSSR_RDH (1 << 5) /* Rea 86 #define PSSR_PH (1 << 4) /* Per 87 #define PSSR_STS (1 << 3) /* Sta 88 #define PSSR_VFS (1 << 2) /* VDD 89 #define PSSR_BFS (1 << 1) /* Bat 90 #define PSSR_SSS (1 << 0) /* Sof 91 92 #define PSLR_SL_ROD (1 << 20) /* Sle 93 94 #define PCFR_RO (1 << 15) /* RDH 95 #define PCFR_PO (1 << 14) /* PH 96 #define PCFR_GPROD (1 << 12) /* GPI 97 #define PCFR_L1_EN (1 << 11) /* Sle 98 #define PCFR_FVC (1 << 10) /* Fre 99 #define PCFR_DC_EN (1 << 7) /* Sle 100 #define PCFR_PI2CEN (1 << 6) /* Ena 101 #define PCFR_GPR_EN (1 << 4) /* nRE 102 #define PCFR_DS (1 << 3) /* Dee 103 #define PCFR_FS (1 << 2) /* Flo 104 #define PCFR_FP (1 << 1) /* Flo 105 #define PCFR_OPDE (1 << 0) /* 3.6 106 107 #define RCSR_GPR (1 << 3) /* GPI 108 #define RCSR_SMR (1 << 2) /* Sle 109 #define RCSR_WDR (1 << 1) /* Wat 110 #define RCSR_HWR (1 << 0) /* Har 111 112 #define PWER_GPIO(Nb) (1 << Nb) /* GPI 113 #define PWER_GPIO0 PWER_GPIO (0) /* GPI 114 #define PWER_GPIO1 PWER_GPIO (1) /* GPI 115 #define PWER_GPIO2 PWER_GPIO (2) /* GPI 116 #define PWER_GPIO3 PWER_GPIO (3) /* GPI 117 #define PWER_GPIO4 PWER_GPIO (4) /* GPI 118 #define PWER_GPIO5 PWER_GPIO (5) /* GPI 119 #define PWER_GPIO6 PWER_GPIO (6) /* GPI 120 #define PWER_GPIO7 PWER_GPIO (7) /* GPI 121 #define PWER_GPIO8 PWER_GPIO (8) /* GPI 122 #define PWER_GPIO9 PWER_GPIO (9) /* GPI 123 #define PWER_GPIO10 PWER_GPIO (10) /* GPI 124 #define PWER_GPIO11 PWER_GPIO (11) /* GPI 125 #define PWER_GPIO12 PWER_GPIO (12) /* GPI 126 #define PWER_GPIO13 PWER_GPIO (13) /* GPI 127 #define PWER_GPIO14 PWER_GPIO (14) /* GPI 128 #define PWER_GPIO15 PWER_GPIO (15) /* GPI 129 #define PWER_RTC 0x80000000 /* RTC 130 131 /* 132 * PXA2xx specific Core clock definitions 133 */ 134 #define CCCR io_p2v(0x41300000) /* 135 #define CCSR io_p2v(0x4130000C) /* 136 #define CKEN io_p2v(0x41300004) /* 137 #define OSCC io_p2v(0x41300008) /* 138 139 #define OSCC_OON (1 << 1) /* 32. 140 #define OSCC_OOK (1 << 0) /* 32. 141 142 /* PWRMODE register M field values */ 143 144 #define PWRMODE_IDLE 0x1 145 #define PWRMODE_STANDBY 0x2 146 #define PWRMODE_SLEEP 0x3 147 #define PWRMODE_DEEPSLEEP 0x7 148 149 #endif 150
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